package xiangshan.backend.decode.isa

import chisel3.util._
import xiangshan.backend._
import xiangshan.HasXSParameter
import xiangshan.FuType._
import xiangshan.backend.decode._
import xiangshan.backend.fu.fpu.FPUOpType._

object RVFInstr extends HasXSParameter with HasInstrType {

  def FLW                = BitPat("b?????????????????010?????0000111")
  def FSW                = BitPat("b?????????????????010?????0100111")
  def FADD_S             = BitPat("b0000000??????????????????1010011")
  def FSUB_S             = BitPat("b0000100??????????????????1010011")
  def FMUL_S             = BitPat("b0001000??????????????????1010011")
  def FDIV_S             = BitPat("b0001100??????????????????1010011")
  def FSGNJ_S            = BitPat("b0010000??????????000?????1010011")
  def FSGNJN_S           = BitPat("b0010000??????????001?????1010011")
  def FSGNJX_S           = BitPat("b0010000??????????010?????1010011")
  def FMIN_S             = BitPat("b0010100??????????000?????1010011")
  def FMAX_S             = BitPat("b0010100??????????001?????1010011")
  def FSQRT_S            = BitPat("b010110000000?????????????1010011")
  def FLE_S              = BitPat("b1010000??????????000?????1010011")
  def FLT_S              = BitPat("b1010000??????????001?????1010011")
  def FEQ_S              = BitPat("b1010000??????????010?????1010011")
  def FCVT_W_S           = BitPat("b110000000000?????????????1010011")
  def FCVT_WU_S          = BitPat("b110000000001?????????????1010011")
  def FCVT_L_S           = BitPat("b110000000010?????????????1010011")
  def FCVT_LU_S          = BitPat("b110000000011?????????????1010011")
  def FMV_X_W            = BitPat("b111000000000?????000?????1010011")
  def FCLASS_S           = BitPat("b111000000000?????001?????1010011")
  def FCVT_S_W           = BitPat("b110100000000?????????????1010011")
  def FCVT_S_WU          = BitPat("b110100000001?????????????1010011")
  def FCVT_S_L           = BitPat("b110100000010?????????????1010011")
  def FCVT_S_LU          = BitPat("b110100000011?????????????1010011")
  def FMV_W_X            = BitPat("b111100000000?????000?????1010011")
  def FMADD_S            = BitPat("b?????00??????????????????1000011")
  def FMSUB_S            = BitPat("b?????00??????????????????1000111")
  def FNMSUB_S           = BitPat("b?????00??????????????????1001011")
  def FNMADD_S           = BitPat("b?????00??????????????????1001111")

  val table = Array(
    FLW -> List(InstrFI, ldu, LSUOpType.flw),
    FSW -> List(InstrFS, stu, LSUOpType.sw),

    // FR
    FADD_S    -> List(InstrFR, fmac,  fadd),
    FSUB_S    -> List(InstrFR, fmac,  fsub),
    FMUL_S    -> List(InstrFR, fmac,  fmul),
    FDIV_S    -> List(InstrFR, fmisc, fdiv),
    FMIN_S    -> List(InstrFR, fmisc, fmin),
    FMAX_S    -> List(InstrFR, fmisc, fmax),
    FSGNJ_S   -> List(InstrFR, fmisc, fsgnj),
    FSGNJN_S  -> List(InstrFR, fmisc, fsgnjn),
    FSGNJX_S  -> List(InstrFR, fmisc, fsgnjx),
    FSQRT_S   -> List(InstrFR, fmisc, fsqrt),
    FMADD_S   -> List(InstrFR, fmac,  fmadd),
    FNMADD_S  -> List(InstrFR, fmac,  fnmadd),
    FMSUB_S   -> List(InstrFR, fmac,  fmsub),
    FNMSUB_S  -> List(InstrFR, fmac,  fnmsub),

    // F -> G
    FCLASS_S  -> List(InstrFtoG, fmisc, fclass),
    FMV_X_W   -> List(InstrFtoG, fmisc, fmv_f2i),
    FCVT_W_S  -> List(InstrFtoG, fmisc, f2w),
    FCVT_WU_S -> List(InstrFtoG, fmisc, f2wu),
    FCVT_L_S  -> List(InstrFtoG, fmisc, f2l),
    FCVT_LU_S -> List(InstrFtoG, fmisc, f2lu),
    FLE_S     -> List(InstrFtoG, fmisc, fle),
    FLT_S     -> List(InstrFtoG, fmisc, flt),
    FEQ_S     -> List(InstrFtoG, fmisc, feq),

    // G -> F
    FMV_W_X   -> List(InstrGtoF, i2f, fmv_i2f),
    FCVT_S_W  -> List(InstrGtoF, i2f, w2f),
    FCVT_S_WU -> List(InstrGtoF, i2f, wu2f),
    FCVT_S_L  -> List(InstrGtoF, i2f, l2f),
    FCVT_S_LU -> List(InstrGtoF, i2f, lu2f)
  )
}
