Generate verilog files and compile them using verilator:
* Move to project root, run `make emu` to compile verilator simulator. You can use `make emu config=CONFIG_NAME` to choose different size of XiangShan.
* Move to project root, run `make emu` to compile verilator simulator. You can use `make emu CONFIG=CONFIG_NAME` to choose different size of XiangShan.
* To speed up compiling, use `make emu REMOTE=YOUR_REMOTE_SERVER`. (If you have remote server setuped)
Run program generated by verilator:
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@@ -39,7 +39,7 @@ Run program generated by verilator: