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提交
1d0717ae
编写于
1月 21, 2021
作者:
Z
zoujr
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
BPU: Fix uBtb and Btb bug
上级
a55ae586
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
8 addition
and
8 deletion
+8
-8
src/main/scala/utils/ExcitingUtils.scala
src/main/scala/utils/ExcitingUtils.scala
+1
-1
src/main/scala/xiangshan/backend/fu/CSR.scala
src/main/scala/xiangshan/backend/fu/CSR.scala
+5
-5
src/main/scala/xiangshan/frontend/Btb.scala
src/main/scala/xiangshan/frontend/Btb.scala
+1
-1
src/main/scala/xiangshan/frontend/uBTB.scala
src/main/scala/xiangshan/frontend/uBTB.scala
+1
-1
未找到文件。
src/main/scala/utils/ExcitingUtils.scala
浏览文件 @
1d0717ae
...
...
@@ -59,7 +59,7 @@ object ExcitingUtils {
forceExists
:
Boolean
=
false
)
:
Unit
=
{
val
conn
=
map
.
getOrElseUpdate
(
name
,
new
Connection
(
connType
))
require
(
conn
.
sinkModule
.
isEmpty
)
//
require(conn.sinkModule.isEmpty)
require
(
conn
.
connType
==
connType
)
conn
.
sinkModule
=
Some
(
component
.
parentModName
)
BoringUtils
.
addSink
(
component
,
name
,
disableDedup
,
forceExists
)
...
...
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @
1d0717ae
...
...
@@ -803,7 +803,7 @@ class CSR extends FunctionUnit with HasCSRConst
"LoopExit"
->
(
0x102a
,
"perfCntLoopExit"
),
"isReplay"
->
(
0x102b
,
"Replay"
),
// "FetchFromICache" -> (0x102a, "CntFetchFromICache"),
"ICacheMMIO"
->
(
0x102
a
,
"perfCntIcacheMMIOCnt"
),
"ICacheMMIO"
->
(
0x102
c
,
"perfCntIcacheMMIOCnt"
),
// "FetchFromLoopBuffer" -> (0x102b, "CntFetchFromLoopBuffer"),
// "ExitLoop1" -> (0x102c, "CntExitLoop1"),
// "ExitLoop2" -> (0x102d, "CntExitLoop2"),
...
...
@@ -820,19 +820,19 @@ class CSR extends FunctionUnit with HasCSRConst
// "L2cacheHit" -> (0x1023, "perfCntCondL2cacheHit")
)
++
(
(
0
until
dcacheParameters
.
nMissEntries
).
map
(
i
=>
(
"DCacheMissQueuePenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
2a
+
i
,
"perfCntDCacheMissQueuePenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
(
"DCacheMissQueuePenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
40
+
i
,
"perfCntDCacheMissQueuePenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
).
toMap
)
++
(
(
0
until
icacheParameters
.
nMissEntries
).
map
(
i
=>
(
"ICacheMissQueuePenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
2a
+
dcacheParameters
.
nMissEntries
+
i
,
"perfCntICacheMissQueuePenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
(
"ICacheMissQueuePenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
40
+
dcacheParameters
.
nMissEntries
+
i
,
"perfCntICacheMissQueuePenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
).
toMap
)
++
(
(
0
until
l1plusPrefetcherParameters
.
nEntries
).
map
(
i
=>
(
"L1+PrefetchPenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
2a
+
dcacheParameters
.
nMissEntries
+
icacheParameters
.
nMissEntries
+
i
,
"perfCntL1plusPrefetchPenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
(
"L1+PrefetchPenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
40
+
dcacheParameters
.
nMissEntries
+
icacheParameters
.
nMissEntries
+
i
,
"perfCntL1plusPrefetchPenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
).
toMap
)
++
(
(
0
until
l2PrefetcherParameters
.
nEntries
).
map
(
i
=>
(
"L2PrefetchPenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
2a
+
dcacheParameters
.
nMissEntries
+
icacheParameters
.
nMissEntries
+
l1plusPrefetcherParameters
.
nEntries
+
i
,
"perfCntL2PrefetchPenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
(
"L2PrefetchPenalty"
+
Integer
.
toString
(
i
,
10
),
(
0x10
40
+
dcacheParameters
.
nMissEntries
+
icacheParameters
.
nMissEntries
+
l1plusPrefetcherParameters
.
nEntries
+
i
,
"perfCntL2PrefetchPenaltyEntry"
+
Integer
.
toString
(
i
,
10
)))
).
toMap
)
...
...
src/main/scala/xiangshan/frontend/Btb.scala
浏览文件 @
1d0717ae
...
...
@@ -189,7 +189,7 @@ class BTB extends BasePredictor with BTBParams{
val
dataWrite
=
BtbDataEntry
(
new_lower
,
new_extended
)
val
jalFirstEncountered
=
!
u
.
isMisPred
&&
!
u
.
bpuMeta
.
btbHitJal
&&
updateType
===
BTBtype
.
J
val
updateValid
=
io
.
update
.
valid
&&
(
u
.
isMisPred
||
jalFirstEncountered
)
&&
!
u
.
isReplay
val
updateValid
=
io
.
update
.
bits
.
taken
&&
io
.
update
.
valid
&&
(
u
.
isMisPred
||
jalFirstEncountered
)
&&
!
u
.
isReplay
// Update btb
for
(
w
<-
0
until
BtbWays
)
{
for
(
b
<-
0
until
BtbBanks
)
{
...
...
src/main/scala/xiangshan/frontend/uBTB.scala
浏览文件 @
1d0717ae
...
...
@@ -229,7 +229,7 @@ class MicroBTB extends BasePredictor
val
jalFirstEncountered
=
!
u
.
isMisPred
&&
!
u
.
bpuMeta
.
btbHitJal
&&
(
u
.
pd
.
brType
===
BrType
.
jal
)
val
entry_write_valid
=
io
.
update
.
valid
&&
(
u
.
isMisPred
||
jalFirstEncountered
)
&&
!
u
.
isReplay
//io.update.valid //&& update_is_BR_or_JAL
val
entry_write_valid
=
io
.
update
.
valid
&&
update_taken
&&
(
u
.
isMisPred
||
jalFirstEncountered
)
&&
!
u
.
isReplay
//io.update.valid //&& update_is_BR_or_JAL
val
meta_write_valid
=
io
.
update
.
valid
&&
(
u
.
isMisPred
||
jalFirstEncountered
)
&&
!
u
.
isReplay
//io.update.valid //&& update_is_BR_or_JAL
for
(
b
<-
0
until
PredictWidth
)
{
...
...
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