readme: update readme

README.md

 # XiangShan
 
-XiangShan is an open-source high-performance RISC-V processor.
+XiangShan (香山) is an open-source high-performance RISC-V processor project. 
 
-NOTE: XiangShan has not been officially released to the public open-source community.
-License and docs to be added later.
+Detailed documents will be released in the near future.
 
 Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
 
-## Prepare environment
+
+
+## === Tutorial is Comming! ===
+
+A tutorial on XiangShan is held at RISC-V World Conference China 2021 in June.  Multiple technical reports will be included in the conference as well. Stay tuned!
+
+For more information, please refer to [this link](https://openxiangshan.github.io).
+
+
+
+## Architecture
+
+The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June, 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on master branch.
+
+The micro-architecture overview is shown below.
+
+![xs-arch-single](xs-arch-single.svg)
+
+
+
+## Sub-directories Overview
+
+Some of the key directories are shown below.
+
+```
+.
+├── fpga                   # supported FPGA boards and files to build a Vivado project
+├── read-to-run            # pre-built simulation images
+├── scripts                # scripts for agile development
+└── src
+    ├── test               # test files (including diff-test, module-test, etc.)
+    └── main/scala         # design files
+    		 ├── bus/tilelink  # tilelink utils
+    		 ├── device        # virtual device for simulation
+    		 ├── difftest      # diff-test chisel interface
+    		 ├── system        # SoC wrapper
+    		 ├── top           # top module
+    		 ├── utils         # utilization code
+    		 ├── xiangshan     # main design code
+    		 └── xstransforms  # some useful firrtl transforms
+```
+
+
+
+## Generate Verilog
+
+* Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`.
+* Refer to `Makefile` for more information.
+
+
+
+## Run Programs by Simulation
+
+### Prepare environment
 
 * Set environment variable `NEMU_HOME` to the **absolute path** of the [NEMU project](https://github.com/OpenXiangShan/NEMU).
 * Set environment variable `NOOP_HOME` to the **absolute path** of the XiangShan project.
 * Set environment variable `AM_HOME` to the **absolute path** of the [AM project](https://github.com/OpenXiangShan/nexus-am).
 * Install `mill`. Refer to [the Manual section in this guide](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation).
-* Run `make init` to initialize submodules.
+* Clone this project and run `make init` to initialize submodules.
 
-## Run simulation
+### Run with simulator
 
 * Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator.
 * Run `make emu` to build the C++ simulator `./build/emu` with Verilator.
@@ -28,6 +80,3 @@ make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
 ./build/emu -b 0 -e 0 -i $AM_HOME/apps/coremark/build/coremark-riscv64-noop.bin
 ```
 
-## Generate Verilog
-* Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`.
-* Refer to `Makefile` for more information.