diff --git a/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala b/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
index 84571e8b2a626b228a08d420421779c98f015853..132a2ce6d309154ed78b00c854c06b603fafafca 100644
--- a/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
@@ -138,7 +138,8 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, name: String)(implicit
   val loValidBitVec = Cat((0 until size).map(i => validBitVec(i) && headPtrMask(i)))
   val hiValidBitVec = Cat((0 until size).map(i => validBitVec(i) && ~headPtrMask(i)))
   val flippedFlag = loValidBitVec.orR || validBitVec(size - 1)
-  val lastOneIndex = size.U - PriorityEncoder(Mux(loValidBitVec.orR, loValidBitVec, hiValidBitVec))
+  val leadingZeros = PriorityEncoder(Mux(loValidBitVec.orR, loValidBitVec, hiValidBitVec))
+  val lastOneIndex = Mux(leadingZeros === 0.U, 0.U, size.U - leadingZeros)
   val walkedTailPtr = Wire(new DispatchQueuePtr)
   walkedTailPtr.flag := flippedFlag ^ headPtr(0).flag
   walkedTailPtr.value := lastOneIndex