Update README.md and add a simplified Chinese version (#850)

* Add ZH-Hans readme.md and fix some grammar issues in english readme
Signed-off-by: NClSlaid <cailue@bupt.edu.cn>

* Typo fixes in ZH-Hans.md
Signed-off-by: NClSlaid <cailue@bupt.edu.cn>

* Add link to zh-hans in readme
Signed-off-by: NClSlaid <cailue@bupt.edu.cn>

README-ZH-HANS.md

+# 香山
+
+香山是一款开源的高性能 RISC-V 处理器。采用 Chisel 硬件设计语言开发，支持 RV64GC 指令集。
+
+详细文档将在未来放出。
+English Readme is [here](README.md).
+
+©2020-2021 中国科学院计算技术研究所版权所有。
+
+## === 教程即将登场 ===
+
+香山的教程将于 2021 年 6 月的 [RISC-V 中国峰会](https://www.riscv-conf-china.com/cn/index.html)上放出。峰会群贤毕至，少长咸集，更有诸多科技报告以飨诸君。敬请期待！
+
+详见[香山官方网站](https://openxiangshan.github.io)。
+
+## 处理器架构
+
+自 2020 年 6 月开始开发的[雁栖湖](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu)为香山处理器的首个稳定的微架构。目前版本的香山（即南湖）正在 master 分支上不断开发中。
+
+微架构概览：
+![xs-arch-single](xs-arch-simple.svg)
+
+## 目录概览
+
+以下是一些关键目录：
+
+```
+.
+├── fpga                   # 支持的 FPGA 开发板、用于构建 Vivado 项目的文件
+├── read-to-run            # 预建的仿真镜像文件
+├── scripts                # 用于敏捷开发的脚本文件
+└── src
+    ├── test               # 测试文件（包括差异测试（diff-test）和模块测试（module-test） 等）
+    └── main/scala         # 设计文件
+        ├── bus/tilelink   # tilelink 实用工具
+        ├── device         # 用于仿真的虚拟设备
+        ├── difftest       # chisel 差异测试接口
+        ├── system         # SoC 封装
+        ├── top            # 顶层模块
+        ├── utils          # 复用封装
+        ├── xiangshan      # 主体设计代码
+        └── xstransforms   # 一些实用的 firrtl 变换代码
+```
+
+## 生成 Verilog
+
+* 运行 `make verilog` 以生成 verilog 代码。输出文件为 `build/XSTop.v`。
+* 更多信息详见 `Makefile`。
+
+## 仿真运行
+
+### 环境搭建
+
+* 设定环境变量 `NEMU_HOME` 为[香山 NEMU](https://github.com/OpenXiangShan/NEMU) 在您机器上的绝对路径。
+* 设定环境变量 `NOOP_HOME` 为香山工程文件夹的绝对路径。
+* 设定环境变量 `AM_HOME` 为[香山 AM](https://github.com/OpenXiangShan/nexus-am) 的绝对路径。
+* 项目使用 `mill` 进行 scala 编译，因此需要安装 `mill`，详见 [mill 手动安装指南](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation)（目前仅英文版本）。
+* 克隆本项目，运行 `make init` 以初始化本项目引用的开源子模块。
+
+### 运行仿真
+
+* 安装开源 verilog 仿真器 [Verilator](https://verilator.org/guide/latest/)。
+* 运行 `make emu` 以利用 Verilator 构建 C++ 仿真器 `./build/emu`。
+* 运行 `./build/emu --help` 可以获得仿真器的各种运行时参数。
+* 更多细节详见 `Makefile` 与 `verilator.mk`。
+
+运行示例：
+
+```bash
+make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
+./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
+```
+
+## 致谢
+
+在香山的开发过程中，我们采用了来自开源社区的子模块。具体情况如下：
+
+| 子模块         | 来源                                                       | 详细用途                                                       |
+| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
+| L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | 我们增强了原模块的功能和时序，最终使之能胜任 L2/LLC 任务的缓存生成器 |
+| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | 我们复用了来自 rocket-chip 的外接框架和链接，来调度总线 |
+| FPU                | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | 我们使用了 Barkeley-hardfloat 作为浮点运算器并为之设计了 SRT-4 除法/开方运算单元。此外我们分割了 FMA 流水线以优化时序 |
+
+我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。:)

README.md

@@ -3,6 +3,7 @@
 XiangShan (香山) is an open-source high-performance RISC-V processor project. 
 
 Detailed documents will be released in the near future.
+中文说明[在此](README-ZH-HANS.md)。
 
 Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
 
@@ -18,7 +19,7 @@ For more information, please refer to [this link](https://openxiangshan.github.i
 
 ## Architecture
 
-The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June, 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on master branch.
+The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch.
 
 The micro-architecture overview is shown below.
 
@@ -75,22 +76,21 @@ Some of the key directories are shown below.
 * Refer to `Makefile` and `verilator.mk` for more information.
 
 Example:
+
 ```bash
 make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
 ```
 
-
-
 ## Acknowledgement
 
-In the development of XiangShan, some sub-modules from open source community are employed. All relevant usage is listed below.
+In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.
 
 | Sub-module         | Source                                                       | Detail                                                       |
 | ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
 | L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. |
 | Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
-| FPU                | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement a SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. |
+| FPU                | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement an SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. |
 
-We are grateful for the support of the open source community and encourage other open source projects to reuse our code within the scope of the [license](LICENSE).
+We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).