From 9e38a5d42184d57acfb78cfda6aea0d065c7f3d7 Mon Sep 17 00:00:00 2001
From: linjiawei <linjiav@outlook.com>
Date: Thu, 20 Aug 2020 20:09:37 +0800
Subject: [PATCH] update README.md

---
 Makefile  | 7 ++++++-
 README.md | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 87804100e..16fc37162 100644
--- a/Makefile
+++ b/Makefile
@@ -134,4 +134,9 @@ cache:
 clean:
 	rm -rf $(BUILD_DIR)
 
-.PHONY: verilog emu clean help $(REF_SO)
+init:
+	git submodule update --init
+	# do not use a recursive init to pull some not used submodules
+	cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat
+
+.PHONY: verilog emu clean help init $(REF_SO)
diff --git a/README.md b/README.md
index 320311565..a2db54f27 100644
--- a/README.md
+++ b/README.md
@@ -6,6 +6,7 @@ Currently it only supports riscv32.
 ## Compile chisel code
 
 * Install `mill`. Refer to [the Manual section in this guide][mill].
+* Run `make init` to init git submodules
 * Run `make` to generate verilog code. The output file is `build/TopMain.v`.
 
 [mill]: http://lihaoyi.com/mill#manual
-- 
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