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# XiangShan
XiangShan is a processor targeting super-scalar out-of-order execution.
Currently it supports riscv64GC.
XiangShan is an open-source high-performance RISC-V processor.
## Compile chisel code
NOTE: XiangShan has not been officially released to the public open-source community.
License and docs to be added later.
* Install `mill`. Refer to [the Manual section in this guide][mill].
* Run `make init` to init git submodules
* Run `make` to generate verilog code. The output file is `build/TopMain.v`.
Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
[mill]: http://lihaoyi.com/mill#manual
## Prepare environment
## Run programs by simulation
* Set environment variable `NEMU_HOME` to the **absolute path** of the [NEMU project](https://github.com/OpenXiangShan/NEMU).
* Set environment variable `NOOP_HOME` to the **absolute path** of the XiangShan project.
* Set environment variable `AM_HOME` to the **absolute path** of the [AM project](https://github.com/OpenXiangShan/nexus-am).
* Install `mill`. Refer to [the Manual section in this guide](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation).
* Run `make init` to initialize submodules.
### Prepare environment
## Run simulation
* Set a new environment variable `NEMU_HOME` to the **absolute path** of the NEMU project.
* Set a new environment variable `NOOP_HOME` to the **absolute path** of the XiangShan project.
* Clone the [AM project](https://github.com/NJU-ProjectN/nexus-am.git).
* Set a new environment variable `AM_HOME` to the **absolute path** of the AM project.
* Add a new AM `riscv64-noop` in the AM project if it is not provided.
### Verilator simulation
Install verilator:
TBD
Generate verilog files and compile them using verilator:
* Move to project root, run `make emu` to compile verilator simulator. You can use `make emu CONFIG=CONFIG_NAME` to choose different size of XiangShan.
* To speed up compiling, use `make emu REMOTE=YOUR_REMOTE_SERVER`. (If you have remote server setuped)
Run program generated by verilator:
* If compile succeed, you can run the application in the AM project by `make ARCH=riscv64-noop run`.
* Or you can run emulator and select image manually: `./build/emu -i PROGRAM_IMAGE`
* Use parameters to control emulator behavior: `./build/emu [-b DUMP_BEGIN_TIME] [-e DUMP_END_TIME] [--force-dump-result] [--dump-wave] -i PROGRAM_IMAGE`.
* Run `./build/emu` for further instructions.
* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator.
* Run `make emu` to build the C++ simulator `./build/emu` with Verilator.
* Refer to `./build/emu --help` for run-time arguments of the simulator.
* Refer to `Makefile` and `verilator.mk` for more information.
Example:
```makefile
make emu CONFIG=MinimalSimConfig
./build/emu -b 0 -e 0 --force-dump-reult -i ./mem.bin
```bash
make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i $AM_HOME/apps/coremark/build/coremark-riscv64-noop.bin
```
`debug` dir provides some scripts for verilator simulation.
### VCS simulation
Make sure you have VCS installed.
* Run `make simv` to compile vcs simulator.
* After that, run `./simv`
\ No newline at end of file
## Generate Verilog
* Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`.
* Refer to `Makefile` for more information.
......@@ -122,7 +122,11 @@ endif
EMU_FLAGS = -s $(SEED) -b $(B) -e $(E) $(SNAPSHOT_OPTION) $(WAVEFORM) $(EMU_ARGS)
emu: $(EMU)
emu-run: emu
ifneq ($(REMOTE),localhost)
ls build
endif
$(EMU) -i $(IMAGE) --diff=$(REF_SO) $(EMU_FLAGS)
coverage:
......
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