CSR: fix mip/sip implementation (#823)

* Only ssip in sip is writeable in smode
* Add sip write permission check
* Fix mipReg write logic

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -336,7 +336,8 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst
   val stvec = RegInit(UInt(XLEN.W), 0.U)
   // val sie = RegInit(0.U(XLEN.W))
   val sieMask = "h222".U & mideleg
-  val sipMask  = "h222".U & mideleg
+  val sipMask = "h222".U & mideleg
+  val sipWMask = "h2".U // ssip is writeable in smode
   val satp = if(EnbaleTlbDebug) RegInit(UInt(XLEN.W), "h8000000000087fbe".U) else RegInit(0.U(XLEN.W))
   // val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
   val satpMask = "h80000fffffffffff".U // disable asid, mode can only be 8 / 0
@@ -522,7 +523,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst
     MaskedRegMap(Sepc, sepc),
     MaskedRegMap(Scause, scause),
     MaskedRegMap(Stval, stval),
-    MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
+    MaskedRegMap(Sip, mip.asUInt, sipWMask, MaskedRegMap.Unwritable, sipMask),
 
     //--- Supervisor Protection and Translation ---
     MaskedRegMap(Satp, satp, satpMask, MaskedRegMap.NoSideEffect, satpMask),
@@ -634,10 +635,18 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst
   // Fix Mip/Sip write
   val fixMapping = Map(
     MaskedRegMap(Mip, mipReg.asUInt, mipFixMask),
-    MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask)
+    MaskedRegMap(Sip, mipReg.asUInt, sipWMask, MaskedRegMap.NoSideEffect, sipMask)
   )
-  val rdataDummy = Wire(UInt(XLEN.W))
-  MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen, wdata)
+  val rdataFix = Wire(UInt(XLEN.W))
+  val wdataFix = LookupTree(func, List(
+    CSROpType.wrt  -> src1,
+    CSROpType.set  -> (rdataFix | src1),
+    CSROpType.clr  -> (rdataFix & (~src1).asUInt()),
+    CSROpType.wrti -> csri,
+    CSROpType.seti -> (rdataFix | csri),
+    CSROpType.clri -> (rdataFix & (~csri).asUInt())
+  ))
+  MaskedRegMap.generate(fixMapping, addr, rdataFix, wen && permitted, wdataFix)
 
   when (csrio.fpu.fflags.valid) {
     fcsr := fflags_wfn(update = true)(csrio.fpu.fflags.bits)
@@ -773,6 +782,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst
   mipWire.t.m := csrio.externalInterrupt.mtip
   mipWire.s.m := csrio.externalInterrupt.msip
   mipWire.e.m := csrio.externalInterrupt.meip
+  mipWire.e.s := csrio.externalInterrupt.meip
 
   // interrupts
   val intrNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(intrVec(i), i.U, sum))