From b8bcc142afff3301369eaca6712b08d963a4e7d4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E6=A2=81=E6=A3=AE=20Liang=20Sen?= <liangsen20z@ict.ac.cn>
Date: Mon, 4 Sep 2023 15:56:03 +0800
Subject: [PATCH] Update makefile

---
 Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 8348b50c0..ab3263f02 100644
--- a/Makefile
+++ b/Makefile
@@ -79,7 +79,7 @@ $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
 	time -o $(@D)/time.log mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \
 		--config $(CONFIG) --full-stacktrace --num-cores $(NUM_CORES) \
-		$(RELEASE_ARGS) --output-file $(TOP_V)
+		$(RELEASE_ARGS) --output-file $(TOP)
 	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_bits_/m_\1_\2_/g' \
 	-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_bits_/s_\1_\2_/g' $@ > $(BUILD_DIR)/tmp.v
 	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_/m_\1_\2_/g' \
@@ -108,7 +108,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	@date -R | tee -a $(@D)/time.log
 	time -o $(@D)/time.log mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \
 		--config $(CONFIG) --full-stacktrace --num-cores $(NUM_CORES) \
-		$(SIM_ARGS) --output-file $(SIM_TOP_V)
+		$(SIM_ARGS) --output-file $(SIM_TOP)
 	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_bits_/m_\1_\2_/g' \
 	-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_bits_/s_\1_\2_/g' $@ > $(BUILD_DIR)/tmp.v
 	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_/m_\1_\2_/g' \
@@ -134,7 +134,7 @@ sim-verilog-release:
 	# split rtl modules and sim top, copy extra files
 	python3 scripts/parser.py SimTop --config $(CONFIG) \
 		--ignore XSTop --include difftest          \
-        --no-sram-conf --no-sram-xlsx --no-extra-files
+        --no-sram-conf --no-sram-xlsx
 
 clean:
 	$(MAKE) -C ./difftest clean
-- 
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