From fd13f5ed06ce907623d639176499449acffe201c Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Wed, 5 May 2021 18:48:43 +0800 Subject: [PATCH] dispatch1: allow enq.ready when !enq.valid (#799) --- src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala index b2a3aed6a..e1456333a 100644 --- a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala +++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala @@ -199,10 +199,11 @@ class Dispatch1(implicit p: Parameters) extends XSModule with HasExceptionNO { /** * Part 4: send response to rename when dispatch queue accepts the uop */ + val hasValidInstr = VecInit(io.fromRename.map(_.valid)).asUInt.orR val hasSpecialInstr = Cat((0 until RenameWidth).map(i => io.fromRename(i).valid && (isBlockBackward(i) || isNoSpecExec(i)))).orR for (i <- 0 until RenameWidth) { io.recv(i) := thisCanActualOut(i) && io.enqLsq.canAccept && io.enqRoq.canAccept && io.toIntDq.canAccept && io.toFpDq.canAccept && io.toLsDq.canAccept - io.fromRename(i).ready := !hasSpecialInstr && io.enqLsq.canAccept && io.enqRoq.canAccept && io.toIntDq.canAccept && io.toFpDq.canAccept && io.toLsDq.canAccept + io.fromRename(i).ready := !hasValidInstr || !hasSpecialInstr && io.enqLsq.canAccept && io.enqRoq.canAccept && io.toIntDq.canAccept && io.toFpDq.canAccept && io.toLsDq.canAccept XSInfo(io.recv(i) && io.fromRename(i).valid, p"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)}, type(${isInt(i)}, ${isFp(i)}, ${isLs(i)}), " + @@ -220,9 +221,9 @@ class Dispatch1(implicit p: Parameters) extends XSModule with HasExceptionNO { XSError(enqFireCnt > renameFireCnt, "enqFireCnt should not be greater than renameFireCnt\n") XSPerfAccumulate("in", Mux(RegNext(io.fromRename(0).ready), PopCount(io.fromRename.map(_.valid)), 0.U)) + XSPerfAccumulate("empty", !hasValidInstr) XSPerfAccumulate("utilization", PopCount(io.fromRename.map(_.valid))) XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.fromRename(i).valid && !io.recv(i)))) - val hasValidInstr = VecInit(io.fromRename.map(_.valid)).asUInt.orR XSPerfAccumulate("stall_cycle_lsq", hasValidInstr && !io.enqLsq.canAccept && io.enqRoq.canAccept && io.toIntDq.canAccept && io.toFpDq.canAccept && io.toLsDq.canAccept) XSPerfAccumulate("stall_cycle_roq", hasValidInstr && io.enqLsq.canAccept && !io.enqRoq.canAccept && io.toIntDq.canAccept && io.toFpDq.canAccept && io.toLsDq.canAccept) XSPerfAccumulate("stall_cycle_int_dq", hasValidInstr && io.enqLsq.canAccept && io.enqRoq.canAccept && !io.toIntDq.canAccept && io.toFpDq.canAccept && io.toLsDq.canAccept) -- GitLab