1. 27 6月, 2021 1 次提交
  2. 26 6月, 2021 5 次提交
  3. 25 6月, 2021 1 次提交
  4. 24 6月, 2021 1 次提交
  5. 22 6月, 2021 2 次提交
    • W
      Ready to run (#833) · 2f256e1d
      wakafa 提交于
      * misc: exclude ready-to-run dir in gitignore
      
      * misc: update ready-to-run flow
      
      * misc: update nemu-so
      
      * readme: use nemu-so in ready-to-run
      2f256e1d
    • W
      misc: update ready-to-run flow (#832) · b8bf926c
      wakafa 提交于
      * misc: exclude ready-to-run dir in gitignore
      
      * misc: update ready-to-run flow
      b8bf926c
  6. 17 6月, 2021 2 次提交
  7. 16 6月, 2021 2 次提交
  8. 14 6月, 2021 2 次提交
  9. 08 6月, 2021 5 次提交
  10. 04 6月, 2021 2 次提交
  11. 01 6月, 2021 1 次提交
  12. 31 5月, 2021 1 次提交
  13. 27 5月, 2021 1 次提交
  14. 25 5月, 2021 1 次提交
  15. 22 5月, 2021 1 次提交
  16. 18 5月, 2021 3 次提交
  17. 17 5月, 2021 2 次提交
  18. 15 5月, 2021 1 次提交
    • Y
      backend,RS: rewrite RS to optimize timing (#812) · 5c7674fe
      Yinan Xu 提交于
      * test,vcs: call $finish when difftest fails
      
      * backend,RS: refactor with more submodules
      
      This commit rewrites the reservation station in a more configurable style.
      
      The new RS has not finished.
      - Support only integer instructions
      - Feedback from load/store instructions is not supported
      - Fast wakeup for multi-cycle instructions is not supported
      - Submodules are refined later
      
      * RS: use wakeup signals from arbiter.out
      
      * RS: support feedback and re-schedule when needed
      
      For load and store reservation stations, the instructions that left RS before may be
      replayed later.
      
      * test,vcs: check difftest_state and return on nemu trap instructions
      
      * backend,RS: support floating-point operands and delayed regfile read for store RS
      
      This commit adds support for floating-point instructions in reservation stations.
      Beside, currently fp data for store operands come a cycle later than int data. This
      feature is also supported.
      
      Currently the RS should be ready for any circumstances.
      
      * rs,status: don't trigger assertions when !status.valid
      
      * test,vcs: add +workload option to specify the ram init file
      
      * backend,rs: don't enqueue when redirect.valid or flush.valid
      
      * backend,rs: support wait bit that instruction waits until store issues
      
      This commit adds support for wait bit, which is mainly used in load and
      store reservation stations to delay instruction issue until the corresponding
      store instruction issued.
      
      * backend,RS: optimize timing
      
      This commit optimizes BypassNetwork and PayloadArray timing.
      
      - duplicate bypass mask to avoid too many FO4
      - use one-hot vec to get read data
      5c7674fe
  19. 12 5月, 2021 3 次提交
    • L
      PTW: rewrite ptw for multiple requests support (#811) · 4d586ba1
      Lemover 提交于
      * PTW: add ptw multi-processing graph
      
      * [WIP] PTW: try to add miss queue, failed for complexity and not very useful
      
      * [WIP] PTW: rewrite ptw for multi req support
      
      * PTW: remove some assert, fix level init bug
      
      * PTW: itlb has highter priority than dtlb
      
      * PTW: fix bug that mix cache's resp logic
      
      * PTW: fix stupid bug that mix .U and .W
      
      * PTW: replay will not be blocked if fsm empty
      
      * PTW: miss queue req may return miss queue
      
      In the before design, only miss queue req can go into
      fsm, and would not be blocked.
      Now, to simplify design, miss queue req are just the
      same with new req, may blocked, going to fsm or miss queue.
      
      * PTW: fix ptw filter iss valid bug
      
      * PTW.fsm: fix bug that should not mem.req when sfenceLatch
      
      * PTW: fix ptw sfenceLatch's bug
      
      * PTW: add some perf counters
      
      * PTW: fix bug in filter enq ptr logic
      
      * PTW: fix bug of sfence in ptw
      
      * test: add current branch to ci-test, tmp
      
      * PTW: fix bug of cache's hit logic and fsm's pf
      
      * PTW: fix bug of filter's enq and block* signal
      
      * PTW: fix bug of filter's pteResp filter
      
      * PTW: add some assert of filter's counter
      
      * PTW: fix bug of filter's enq logic
      
      * PTW: set PTWMSHRSIZE 16
      
      * PTW: fix naive perf counter's bug
      
      * PTW: set PTWMSHRSIZE 8
      
      * PTW: set PTWMSHRSIZE 32
      
      * Revert "PTW: set PTWMSHRSIZE 32"
      
      This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef.
      
      * Revert "test: add current branch to ci-test, tmp"
      
      This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.
      4d586ba1
    • J
      Update mill and rocket-chip (#810) · 16cf0dd4
      Jiawei Lin 提交于
      16cf0dd4
    • W
      Configs: update MinimalConfig for FPGA (#809) · 05f23f57
      William Wang 提交于
      * Configs: add MinimalFPGAConfig
      
      * TODO: change cache parameters
      
      * Chore: add parameter print
      
      * README: add simulation usage
      
      Currently, XiangShan does not support NOOP FPGA. FPGA related
      instructions are removed
      
      * Configs: limit frontend width in MinimalConfig
      
      * MinimalConfig: limit L1/L2 cache size
      
      * MinimalConfig: limit ptw size, disable L2
      
      * MinimalConfig: limit L3 size
      
      * Sbuffer: force trigger write if sbuffer fulls
      05f23f57
  20. 11 5月, 2021 2 次提交
    • Y
      test,vcs: call $finish when difftest fails (#808) · 632fc81b
      Yinan Xu 提交于
      632fc81b
    • W
      backend,mem: add Store Sets memory dependence predictor (#796) · de169c67
      William Wang 提交于
      * LoadQueue: send stFtqIdx via rollback request
      
      * It will make it possible for setore set to update its SSIT
      
      * StoreSet: setup store set update req
      
      * StoreSet: add store set identifier table (SSIT)
      
      * StoreSet: add last fetched store table (LFST)
      
      * StoreSet: put SSIT into decode stage
      
      * StoreSet: put LFST into dispatch1
      
      * Future work: optimize timing
      
      * RS: store rs now supports delayed issue
      
      * StoreSet: add perf counter
      
      * StoreSet: fix SSIT update logic
      
      * StoreSet: delay LFST update input for 1 cycle
      
      * StoreSet: fix LFST update logic
      
      * StoreSet: fix LFST raddr width
      
      * StoreSet: do not force store in ss issue in order
      
      Classic store set requires store in the same store set issue in seq.
      However, in current micro-architecture, such restrict will lead to
      severe perf lost. We choose to disable it until we find another way
      to fix it.
      
      * StoreSet: support ooo store in the same store set
      
      * StoreSet: fix store set merge logic
      
      * StoreSet: check earlier store when read LFST
      
      * If store-load pair is in the same dispatch bundle, loadWaitBit should
      also be set for load
      
      * StoreSet: increase default SSIT flush period
      
      * StoreSet: fix LFST read logic
      
      * Fix commit c0e541d1
      
      * StoreSet: add StoreSetEnable parameter
      
      * RSFeedback: add source type
      
      * StoreQueue: split store addr and store data
      
      * StoreQueue: update ls forward logic
      
      * Now it supports splited addr and data
      
      * Chore: force assign name for load/store unit
      
      * RS: add rs'support for store a-d split
      
      * StoreQueue: fix stlf logic
      
      * StoreQueue: fix addr wb sq update logic
      
      * AtomicsUnit: support splited a/d
      
      * Parameters: disable store set by default
      
      * WaitTable: wait table will not cause store delay
      
      * WaitTable: recover default reset period to 2^17
      
      * Fix dev-stad merge conflict
      
      * StoreSet: enable storeset
      
      * RS: disable store rs delay logic
      
      CI perf shows that current delay logic will cause perf loss. Disable
      unnecessary delay logic will help.
      
      To be more specific, `io.readyVec` caused the problem. It will be
      updated in future commits.
      
      * RS: opt select logic with load delay (ldWait)
      
      * StoreSet: disable 2-bit lwt
      Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
      de169c67
  21. 09 5月, 2021 1 次提交