From ca39c0e3f10cdd570cf01f4e57f21a88c63e5890 Mon Sep 17 00:00:00 2001
From: Guokai Chen <chenguokai17@mails.ucas.ac.cn>
Date: Mon, 7 Nov 2022 17:09:51 +0800
Subject: [PATCH] arch,riscv: fix supervisor timer interrupt

---
 am/src/nemu/isa/riscv/mtime.S | 5 +++--
 am/src/xs/isa/riscv/clint.c   | 6 +++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/am/src/nemu/isa/riscv/mtime.S b/am/src/nemu/isa/riscv/mtime.S
index aa6e0d08..d2a9264a 100644
--- a/am/src/nemu/isa/riscv/mtime.S
+++ b/am/src/nemu/isa/riscv/mtime.S
@@ -28,8 +28,9 @@ is_timer:
         add a3, a3, a2
         sd a3, 0(a1)
 
-        # raise a supervisor software interrupt.
-        csrwi sip, 2
+        # raise a supervisor timer interrupt.
+	li a3, 32
+        csrw mip, a3
         j end_of_intr
 
 is_ext:
diff --git a/am/src/xs/isa/riscv/clint.c b/am/src/xs/isa/riscv/clint.c
index 9e22a778..bf7e62b6 100644
--- a/am/src/xs/isa/riscv/clint.c
+++ b/am/src/xs/isa/riscv/clint.c
@@ -48,7 +48,7 @@ void init_timer() {
  */
 void enable_timer() {
   // set machine timer interrupt
-  asm volatile("csrs mie, %0" : : "r"((1 << 7) | (1 << 1)));
+  asm volatile("csrs mie, %0" : : "r"((1 << 7) | (1 << 5) | (1 << 1)));
 }
 
 /*
@@ -56,5 +56,5 @@ void enable_timer() {
  */
 void disable_timer() {
   // unset machine timer interrupt
-  asm volatile("csrc mie, %0" : : "r"((1 << 7) | (1 << 1)));
-}
\ No newline at end of file
+  asm volatile("csrc mie, %0" : : "r"((1 << 7) | (1 << 5) | (1 << 1)));
+}
-- 
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