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提交 187d2bd8 编写于 作者: 饶先宏's avatar 饶先宏
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202109031637

上级 1958f7e5
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Showing with 9101 addition and 4386 deletion
examples/hdl4se_riscv/de1/de1_riscv_v4.v
浏览文件 @ 187d2bd8
......@@ -2,7 +2,9 @@
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define USECLOCK50_1
`define USECLOCK50
module de1_riscv_v4(
//////////// ADC //////////
......@@ -90,8 +92,6 @@ module de1_riscv_v4(
inout [35:0] GPIO
);
wire uart_tx;
wire uart_rx;
assign GPIO[5] = uart_tx;
......@@ -144,6 +144,17 @@ module de1_riscv_v4(
wire [29:0] ramaddr;
assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];
wire [4:0] regno;
wire [3:0] regena;
wire [31:0] regwrdata;
wire regwren;
wire [31:0] regrddata;
wire [4:0] regno2;
wire [3:0] regena2;
wire [31:0] regwrdata2;
wire regwren2;
wire [31:0] regrddata2;
uart_ctrl uart_ctrl(
.wClk(wClk),
.nwReset(nwReset),
......@@ -161,10 +172,21 @@ module de1_riscv_v4(
.recvempty(LEDR[5])
);
reg [4:0] lastregno;
reg [4:0] lastregno2;
always @(posedge wClk) begin
lastregno <= regno;
lastregno2 <= regno2;
end
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
ram16kB ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
regno, regena, regwrdata, regwren, (lastregno == 0) ? 0 : regrddata,
regno2, regena2, regwrdata2, regwren2, (lastregno2 == 0) ? 0 : regrddata2
);
reg [6:0] led0;
reg [6:0] led1;
......@@ -219,5 +241,6 @@ module de1_riscv_v4(
end
end
end
endmodule
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v4.c
浏览文件 @ 187d2bd8
......@@ -53,40 +53,51 @@
#define M_ID(id) riscv_core##id
IDLIST
VID(wClk),
VID(nwReset),
VID(wWrite),
VID(bWriteAddr),
VID(bWriteData),
VID(bWriteMask),
VID(wRead),
VID(bReadAddr),
VID(bReadData),
VID(regno),
VID(regena),
VID(regwrdata),
VID(regwren),
VID(regrddata),
VID(regno2),
VID(regena2),
VID(regwrdata2),
VID(regwren2),
VID(regrddata2),
VID(pc),
VID(instr),
VID(write),
VID(writeaddr),
VID(writedata),
VID(writemask),
VID(readreg),
VID(state),
VID(imm),
VID(dstreg),
VID(dstvalue),
VID(lastv),
VID(lastaddr),
VID(ldaddr),
VID(divclk),
VID(wClk),
VID(nwReset),
VID(wWrite),
VID(bWriteAddr),
VID(bWriteData),
VID(bWriteMask),
VID(wRead),
VID(bReadAddr),
VID(bReadData),
VID(regno),
VID(regena),
VID(regwrdata),
VID(regwren),
VID(regrddata),
VID(regno2),
VID(regena2),
VID(regwrdata2),
VID(regwren2),
VID(regrddata2),
VID(pc),
VID(instr),
VID(write),
VID(writeaddr),
VID(writedata),
VID(writemask),
VID(readreg),
VID(state),
VID(imm),
VID(dstreg),
VID(dstvalue),
VID(lastv),
VID(lastaddr),
VID(ldaddr),
VID(divclk),
VID(misa), /*0301*/
VID(ucycle), /*0c00*/
VID(utime), /*0c01*/
VID(uinstret), /*0c02*/
VID(ucycleh), /*0c80*/
VID(utimeh), /*0c81*/
VID(uinstreth), /*0c82*/
VID(mcycle), /*0b00*/
VID(minstret), /*0b02*/
VID(mcycleh), /*0b80*/
VID(minstreth) /*0b82*/
END_IDLIST
enum riscv_core_state {
......@@ -535,7 +546,7 @@ DEFINE_FUNC(riscv_core_exec_inst, "") {
case 0x04: break;// riscv_core_exec_alui_inst(pobj, pc, instr, rs1, rs2); break;
case 0x0c: break;// riscv_core_exec_alu_inst(pobj, pc, instr, rs1, rs2); break;
case 0x03: riscv_core_exec_fence_inst(pobj, pc, instr, rs1, rs2); break;
case 0x1c: riscv_core_exec_sys_inst(pobj, pc, instr, rs1, rs2); break;
case 0x1c: break;// riscv_core_exec_sys_inst(pobj, pc, instr, rs1, rs2); break;
default: {
INSTR_FORMAT_ERROR;
exit(-2);
......@@ -655,6 +666,34 @@ DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc
case 0x19: RISCV_SETDSTREG(rd, pc + 4); break;
case 0x04: riscv_core_exec_alui_inst(pobj, pc, instr, rs1, rs2); break;
case 0x0c: riscv_core_exec_alu_inst(pobj, pc, instr, rs1, rs2); break;
case 0x1c: {
unsigned int csr_r;
unsigned int func3 = (instr >> 12) & 0x7;
switch (instr >> 20) {
case 0x301: csr_r = vget(misa); break;
case 0xc00: csr_r = vget(ucycle); break;
case 0xc01: csr_r = vget(utime); break;
case 0xc02: csr_r = vget(uinstret); break;
case 0xc80: csr_r = vget(ucycleh); break;
case 0xc81: csr_r = vget(utimeh); break;
case 0xc82: csr_r = vget(uinstreth); break;
case 0xb00: csr_r = vget(mcycle); break;
case 0xb02: csr_r = vget(minstret); break;
case 0xb80: csr_r = vget(mcycleh); break;
case 0xb82: csr_r = vget(minstreth); break;
default: csr_r = 0;
}
switch (func3) {
case 0: /* ECALL/EBREAK */ RISCV_SETDSTREG(0, 0); break;
case 1: /* CSRRW */ RISCV_SETDSTREG(rd, csr_r); break;
case 2: /* CSRRS */ RISCV_SETDSTREG(rd, csr_r); break;
case 3: /* CSRRC */ RISCV_SETDSTREG(rd, csr_r); break;
case 5: /* CSRRWI */ RISCV_SETDSTREG(rd, csr_r); break;
case 6: /* CSRRSI */ RISCV_SETDSTREG(rd, csr_r); break;
case 7: /* CSRRCI */ RISCV_SETDSTREG(rd, csr_r); break;
default: RISCV_SETDSTREG(0, 0); break;
}
} break;
default: {
RISCV_SETDSTREG(0, 0);
}
......@@ -731,6 +770,11 @@ DEFINE_FUNC(riscv_core_gen_imm, "instr, state") {
imm = sign_expand(imm, 11);
vput(imm, imm);
}break;
case 0x1c: { /*csr*/
unsigned int imm;
imm = (instr >> 15) & 0x1f;
vput(imm, imm);
}break;
}
}
} END_DEFINE_FUNC
......@@ -1056,41 +1100,158 @@ DEFINE_FUNC(riscv_core_clktick, "") {
}
} END_DEFINE_FUNC
MODULE_INIT(riscv_core)
PORT_IN(wClk, 1);
PORT_IN(nwReset, 1);
GPORT_OUT(wWrite, 1, riscv_core_wr_sig);
GPORT_OUT(bWriteAddr, 32, riscv_core_wr_sig);
GPORT_OUT(bWriteData, 32, riscv_core_wr_sig);
GPORT_OUT(bWriteMask, 4, riscv_core_wr_sig);
GPORT_OUT(wRead, 1, riscv_core_read_sig);
GPORT_OUT(bReadAddr, 32, riscv_core_read_sig);
PORT_IN(bReadData, 32);
GPORT_OUT(regno, 5, riscv_core_reg_wr_sig);
GPORT_OUT(regena, 4, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata, 32, riscv_core_reg_wr_sig);
GPORT_OUT(regwren, 1, riscv_core_reg_wr_sig);
PORT_IN(regrddata, 32);
GPORT_OUT(regno2, 5, riscv_core_reg_wr_sig);
GPORT_OUT(regena2, 4, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata2, 32, riscv_core_reg_wr_sig);
GPORT_OUT(regwren2, 1, riscv_core_reg_wr_sig);
PORT_IN(regrddata2, 32);
GREG(pc, 32, riscv_core_reg_gen_pc);
GREG(instr, 32, riscv_core_reg_gen_instr);
GREG(write, 1, riscv_core_gen_write);
GREG(writeaddr, 32, riscv_core_gen_write);
GREG(writedata, 32, riscv_core_gen_write);
GREG(writemask, 4, riscv_core_gen_write);
GREG(readreg, 5, riscv_core_reg_gen_readreg);
GREG(state, 4, riscv_core_gen_state);
GREG(imm, 32, riscv_core_gen_imm);
GWIRE(dstreg, 5, riscv_core_gen_dstreg);
GWIRE(dstvalue, 32, riscv_core_gen_dstreg);
GREG(ldaddr, 32, riscv_core_gen_ldaddr);
GREG(divclk, 6, riscv_core_reg_gen_divclk);
GREG(lastv, 32, riscv_core_reg_gen_lastv);
GREG(lastaddr, 32, riscv_core_reg_gen_lastv);
DEFINE_FUNC(riscv_core_gen_csr, "nwReset, ucycle, ucycleh, misa, mcycle, mcycleh, utime,utimeh, uinstret, uinstreth, minstret, minstreth, instr, imm, regrddata") {
if (vget(nwReset) == 0) {
vput(misa, 0x40101100); //32'b0100_0000_0001_0000_0001_0001_0000_0000 RV32IM
vput(ucycle, 0);
vput(ucycleh, 0);
vput(mcycle, 0);
vput(mcycleh, 0);
vput(utime, 0);
vput(utimeh, 0);
vput(uinstret, 0);
vput(uinstreth, 0);
vput(minstret, 0);
vput(minstreth, 0);
}
else {
if (vget(ucycle) == 0xffffffff) {
vput(ucycleh, vget(ucycleh) + 1);
vput(ucycle, 0);
}
else {
vput(ucycle, vget(ucycle) + 1);
}
if (vget(utime) == 0xffffffff) {
vput(utimeh, vget(utimeh) + 1);
vput(utime, 0);
}
else {
vput(utime, vget(utime) + 1);
}
if (vget(mcycle) == 0xffffffff) {
vput(mcycleh, vget(mcycleh) + 1);
vput(mcycle, 0);
}
else {
vput(mcycle, vget(mcycle) + 1);
}
if (vget(state) == RISCVSTATE_EXEC_INST) {
unsigned int instr = vget(instr);
unsigned int rs1 = vget(regrddata);
unsigned int imm = vget(imm);
unsigned int opcode = instr & 0x7f;
opcode >>= 2;
if (opcode == 0x1c) { /* CSR */
unsigned int csr_v;
unsigned int csr_op;
unsigned int csr_r;
unsigned int func3 = (instr >> 12) & 0x7;
switch (instr >> 20) {
case 0x301: csr_r = vget(misa); break;
case 0xc00: csr_r = vget(ucycle); break;
case 0xc01: csr_r = vget(utime); break;
case 0xc02: csr_r = vget(uinstret); break;
case 0xc80: csr_r = vget(ucycleh); break;
case 0xc81: csr_r = vget(utimeh); break;
case 0xc82: csr_r = vget(uinstreth); break;
case 0xb00: csr_r = vget(mcycle); break;
case 0xb02: csr_r = vget(minstret); break;
case 0xb80: csr_r = vget(mcycleh); break;
case 0xb82: csr_r = vget(minstreth); break;
default: csr_r = 0;
}
switch (func3) {
case 1: /* CSRRW */ csr_v = rs1; csr_op = 1; break;
case 2: /* CSRRS */ csr_v = csr_r | rs1; csr_op = 1; break;
case 3: /* CSRRC */ csr_v = csr_r & (~rs1); csr_op = 1; break;
case 5: /* CSRRWI */ csr_v = imm; csr_op = 1; break;
case 6: /* CSRRSI */ csr_v = csr_r | imm; csr_op = 1; break;
case 7: /* CSRRCI */ csr_v = csr_r & (~imm); csr_op = 1; break;
default: csr_op = 0;;
}
if (csr_op) {
switch (instr >> 20) {
case 0x301: vput(misa, csr_v); break;
case 0xc00: vput(ucycle, csr_v); break;
case 0xc01: vput(utime, csr_v); break;
case 0xc02: vput(uinstret, csr_v); break;
case 0xc80: vput(ucycleh, csr_v); break;
case 0xc81: vput(utimeh, csr_v); break;
case 0xc82: vput(uinstreth, csr_v); break;
case 0xb00: vput(mcycle, csr_v); break;
case 0xb02: vput(minstret, csr_v); break;
case 0xb80: vput(mcycleh, csr_v); break;
case 0xb82: vput(minstreth, csr_v); break;
}
}
}
else {
if (vget(uinstret) == 0xffffffff) {
vput(uinstreth, vget(uinstreth) + 1);
vput(uinstret, 0);
}
else {
vput(uinstret, vget(uinstret) + 1);
}
if (vget(minstret) == 0xffffffff) {
vput(minstreth, vget(minstreth) + 1);
vput(minstret, 0);
}
else {
vput(minstret, vget(minstret) + 1);
}
}
}
}
} END_DEFINE_FUNC
CLKTICK_FUNC(riscv_core_clktick);
MODULE_INIT(riscv_core)
PORT_IN(wClk, 1);
PORT_IN(nwReset, 1);
GPORT_OUT(wWrite, 1, riscv_core_wr_sig);
GPORT_OUT(bWriteAddr, 32, riscv_core_wr_sig);
GPORT_OUT(bWriteData, 32, riscv_core_wr_sig);
GPORT_OUT(bWriteMask, 4, riscv_core_wr_sig);
GPORT_OUT(wRead, 1, riscv_core_read_sig);
GPORT_OUT(bReadAddr, 32, riscv_core_read_sig);
PORT_IN(bReadData, 32);
GPORT_OUT(regno, 5, riscv_core_reg_wr_sig);
GPORT_OUT(regena, 4, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata, 32, riscv_core_reg_wr_sig);
GPORT_OUT(regwren, 1, riscv_core_reg_wr_sig);
PORT_IN(regrddata, 32);
GPORT_OUT(regno2, 5, riscv_core_reg_wr_sig);
GPORT_OUT(regena2, 4, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata2, 32, riscv_core_reg_wr_sig);
GPORT_OUT(regwren2, 1, riscv_core_reg_wr_sig);
PORT_IN(regrddata2, 32);
GREG(pc, 32, riscv_core_reg_gen_pc);
GREG(instr, 32, riscv_core_reg_gen_instr);
GREG(write, 1, riscv_core_gen_write);
GREG(writeaddr, 32, riscv_core_gen_write);
GREG(writedata, 32, riscv_core_gen_write);
GREG(writemask, 4, riscv_core_gen_write);
GREG(readreg, 5, riscv_core_reg_gen_readreg);
GREG(state, 4, riscv_core_gen_state);
GREG(imm, 32, riscv_core_gen_imm);
GWIRE(dstreg, 5, riscv_core_gen_dstreg);
GWIRE(dstvalue, 32, riscv_core_gen_dstreg);
GREG(ldaddr, 32, riscv_core_gen_ldaddr);
GREG(divclk, 6, riscv_core_reg_gen_divclk);
GREG(lastv, 32, riscv_core_reg_gen_lastv);
GREG(lastaddr, 32, riscv_core_reg_gen_lastv);
GREG(misa, 32, riscv_core_gen_csr);
GREG(ucycle, 32, riscv_core_gen_csr);
GREG(utime, 32, riscv_core_gen_csr);
GREG(uinstret, 32, riscv_core_gen_csr);
GREG(ucycleh, 32, riscv_core_gen_csr);
GREG(utimeh, 32, riscv_core_gen_csr);
GREG(uinstreth, 32, riscv_core_gen_csr);
GREG(mcycle, 32, riscv_core_gen_csr);
GREG(minstret, 32, riscv_core_gen_csr);
GREG(mcycleh, 32, riscv_core_gen_csr);
GREG(minstreth, 32, riscv_core_gen_csr);
CLKTICK_FUNC(riscv_core_clktick);
END_MODULE_INIT(riscv_core)
examples/hdl4se_riscv/test_code/console.c
浏览文件 @ 187d2bd8
......@@ -106,7 +106,7 @@ int _d2s(char* buf, int num)
return len;
}
int _h2s(char* buf, unsigned int num, int fixlen, char lead)
int _h2s(char* buf, unsigned long long num, int fixlen, char lead)
{
int i;
int len;
......@@ -326,6 +326,37 @@ unsigned int num2seg(unsigned int num)
return segcode[num % 10];
}
unsigned long long cycle() {
unsigned long long ret;
unsigned int retl, reth;
asm volatile (
"csrrsi %0, %1, %2 " : "=r"(retl) : "i"(0xc00),"i"(0):"a0"
);
asm volatile (
"csrrsi %0, %1, %2 " : "=r"(reth) : "i"(0xc80), "i"(0) : "a0"
);
ret = reth;
ret <<= 32;
ret |= retl;
return ret;
}
unsigned long long instrcount() {
unsigned long long ret;
unsigned int retl, reth;
asm volatile (
"csrrsi %0, %1, %2 " : "=r"(retl) : "i"(0xc02), "i"(0) : "a0"
);
asm volatile (
"csrrsi %0, %1, %2 " : "=r"(reth) : "i"(0xc82), "i"(0) : "a0"
);
ret = reth;
ret <<= 32;
ret |= retl;
return ret;
}
int main(int argc, char* argv[])
{
volatile unsigned int* ledkey = (unsigned int*)0xF0000000;
......@@ -346,8 +377,16 @@ int main(int argc, char* argv[])
count1 = 0;
do {
char buf[256];
_h2s(buf, test, 8, '0');
int rate;
rate = cycle() / (instrcount() / 100);
if (_canputchar()) {
_h2s(buf, cycle(), 8, '0');
_puts(buf);
_puts(":");
_h2s(buf, instrcount(), 8, '0');
_puts(buf);
_puts(":");
_d2s(buf, rate);
_puts(buf);
_puts(">>");
}
......@@ -381,7 +420,9 @@ int main(int argc, char* argv[])
leddata[2] = *(unsigned int*)&ledd[8];
}
else {
ledd[0] = num2seg(count0);
unsigned int count = cycle()/1000;
ledd[0] = num2seg(count);
ledd[1] = num2seg(count1 / 10);
ledd[2] = num2seg(count1 / 100);
ledd[3] = num2seg(count1 / 1000);
......
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ 187d2bd8
......@@ -10,32 +10,40 @@ ELF Header:
Version: 0x1
Entry point address: 0x8c
Start of program headers: 52 (bytes into file)
Start of section headers: 9300 (bytes into file)
Start of section headers: 20444 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 2
Size of section headers: 40 (bytes)
Number of section headers: 15
Section header string table index: 14
Number of section headers: 23
Section header string table index: 22
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000074 000074 0015e4 00 AX 0 0 4
[ 2] .rodata PROGBITS 00001658 001658 0000bb 00 A 0 0 4
[ 3] .eh_frame PROGBITS 00002714 001714 000004 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 00002718 001718 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 00002720 001720 000004 04 WA 0 0 4
[ 6] .data PROGBITS 00002728 001728 000428 00 WA 0 0 8
[ 7] .sdata PROGBITS 00002b50 001b50 000010 00 WA 0 0 4
[ 8] .sbss NOBITS 00002b60 001b60 000008 00 WA 0 0 4
[ 9] .bss NOBITS 00002b68 001b60 00001c 00 WA 0 0 4
[10] .comment PROGBITS 00000000 001b60 000012 01 MS 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 001b72 000021 00 0 0 1
[12] .symtab SYMTAB 00000000 001b94 000540 10 13 41 4
[13] .strtab STRTAB 00000000 0020d4 000302 00 0 0 1
[14] .shstrtab STRTAB 00000000 0023d6 00007e 00 0 0 1
[ 1] .text PROGBITS 00000074 000074 001c58 00 AX 0 0 4
[ 2] .rodata PROGBITS 00001ccc 001ccc 0001bc 00 A 0 0 4
[ 3] .eh_frame PROGBITS 00002000 002000 00002c 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 0000202c 00202c 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 00002034 002034 000004 04 WA 0 0 4
[ 6] .data PROGBITS 00002038 002038 000428 00 WA 0 0 8
[ 7] .sdata PROGBITS 00002460 002460 000010 00 WA 0 0 4
[ 8] .sbss NOBITS 00002470 002470 000008 00 WA 0 0 4
[ 9] .bss NOBITS 00002478 002470 00001c 00 WA 0 0 4
[10] .comment PROGBITS 00000000 002470 000012 01 MS 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 002482 00002a 00 0 0 1
[12] .debug_aranges PROGBITS 00000000 0024ac 000038 00 0 0 1
[13] .debug_info PROGBITS 00000000 0024e4 000839 00 0 0 1
[14] .debug_abbrev PROGBITS 00000000 002d1d 000216 00 0 0 1
[15] .debug_line PROGBITS 00000000 002f33 000766 00 0 0 1
[16] .debug_str PROGBITS 00000000 003699 00029a 01 MS 0 0 1
[17] .debug_line_str PROGBITS 00000000 003933 0000aa 01 MS 0 0 1
[18] .debug_loclists PROGBITS 00000000 0039dd 000a99 00 0 0 1
[19] .debug_rnglists PROGBITS 00000000 004476 000111 00 0 0 1
[20] .symtab SYMTAB 00000000 004588 000620 10 21 51 4
[21] .strtab STRTAB 00000000 004ba8 000344 00 0 0 1
[22] .shstrtab STRTAB 00000000 004eec 0000ee 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -46,8 +54,8 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000000 0x00000000 0x00000000 0x01713 0x01713 R E 0x1000
LOAD 0x001714 0x00002714 0x00002714 0x0044c 0x00470 RW 0x1000
LOAD 0x000000 0x00000000 0x00000000 0x01e88 0x01e88 R E 0x1000
LOAD 0x002000 0x00002000 0x00002000 0x00470 0x00494 RW 0x1000
Section to Segment mapping:
Segment Sections...
......@@ -60,95 +68,111 @@ There are no relocations in this file.
The decoding of unwind sections for machine type RISC-V is not currently supported.
Symbol table '.symtab' contains 84 entries:
Symbol table '.symtab' contains 98 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000074 0 SECTION LOCAL DEFAULT 1 .text
2: 00001658 0 SECTION LOCAL DEFAULT 2 .rodata
3: 00002714 0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 00002718 0 SECTION LOCAL DEFAULT 4 .init_array
5: 00002720 0 SECTION LOCAL DEFAULT 5 .fini_array
6: 00002728 0 SECTION LOCAL DEFAULT 6 .data
7: 00002b50 0 SECTION LOCAL DEFAULT 7 .sdata
8: 00002b60 0 SECTION LOCAL DEFAULT 8 .sbss
9: 00002b68 0 SECTION LOCAL DEFAULT 9 .bss
2: 00001ccc 0 SECTION LOCAL DEFAULT 2 .rodata
3: 00002000 0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 0000202c 0 SECTION LOCAL DEFAULT 4 .init_array
5: 00002034 0 SECTION LOCAL DEFAULT 5 .fini_array
6: 00002038 0 SECTION LOCAL DEFAULT 6 .data
7: 00002460 0 SECTION LOCAL DEFAULT 7 .sdata
8: 00002470 0 SECTION LOCAL DEFAULT 8 .sbss
9: 00002478 0 SECTION LOCAL DEFAULT 9 .bss
10: 00000000 0 SECTION LOCAL DEFAULT 10 .comment
11: 00000000 0 SECTION LOCAL DEFAULT 11 .riscv.attributes
12: 00000000 0 FILE LOCAL DEFAULT ABS __call_atexit.c
13: 00000074 24 FUNC LOCAL DEFAULT 1 register_fini
14: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
15: 00002714 0 OBJECT LOCAL DEFAULT 3
16: 000000d8 0 FUNC LOCAL DEFAULT 1 __do_global_dtors_aux
17: 00002b68 1 OBJECT LOCAL DEFAULT 9 completed.1
18: 00002720 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...]
19: 0000011c 0 FUNC LOCAL DEFAULT 1 frame_dummy
20: 00002b6c 24 OBJECT LOCAL DEFAULT 9 object.0
21: 0000271c 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...]
22: 00000000 0 FILE LOCAL DEFAULT ABS console.c
23: 00000000 0 FILE LOCAL DEFAULT ABS exit.c
24: 00000000 0 FILE LOCAL DEFAULT ABS impure.c
25: 00002728 1064 OBJECT LOCAL DEFAULT 6 impure_data
26: 00000000 0 FILE LOCAL DEFAULT ABS init.c
27: 00000000 0 FILE LOCAL DEFAULT ABS fini.c
28: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c
29: 00000000 0 FILE LOCAL DEFAULT ABS __atexit.c
30: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c
31: 00000000 0 FILE LOCAL DEFAULT ABS errno.c
32: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
33: 00002714 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__
34: 00000000 0 FILE LOCAL DEFAULT ABS
35: 00002724 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end
36: 00002720 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start
37: 00002720 0 NOTYPE LOCAL DEFAULT 4 __init_array_end
38: 00002718 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end
39: 00002718 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
40: 00002718 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
41: 000001b8 88 FUNC GLOBAL DEFAULT 1 _putchar
42: 00000970 140 FUNC GLOBAL DEFAULT 1 _strcat
43: 00002f28 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
44: 000009fc 112 FUNC GLOBAL DEFAULT 1 _strcmp
45: 00001674 40 OBJECT GLOBAL DEFAULT 2 segcode
46: 00001650 8 FUNC GLOBAL DEFAULT 1 __errno
47: 00002b50 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__
48: 0000013c 60 FUNC GLOBAL DEFAULT 1 _canputchar
49: 00000778 312 FUNC GLOBAL DEFAULT 1 _s2h
50: 0000025c 104 FUNC GLOBAL DEFAULT 1 _puts
51: 00000b04 64 FUNC GLOBAL DEFAULT 1 _buadrateset
52: 000004f8 388 FUNC GLOBAL DEFAULT 1 _h2s
53: 00002b54 0 OBJECT GLOBAL HIDDEN 7 __dso_handle
54: 00000b44 584 FUNC GLOBAL DEFAULT 1 dispmem
55: 00000178 64 FUNC GLOBAL DEFAULT 1 _haschar
56: 00002b50 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr
57: 00001280 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
58: 000002c4 216 FUNC GLOBAL DEFAULT 1 _gets
59: 00001518 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
60: 0000067c 252 FUNC GLOBAL DEFAULT 1 _s2d
61: 000013f8 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
62: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
63: 00001588 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
64: 00000210 76 FUNC GLOBAL DEFAULT 1 _getchar
65: 00002b84 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__
66: 00002b58 4 OBJECT GLOBAL DEFAULT 7 _uartaddr
67: 0000039c 348 FUNC GLOBAL DEFAULT 1 _d2s
68: 00002b60 0 NOTYPE GLOBAL DEFAULT 8 __bss_start
69: 0000131c 220 FUNC GLOBAL DEFAULT 1 memset
70: 00000dcc 1156 FUNC GLOBAL DEFAULT 1 main
71: 00002b64 4 OBJECT GLOBAL DEFAULT 8 displayaddr
72: 00000900 112 FUNC GLOBAL DEFAULT 1 _strcpy
73: 00001574 20 FUNC GLOBAL DEFAULT 1 atexit
74: 00002b5c 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr
75: 00002728 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
76: 00000a6c 152 FUNC GLOBAL DEFAULT 1 _strncmp
77: 00000d8c 64 FUNC GLOBAL DEFAULT 1 num2seg
78: 00002b60 4 OBJECT GLOBAL DEFAULT 8 _uartstate
79: 00002b60 0 NOTYPE GLOBAL DEFAULT 7 _edata
80: 00002b84 0 NOTYPE GLOBAL DEFAULT 9 _end
81: 00001250 48 FUNC GLOBAL DEFAULT 1 exit
82: 000008b0 80 FUNC GLOBAL DEFAULT 1 _strlen
83: 00001620 48 FUNC GLOBAL DEFAULT 1 _exit
12: 00000000 0 SECTION LOCAL DEFAULT 12 .debug_aranges
13: 00000000 0 SECTION LOCAL DEFAULT 13 .debug_info
14: 00000000 0 SECTION LOCAL DEFAULT 14 .debug_abbrev
15: 00000000 0 SECTION LOCAL DEFAULT 15 .debug_line
16: 00000000 0 SECTION LOCAL DEFAULT 16 .debug_str
17: 00000000 0 SECTION LOCAL DEFAULT 17 .debug_line_str
18: 00000000 0 SECTION LOCAL DEFAULT 18 .debug_loclists
19: 00000000 0 SECTION LOCAL DEFAULT 19 .debug_rnglists
20: 00000000 0 FILE LOCAL DEFAULT ABS __call_atexit.c
21: 00000074 24 FUNC LOCAL DEFAULT 1 register_fini
22: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
23: 00002000 0 OBJECT LOCAL DEFAULT 3 __EH_FRAME_BEGIN__
24: 000000d8 0 FUNC LOCAL DEFAULT 1 __do_global_dtors_aux
25: 00002478 1 OBJECT LOCAL DEFAULT 9 completed.1
26: 00002034 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...]
27: 0000011c 0 FUNC LOCAL DEFAULT 1 frame_dummy
28: 0000247c 24 OBJECT LOCAL DEFAULT 9 object.0
29: 00002030 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...]
30: 00000000 0 FILE LOCAL DEFAULT ABS console.c
31: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
32: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
33: 00000000 0 FILE LOCAL DEFAULT ABS exit.c
34: 00000000 0 FILE LOCAL DEFAULT ABS impure.c
35: 00002038 1064 OBJECT LOCAL DEFAULT 6 impure_data
36: 00000000 0 FILE LOCAL DEFAULT ABS init.c
37: 00000000 0 FILE LOCAL DEFAULT ABS fini.c
38: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c
39: 00000000 0 FILE LOCAL DEFAULT ABS __atexit.c
40: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c
41: 00000000 0 FILE LOCAL DEFAULT ABS errno.c
42: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
43: 00002028 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__
44: 00000000 0 FILE LOCAL DEFAULT ABS
45: 00002038 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end
46: 00002034 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start
47: 00002034 0 NOTYPE LOCAL DEFAULT 4 __init_array_end
48: 0000202c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end
49: 0000202c 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
50: 0000202c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
51: 000001b8 88 FUNC GLOBAL DEFAULT 1 _putchar
52: 00000e28 124 FUNC GLOBAL DEFAULT 1 cycle
53: 00000994 140 FUNC GLOBAL DEFAULT 1 _strcat
54: 00002838 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
55: 00000a20 112 FUNC GLOBAL DEFAULT 1 _strcmp
56: 00001ce8 40 OBJECT GLOBAL DEFAULT 2 segcode
57: 00001cc4 8 FUNC GLOBAL DEFAULT 1 __errno
58: 00002460 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__
59: 0000013c 60 FUNC GLOBAL DEFAULT 1 _canputchar
60: 0000079c 312 FUNC GLOBAL DEFAULT 1 _s2h
61: 0000025c 104 FUNC GLOBAL DEFAULT 1 _puts
62: 00000b28 64 FUNC GLOBAL DEFAULT 1 _buadrateset
63: 000004f8 424 FUNC GLOBAL DEFAULT 1 _h2s
64: 00002464 0 OBJECT GLOBAL HIDDEN 7 __dso_handle
65: 00000b68 640 FUNC GLOBAL DEFAULT 1 dispmem
66: 00000178 64 FUNC GLOBAL DEFAULT 1 _haschar
67: 00002460 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr
68: 000018f4 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
69: 00001494 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
70: 000002c4 216 FUNC GLOBAL DEFAULT 1 _gets
71: 00001b8c 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
72: 000006a0 252 FUNC GLOBAL DEFAULT 1 _s2d
73: 00001a6c 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
74: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
75: 00001bfc 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
76: 00000210 76 FUNC GLOBAL DEFAULT 1 _getchar
77: 00002494 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__
78: 00002468 4 OBJECT GLOBAL DEFAULT 7 _uartaddr
79: 0000039c 348 FUNC GLOBAL DEFAULT 1 _d2s
80: 00002470 0 NOTYPE GLOBAL DEFAULT 8 __bss_start
81: 00001990 220 FUNC GLOBAL DEFAULT 1 memset
82: 00000f20 1396 FUNC GLOBAL DEFAULT 1 main
83: 00002474 4 OBJECT GLOBAL DEFAULT 8 displayaddr
84: 00000924 112 FUNC GLOBAL DEFAULT 1 _strcpy
85: 00001d88 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
86: 00001be8 20 FUNC GLOBAL DEFAULT 1 atexit
87: 0000246c 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr
88: 00002038 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
89: 00000a90 152 FUNC GLOBAL DEFAULT 1 _strncmp
90: 00000de8 64 FUNC GLOBAL DEFAULT 1 num2seg
91: 00002470 4 OBJECT GLOBAL DEFAULT 8 _uartstate
92: 00002470 0 NOTYPE GLOBAL DEFAULT 7 _edata
93: 00002494 0 NOTYPE GLOBAL DEFAULT 9 _end
94: 000018c4 48 FUNC GLOBAL DEFAULT 1 exit
95: 000008d4 80 FUNC GLOBAL DEFAULT 1 _strlen
96: 00001c94 48 FUNC GLOBAL DEFAULT 1 _exit
97: 00000ea4 124 FUNC GLOBAL DEFAULT 1 instrcount
No version information found in this file.
Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0"
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 11
examples/hdl4se_riscv/verilog/riscv_core_v4.v
浏览文件 @ 187d2bd8
......@@ -70,22 +70,53 @@ module riscv_core(
input [31:0] regrddata2
);
reg [31:0] pc; //GREG(pc, 32, riscv_core_reg_gen_pc);
reg [31:0] instr; //GREG(instr, 32, riscv_core_reg_gen_instr);
reg write; //GREG(write, 1, riscv_core_gen_write);
reg [31:0] writeaddr; //GREG(writeaddr, 32, riscv_core_gen_write);
reg [31:0] writedata; //GREG(writedata, 32, riscv_core_gen_write);
reg [3:0] writemask; //GREG(writemask, 4, riscv_core_gen_write);
reg [4:0] readreg; //GREG(readreg, 5, riscv_core_reg_gen_readreg);
reg [3:0] state; //GREG(state, 4, riscv_core_gen_state);
reg [31:0] imm; //GREG(imm, 32, riscv_core_gen_imm);
reg [4:0] dstreg; //GREG(dstreg, 5, riscv_core_gen_dstreg);
reg [31:0] dstvalue; //GREG(dstvalue, 32, riscv_core_gen_dstreg);
reg [31:0] ldaddr; //GREG(ldaddr, 2, riscv_core_gen_ldaddr);
reg [31:0] pc; //GREG(pc, 32, riscv_core_reg_gen_pc;
reg [31:0] instr; //GREG(instr, 32, riscv_core_reg_gen_instr;
reg write; //GREG(write, 1, riscv_core_gen_write;
reg [31:0] writeaddr; //GREG(writeaddr, 32, riscv_core_gen_write;
reg [31:0] writedata; //GREG(writedata, 32, riscv_core_gen_write;
reg [3:0] writemask; //GREG(writemask, 4, riscv_core_gen_write;
reg [4:0] readreg; //GREG(readreg, 5, riscv_core_reg_gen_readreg;
reg [3:0] state; //GREG(state, 4, riscv_core_gen_state;
reg [31:0] imm; //GREG(imm, 32, riscv_core_gen_imm;
reg [4:0] dstreg; //GREG(dstreg, 5, riscv_core_gen_dstreg;
reg [31:0] dstvalue; //GREG(dstvalue, 32, riscv_core_gen_dstreg;
reg [31:0] ldaddr; //GREG(ldaddr, 2, riscv_core_gen_ldaddr;
reg [4:0] divclk;
reg [31:0] lastv;
reg [31:0] lastaddr;
/* CSR register */
reg [31:0] misa; /*0301*/
reg [31:0] ucycle; /*0c00*/
reg [31:0] utime; /*0c01*/
reg [31:0] uinstret; /*0c02*/
reg [31:0] ucycleh; /*0c80*/
reg [31:0] utimeh; /*0c81*/
reg [31:0] uinstreth; /*0c82*/
reg [31:0] mcycle; /*0b00*/
reg [31:0] minstret; /*0b02*/
reg [31:0] mcycleh; /*0b80*/
reg [31:0] minstreth; /*0b82*/
reg [31:0] csr_r;
always @(posedge wClk)
if (state == `RISCVSTATE_READ_REGS)
case (bReadData[31:20])
12'h301: csr_r <= misa;
12'hc00: csr_r <= ucycle;
12'hc01: csr_r <= utime;
12'hc02: csr_r <= uinstret;
12'hc80: csr_r <= ucycleh;
12'hc81: csr_r <= utimeh;
12'hc82: csr_r <= uinstreth;
12'hb00: csr_r <= mcycle;
12'hb02: csr_r <= minstret;
12'hb80: csr_r <= mcycleh;
12'hb82: csr_r <= minstreth;
default: csr_r <= 0;
endcase
assign wWrite = write;
assign bWriteAddr = writeaddr;
assign bWriteData = writedata;
......@@ -372,9 +403,96 @@ module riscv_core(
5'h00: imm <= {{20{bReadData[31]}}, bReadData[31:20]};
5'h08: imm <= {{20{bReadData[31]}}, bReadData[31:25], bReadData[11:7]};
5'h04: imm <= {{20{bReadData[31]}}, bReadData[31:20]};
5'h1c: imm <= {27'b0, bReadData[19:15]};
endcase
end
reg[31:0] csr_v;
reg csr_op;
always @(func3 or rs1 or csr_r or imm)
case (func3)
1: /* CSRRW */ begin csr_v = rs1; csr_op = 1; end
2: /* CSRRS */ begin csr_v = csr_r | rs1; csr_op = 1; end
3: /* CSRRC */ begin csr_v = csr_r & (~rs1); csr_op = 1; end
5: /* CSRRWI */ begin csr_v = imm; csr_op = 1; end
6: /* CSRRSI */ begin csr_v = csr_r | imm; csr_op = 1; end
7: /* CSRRCI */ begin csr_v = csr_r & (~imm); csr_op = 1; end
default: begin csr_v = 0; csr_op = 0; end
endcase
//DEFINE_FUNC(riscv_core_gen_csr, "nwReset, ucycle, ucycleh, misa, mcycle, mcycleh, utime,utimeh, uinstret, uinstreth, minstret, minstreth, instr, imm, regrddata") {
always @(posedge wClk)
if (nwReset == 0) begin
misa <= 32'b0100_0000_0001_0000_0001_0001_0000_0000;// RV32IM
ucycle <= 0;
ucycleh <= 0;
mcycle <= 0;
mcycleh <= 0;
utime <= 0;
utimeh <= 0;
uinstret <= 0;
uinstreth <= 0;
minstret <= 0;
minstreth <= 0;
end
else begin
if (ucycle == 32'hffffffff) begin
ucycleh <= ucycleh + 1;
ucycle <= 0;
end
else begin
ucycle <= ucycle + 1;
end
if (utime == 32'hffffffff) begin
utimeh <= utimeh + 1;
utime <= 0;
end
else begin
utime <= utime + 1;
end
if (mcycle == 32'hffffffff) begin
mcycleh <= mcycleh + 1;
mcycle <= 0;
end
else begin
mcycle <= mcycle + 1;
end
if (state == `RISCVSTATE_EXEC_INST) begin
if (uinstret == 32'hffffffff) begin
uinstreth <= uinstreth + 1;
uinstret <= 0;
end
else begin
uinstret <= uinstret + 1;
end
if (minstret == 32'hffffffff) begin
minstreth <= minstreth + 1;
minstret <= 0;
end
else begin
minstret <= minstret + 1;
end
if (opcode == 5'h1c) begin /* CSR */
if (csr_op) begin
case (instr[31:20])
12'h301: misa <= csr_v;
12'hc00: ucycle <= csr_v;
12'hc01: utime <= csr_v;
12'hc02: uinstret <= csr_v;
12'hc80: ucycleh <= csr_v;
12'hc81: utimeh <= csr_v;
12'hc82: uinstreth <= csr_v;
12'hb00: mcycle <= csr_v;
12'hb02: minstret <= csr_v;
12'hb80: mcycleh <= csr_v;
12'hb82: minstreth <= csr_v;
endcase
end
end
end
end
//DEFINE_FUNC(riscv_core_reg_wr_sig, "state, dstreg, dstvalue, bReadData, instr, regrddata, pc") {
always @(state or dstreg or dstvalue or bReadData or instr or regrddata or regrddata2 or pc)
case (state)
......@@ -539,6 +657,14 @@ module riscv_core(
5'h05: begin
dstvalue = imm + pc;
end
5'h1c: begin
if (func3[1:0] != 0) begin /* csr */
dstvalue = csr_r;
end else begin
dstreg = 0;
dstvalue = 0;
end
end
5'h1b: begin
dstvalue = pc + 4;
end
......
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