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examples/hdl4se_riscv/de2/de2_riscv_axi.v
浏览文件 @ 26920e33
......@@ -649,4 +649,19 @@ module uart_fifo_gen (
.q(q),
.usedw(usedw));
endmodule
module riscv_ram(
input wClk,
input wWrite,
input [31:0] bWriteAddr,
input [3:0] bWriteMask,
input [31:0] bWriteData,
input wRead,
input [31:0] bReadAddr,
output [31:0] bReadData
);
ram4kB ram(.clock(wClk), .address(bWriteAddr), .byteena(~bWriteMask), .data(bWriteData), .wren(wWrite), .q(bReadData));
endmodule
\ No newline at end of file
examples/hdl4se_riscv/de2/qsys/.qsys_edit/preferences.xml
浏览文件 @ 26920e33
......@@ -3,7 +3,7 @@
<debug showDebugMenu="0" />
<systemtable>
<columns>
<connections preferredWidth="79" />
<connections preferredWidth="63" />
<irq preferredWidth="34" />
</columns>
</systemtable>
......@@ -14,6 +14,7 @@
<frequency preferredWidth="115" />
</columns>
</clocktable>
<window width="1100" height="1020" x="1187" y="706" />
<library expandedCategories="Library,Project" />
<window width="1100" height="800" x="1187" y="706" />
<library
expandedCategories="Library/Memories and Memory Controllers/External Memory Interfaces,Library,Library/Memories and Memory Controllers,Library/Memories and Memory Controllers/External Memory Interfaces/SDRAM Interfaces,Project" />
</preferences>
examples/hdl4se_riscv/de2/qsys/.qsys_edit/sdram.xml 0 → 100644
浏览文件 @ 26920e33
此差异已折叠。
examples/hdl4se_riscv/de2/qsys/sdram.bsf 0 → 100644
浏览文件 @ 26920e33
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 624 520)
(text "sdram" (rect 294 -1 319 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 504 20 516)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 256 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 256 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "new_sdram_controller_0_reset_reset_n" (rect 0 0 161 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_reset_reset_n" (rect 4 141 220 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 256 152)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "new_sdram_controller_0_s1_address[24..0]" (rect 0 0 177 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_address[24..0]" (rect 4 181 244 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 256 192)(line_width 3))
)
(port
(pt 0 208)
(input)
(text "new_sdram_controller_0_s1_byteenable_n[3..0]" (rect 0 0 192 12)(font "Arial" (font_size 8)))
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(line (pt 0 208)(pt 256 208)(line_width 3))
)
(port
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(line (pt 0 224)(pt 256 224)(line_width 1))
)
(port
(pt 0 240)
(input)
(text "new_sdram_controller_0_s1_writedata[31..0]" (rect 0 0 177 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_writedata[31..0]" (rect 4 229 256 240)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 256 240)(line_width 3))
)
(port
(pt 0 256)
(input)
(text "new_sdram_controller_0_s1_read_n" (rect 0 0 147 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_read_n" (rect 4 245 196 256)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 256 256)(line_width 1))
)
(port
(pt 0 272)
(input)
(text "new_sdram_controller_0_s1_write_n" (rect 0 0 147 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_write_n" (rect 4 261 202 272)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 256 272)(line_width 1))
)
(port
(pt 624 72)
(output)
(text "clk_0_clk_reset_reset_n" (rect 0 0 100 12)(font "Arial" (font_size 8)))
(text "clk_0_clk_reset_reset_n" (rect 499 61 637 72)(font "Arial" (font_size 8)))
(line (pt 624 72)(pt 368 72)(line_width 1))
)
(port
(pt 0 288)
(output)
(text "new_sdram_controller_0_s1_readdata[31..0]" (rect 0 0 177 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_readdata[31..0]" (rect 4 277 250 288)(font "Arial" (font_size 8)))
(line (pt 0 288)(pt 256 288)(line_width 3))
)
(port
(pt 0 304)
(output)
(text "new_sdram_controller_0_s1_readdatavalid" (rect 0 0 171 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_readdatavalid" (rect 4 293 238 304)(font "Arial" (font_size 8)))
(line (pt 0 304)(pt 256 304)(line_width 1))
)
(port
(pt 0 320)
(output)
(text "new_sdram_controller_0_s1_waitrequest" (rect 0 0 162 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_s1_waitrequest" (rect 4 309 226 320)(font "Arial" (font_size 8)))
(line (pt 0 320)(pt 256 320)(line_width 1))
)
(port
(pt 0 360)
(output)
(text "new_sdram_controller_0_wire_addr[12..0]" (rect 0 0 167 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_addr[12..0]" (rect 4 349 238 360)(font "Arial" (font_size 8)))
(line (pt 0 360)(pt 256 360)(line_width 3))
)
(port
(pt 0 376)
(output)
(text "new_sdram_controller_0_wire_ba[1..0]" (rect 0 0 154 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_ba[1..0]" (rect 4 365 220 376)(font "Arial" (font_size 8)))
(line (pt 0 376)(pt 256 376)(line_width 3))
)
(port
(pt 0 392)
(output)
(text "new_sdram_controller_0_wire_cas_n" (rect 0 0 151 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_cas_n" (rect 4 381 202 392)(font "Arial" (font_size 8)))
(line (pt 0 392)(pt 256 392)(line_width 1))
)
(port
(pt 0 408)
(output)
(text "new_sdram_controller_0_wire_cke" (rect 0 0 140 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_cke" (rect 4 397 190 408)(font "Arial" (font_size 8)))
(line (pt 0 408)(pt 256 408)(line_width 1))
)
(port
(pt 0 424)
(output)
(text "new_sdram_controller_0_wire_cs_n" (rect 0 0 146 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_cs_n" (rect 4 413 196 424)(font "Arial" (font_size 8)))
(line (pt 0 424)(pt 256 424)(line_width 1))
)
(port
(pt 0 456)
(output)
(text "new_sdram_controller_0_wire_dqm[3..0]" (rect 0 0 164 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_dqm[3..0]" (rect 4 445 226 456)(font "Arial" (font_size 8)))
(line (pt 0 456)(pt 256 456)(line_width 3))
)
(port
(pt 0 472)
(output)
(text "new_sdram_controller_0_wire_ras_n" (rect 0 0 149 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_ras_n" (rect 4 461 202 472)(font "Arial" (font_size 8)))
(line (pt 0 472)(pt 256 472)(line_width 1))
)
(port
(pt 0 488)
(output)
(text "new_sdram_controller_0_wire_we_n" (rect 0 0 147 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_we_n" (rect 4 477 196 488)(font "Arial" (font_size 8)))
(line (pt 0 488)(pt 256 488)(line_width 1))
)
(port
(pt 0 440)
(bidir)
(text "new_sdram_controller_0_wire_dq[31..0]" (rect 0 0 159 12)(font "Arial" (font_size 8)))
(text "new_sdram_controller_0_wire_dq[31..0]" (rect 4 429 226 440)(font "Arial" (font_size 8)))
(line (pt 0 440)(pt 256 440)(line_width 3))
)
(drawing
(text "clk" (rect 241 43 500 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 261 67 540 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 227 83 484 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 261 107 564 224)(font "Arial" (color 0 0 0)))
(text "clk_0_clk_reset" (rect 369 43 828 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 332 67 706 144)(font "Arial" (color 0 0 0)))
(text "new_sdram_controller_0_reset" (rect 73 123 314 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 261 147 564 304)(font "Arial" (color 0 0 0)))
(text "new_sdram_controller_0_s1" (rect 91 163 332 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "address" (rect 261 187 564 384)(font "Arial" (color 0 0 0)))
(text "byteenable_n" (rect 261 203 594 416)(font "Arial" (color 0 0 0)))
(text "chipselect" (rect 261 219 582 448)(font "Arial" (color 0 0 0)))
(text "writedata" (rect 261 235 576 480)(font "Arial" (color 0 0 0)))
(text "read_n" (rect 261 251 558 512)(font "Arial" (color 0 0 0)))
(text "write_n" (rect 261 267 564 544)(font "Arial" (color 0 0 0)))
(text "readdata" (rect 261 283 570 576)(font "Arial" (color 0 0 0)))
(text "readdatavalid" (rect 261 299 600 608)(font "Arial" (color 0 0 0)))
(text "waitrequest" (rect 261 315 588 640)(font "Arial" (color 0 0 0)))
(text "new_sdram_controller_0_wire" (rect 78 331 318 675)(font "Arial" (color 128 0 0)(font_size 9)))
(text "addr" (rect 261 355 546 720)(font "Arial" (color 0 0 0)))
(text "ba" (rect 261 371 534 752)(font "Arial" (color 0 0 0)))
(text "cas_n" (rect 261 387 552 784)(font "Arial" (color 0 0 0)))
(text "cke" (rect 261 403 540 816)(font "Arial" (color 0 0 0)))
(text "cs_n" (rect 261 419 546 848)(font "Arial" (color 0 0 0)))
(text "dq" (rect 261 435 534 880)(font "Arial" (color 0 0 0)))
(text "dqm" (rect 261 451 540 912)(font "Arial" (color 0 0 0)))
(text "ras_n" (rect 261 467 552 944)(font "Arial" (color 0 0 0)))
(text "we_n" (rect 261 483 546 976)(font "Arial" (color 0 0 0)))
(text " sdram " (rect 594 504 1230 1018)(font "Arial" ))
(line (pt 257 52)(pt 257 76)(line_width 1))
(line (pt 258 52)(pt 258 76)(line_width 1))
(line (pt 257 92)(pt 257 116)(line_width 1))
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(line (pt 624 0)(pt 624 520)(line_width 1))
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)
examples/hdl4se_riscv/de2/qsys/sdram.html 0 → 100644
浏览文件 @ 26920e33
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for sdram</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
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table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">sdram</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2021.09.23.20:17:56</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk_0&#160;</td>
<td class="main" rowspan="2">sdram</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/>All Components
<br/>&#160;&#160;
<a href="#module_new_sdram_controller_0"><b>new_sdram_controller_0</b>
</a> altera_avalon_new_sdram_controller 13.1</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_new_sdram_controller_0"><b>new_sdram_controller_0</b>
</a>
</td>
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
</tr>
</table>
<a name="module_clk_0"> </a>
<div>
<hr/>
<h2>clk_0</h2>clock_source v13.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">inputClockFrequency</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">resetSynchronousEdges</td>
<td class="parametervalue">NONE</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<a name="module_new_sdram_controller_0"> </a>
<div>
<hr/>
<h2>new_sdram_controller_0</h2>altera_avalon_new_sdram_controller v13.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="2">
<a href="#module_clk_0">clk_0</a>
</td>
<td class="from">clk&#160;&#160;</td>
<td class="main" rowspan="2">new_sdram_controller_0</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">TAC</td>
<td class="parametervalue">5.5</td>
</tr>
<tr>
<td class="parametername">TRCD</td>
<td class="parametervalue">20.0</td>
</tr>
<tr>
<td class="parametername">TRFC</td>
<td class="parametervalue">70.0</td>
</tr>
<tr>
<td class="parametername">TRP</td>
<td class="parametervalue">20.0</td>
</tr>
<tr>
<td class="parametername">TWR</td>
<td class="parametervalue">14.0</td>
</tr>
<tr>
<td class="parametername">casLatency</td>
<td class="parametervalue">3</td>
</tr>
<tr>
<td class="parametername">columnWidth</td>
<td class="parametervalue">10</td>
</tr>
<tr>
<td class="parametername">dataWidth</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">generateSimulationModel</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">initRefreshCommands</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">model</td>
<td class="parametervalue">single_Micron_MT48LC4M32B2_7_chip</td>
</tr>
<tr>
<td class="parametername">numberOfBanks</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">numberOfChipSelects</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">pinsSharedViaTriState</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">powerUpDelay</td>
<td class="parametervalue">100.0</td>
</tr>
<tr>
<td class="parametername">refreshPeriod</td>
<td class="parametervalue">15.625</td>
</tr>
<tr>
<td class="parametername">rowWidth</td>
<td class="parametervalue">13</td>
</tr>
<tr>
<td class="parametername">masteredTristateBridgeSlave</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">TMRD</td>
<td class="parametervalue">3</td>
</tr>
<tr>
<td class="parametername">initNOPDelay</td>
<td class="parametervalue">0.0</td>
</tr>
<tr>
<td class="parametername">registerDataIn</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">clockRate</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">componentName</td>
<td class="parametervalue">sdram_new_sdram_controller_0</td>
</tr>
<tr>
<td class="parametername">size</td>
<td class="parametervalue">134217728</td>
</tr>
<tr>
<td class="parametername">addressWidth</td>
<td class="parametervalue">25</td>
</tr>
<tr>
<td class="parametername">bankWidth</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">CAS_LATENCY</td>
<td class="parametervalue">3</td>
</tr>
<tr>
<td class="parametername">CONTENTS_INFO</td>
<td class="parametervalue"></td>
</tr>
<tr>
<td class="parametername">INIT_NOP_DELAY</td>
<td class="parametervalue">0.0</td>
</tr>
<tr>
<td class="parametername">INIT_REFRESH_COMMANDS</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">IS_INITIALIZED</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">POWERUP_DELAY</td>
<td class="parametervalue">100.0</td>
</tr>
<tr>
<td class="parametername">REFRESH_PERIOD</td>
<td class="parametervalue">15.625</td>
</tr>
<tr>
<td class="parametername">REGISTER_DATA_IN</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">SDRAM_ADDR_WIDTH</td>
<td class="parametervalue">25</td>
</tr>
<tr>
<td class="parametername">SDRAM_BANK_WIDTH</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">SDRAM_COL_WIDTH</td>
<td class="parametervalue">10</td>
</tr>
<tr>
<td class="parametername">SDRAM_DATA_WIDTH</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">SDRAM_NUM_BANKS</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">SDRAM_NUM_CHIPSELECTS</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">SDRAM_ROW_WIDTH</td>
<td class="parametervalue">13</td>
</tr>
<tr>
<td class="parametername">SHARED_DATA</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">SIM_MODEL_BASE</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">STARVATION_INDICATOR</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">TRISTATE_BRIDGE_SLAVE</td>
<td class="parametervalue">""</td>
</tr>
<tr>
<td class="parametername">T_AC</td>
<td class="parametervalue">5.5</td>
</tr>
<tr>
<td class="parametername">T_MRD</td>
<td class="parametervalue">3</td>
</tr>
<tr>
<td class="parametername">T_RCD</td>
<td class="parametervalue">20.0</td>
</tr>
<tr>
<td class="parametername">T_RFC</td>
<td class="parametervalue">70.0</td>
</tr>
<tr>
<td class="parametername">T_RP</td>
<td class="parametervalue">20.0</td>
</tr>
<tr>
<td class="parametername">T_WR</td>
<td class="parametervalue">14.0</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.01 seconds</td>
</tr>
</table>
</body>
</html>
examples/hdl4se_riscv/de2/qsys/sdram.qsys 0 → 100644
浏览文件 @ 26920e33
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element new_sdram_controller_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE115F29C7" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface
name="clk_0_clk_reset"
internal="clk_0.clk_reset"
type="reset"
dir="start" />
<interface
name="new_sdram_controller_0_reset"
internal="new_sdram_controller_0.reset"
type="reset"
dir="end" />
<interface
name="new_sdram_controller_0_s1"
internal="new_sdram_controller_0.s1"
type="avalon"
dir="end" />
<interface
name="new_sdram_controller_0_wire"
internal="new_sdram_controller_0.wire"
type="conduit"
dir="end" />
<module kind="clock_source" version="13.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
kind="altera_avalon_new_sdram_controller"
version="13.1"
enabled="1"
name="new_sdram_controller_0">
<parameter name="TAC" value="5.5" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="14.0" />
<parameter name="casLatency" value="3" />
<parameter name="columnWidth" value="10" />
<parameter name="dataWidth" value="32" />
<parameter name="generateSimulationModel" value="true" />
<parameter name="initRefreshCommands" value="2" />
<parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="100.0" />
<parameter name="refreshPeriod" value="15.625" />
<parameter name="rowWidth" value="13" />
<parameter name="masteredTristateBridgeSlave" value="0" />
<parameter name="TMRD" value="3" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="registerDataIn" value="true" />
<parameter name="clockRate" value="50000000" />
<parameter name="componentName">$${FILENAME}_new_sdram_controller_0</parameter>
</module>
<connection
kind="clock"
version="13.1"
start="clk_0.clk"
end="new_sdram_controller_0.clk" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
</system>
examples/hdl4se_riscv/de2/qsys/sdram.sopcinfo 0 → 100644
浏览文件 @ 26920e33
此差异已折叠。
examples/hdl4se_riscv/de2/qsys/sdram/synthesis/sdram.qip 0 → 100644
浏览文件 @ 26920e33
set_global_assignment -entity "sdram" -library "sdram" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "sdram" -library "sdram" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "sdram" -library "sdram" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "sdram" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../sdram.sopcinfo"]
set_global_assignment -entity "sdram" -library "sdram" -name SLD_INFO "QSYS_NAME sdram HAS_SOPCINFO 1 GENERATION_ID 1632399476"
set_global_assignment -library "sdram" -name MISC_FILE [file join $::quartus(qip_path) "../../sdram.cmp"]
set_global_assignment -library "sdram" -name SLD_FILE [file join $::quartus(qip_path) "sdram.debuginfo"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "sdram" -name MISC_FILE [file join $::quartus(qip_path) "../../sdram.qsys"]
set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "sdram.v"]
set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sdram_new_sdram_controller_0.v"]
set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sdram_new_sdram_controller_0_test_component.v"]
set_global_assignment -entity "sdram_new_sdram_controller_0" -library "sdram" -name IP_TOOL_NAME "altera_avalon_new_sdram_controller"
set_global_assignment -entity "sdram_new_sdram_controller_0" -library "sdram" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "sdram_new_sdram_controller_0" -library "sdram" -name IP_TOOL_ENV "Qsys"
examples/hdl4se_riscv/de2/qsys/sdram/synthesis/sdram.v 0 → 100644
浏览文件 @ 26920e33
// sdram.v
// Generated using ACDS version 13.1 162 at 2021.09.23.20:17:56
`timescale 1 ps / 1 ps
module sdram (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire clk_0_clk_reset_reset_n, // clk_0_clk_reset.reset_n
input wire new_sdram_controller_0_reset_reset_n, // new_sdram_controller_0_reset.reset_n
input wire [24:0] new_sdram_controller_0_s1_address, // new_sdram_controller_0_s1.address
input wire [3:0] new_sdram_controller_0_s1_byteenable_n, // .byteenable_n
input wire new_sdram_controller_0_s1_chipselect, // .chipselect
input wire [31:0] new_sdram_controller_0_s1_writedata, // .writedata
input wire new_sdram_controller_0_s1_read_n, // .read_n
input wire new_sdram_controller_0_s1_write_n, // .write_n
output wire [31:0] new_sdram_controller_0_s1_readdata, // .readdata
output wire new_sdram_controller_0_s1_readdatavalid, // .readdatavalid
output wire new_sdram_controller_0_s1_waitrequest, // .waitrequest
output wire [12:0] new_sdram_controller_0_wire_addr, // new_sdram_controller_0_wire.addr
output wire [1:0] new_sdram_controller_0_wire_ba, // .ba
output wire new_sdram_controller_0_wire_cas_n, // .cas_n
output wire new_sdram_controller_0_wire_cke, // .cke
output wire new_sdram_controller_0_wire_cs_n, // .cs_n
inout wire [31:0] new_sdram_controller_0_wire_dq, // .dq
output wire [3:0] new_sdram_controller_0_wire_dqm, // .dqm
output wire new_sdram_controller_0_wire_ras_n, // .ras_n
output wire new_sdram_controller_0_wire_we_n // .we_n
);
sdram_new_sdram_controller_0 new_sdram_controller_0 (
.clk (clk_clk), // clk.clk
.reset_n (new_sdram_controller_0_reset_reset_n), // reset.reset_n
.az_addr (new_sdram_controller_0_s1_address), // s1.address
.az_be_n (new_sdram_controller_0_s1_byteenable_n), // .byteenable_n
.az_cs (new_sdram_controller_0_s1_chipselect), // .chipselect
.az_data (new_sdram_controller_0_s1_writedata), // .writedata
.az_rd_n (new_sdram_controller_0_s1_read_n), // .read_n
.az_wr_n (new_sdram_controller_0_s1_write_n), // .write_n
.za_data (new_sdram_controller_0_s1_readdata), // .readdata
.za_valid (new_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.za_waitrequest (new_sdram_controller_0_s1_waitrequest), // .waitrequest
.zs_addr (new_sdram_controller_0_wire_addr), // wire.export
.zs_ba (new_sdram_controller_0_wire_ba), // .export
.zs_cas_n (new_sdram_controller_0_wire_cas_n), // .export
.zs_cke (new_sdram_controller_0_wire_cke), // .export
.zs_cs_n (new_sdram_controller_0_wire_cs_n), // .export
.zs_dq (new_sdram_controller_0_wire_dq), // .export
.zs_dqm (new_sdram_controller_0_wire_dqm), // .export
.zs_ras_n (new_sdram_controller_0_wire_ras_n), // .export
.zs_we_n (new_sdram_controller_0_wire_we_n) // .export
);
assign clk_0_clk_reset_reset_n = reset_reset_n;
endmodule
examples/hdl4se_riscv/doc/riscv_simd.txt 0 → 100644
浏览文件 @ 26920e33
每个线程设置栈，栈元素：<PC> <active>
do {
if (_haschar()) {
_gets(buf, sizeof(buf)-1);
break;
}
count = count + 1;
*(unsigned int*)0xf0000004 = count;
WATCHDOGSET;
} while (1);
_puts("\n\r:");
_puts(buf);
_puts("\n\r");
if (_haschar()) {
a28: e34ff0ef jal x1,5c <_haschar>
a2c: 00050793 addi x15,x10,0
a30: 04078663 beq x15,x0,a7c <main+0xe8> a7c, a34, 0011
_gets(buf, sizeof(buf)-1)
a34: f7840793 addi x15,x8,-136
a38: 02700593 addi x11,x0,39
a3c: 00078513 addi x10,x15,0
a40: f78ff0ef jal x1,1b8 <_gets>
a44: 00000013 addi x0,x0,0
_puts("\n\t");
a48: 000017b7 lui x15,0x1
a4c: e0c78513 addi x10,x15,-500 # e0c <main+0x478>
a50: ef4ff0ef jal x1,144 <_puts>
_puts(buf);
a54: f7840793 addi x15,x8,-136
a58: 00078513 addi x10,x15,0
a5c: ee8ff0ef jal x1,144 <_puts>
a60: 000017b7 lui x15,0x1
_puts("\n\t");
a64: e0078513 addi x10,x15,-512 # e00 <main+0x46c>
a68: edcff0ef jal x1,144 <_puts>
a6c: f7844703 lbu x14,-136(x8)
a70: 06400793 addi x15,x0,100
a74: 06f71863 bne x14,x15,ae4 <main+0x150> a78, ae4, 0011
break;
a78: 0340006f jal x0,aac <main+0x118>
count = count+1;
a7c: fdc42783 lw x15,-36(x8)
a80: 00178793 addi x15,x15,1
a84: fcf42e23 sw x15,-36(x8)
*(unsigned int*)0xf0000004 = count;
a88: f00007b7 lui x15,0xf0000
a8c: 00478793 addi x15,x15,4 # f0000004 <_end+0xeffff1cc>
a90: fdc42703 lw x14,-36(x8)
a94: 00e7a023 sw x14,0(x15)
a98: 02faf537 lui x10,0x2faf
WATCHDOGSET;
a9c: 08050513 addi x10,x10,128 # 2faf080 <_end+0x2fae248>
aa0: 00000593 addi x11,x0,0
aa4: d68ff0ef jal x1,c <watchdog_set>
jmp a28
aa8: f81ff06f jal x0,a28 <main+0x94>
aac: f7840793 addi x15,x8,-136
ab0: 00278793 addi x15,x15,2
\ No newline at end of file
examples/hdl4se_riscv/test_code/risc_simd.txt 0 → 100644
浏览文件 @ 26920e33
3:
4: b 5, 11
5: b 6, 8
6:
7: goto 9 and pop
8: goto 11
9:
10 goto 4
11: return
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