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提交 3f382ea4 编写于 作者: 饶先宏's avatar 饶先宏
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202109170631

上级 f63b6f3c
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Showing with 296 addition and 7 deletion
examples/hdl4se_riscv/verilog/axi/axi1to2.v
浏览文件 @ 3f382ea4
......@@ -122,7 +122,7 @@ module axi1to2
else if (is_M01_w)
s00_axi_awready = m01_axi_awready;
else
s00_axi_awready = 0;
s00_axi_awready = 1;
always @(*)
if (is_M00_w)
......@@ -130,7 +130,7 @@ module axi1to2
else if (is_M01_w)
s00_axi_wready = m01_axi_wready;
else
s00_axi_wready = 0;
s00_axi_wready = 1;
always @(*)
if (is_M00_w)
......@@ -146,7 +146,7 @@ module axi1to2
else if (is_M01_w)
s00_axi_bvalid = m01_axi_bvalid;
else
s00_axi_bvalid = 0;
s00_axi_bvalid = 1;
always @(*)
if (is_M00_r_r)
......@@ -154,7 +154,7 @@ module axi1to2
else if (is_M01_r_r)
s00_axi_arready = m01_axi_arready;
else
s00_axi_arready = 0;
s00_axi_arready = 1;
always @(*)
if (is_M00_r_r)
......@@ -162,7 +162,7 @@ module axi1to2
else if (is_M01_r_r)
s00_axi_rdata = m01_axi_rdata;
else
s00_axi_rdata = 0;
s00_axi_rdata = 32'hefbeadde;
always @(*)
if (is_M00_r_r)
......@@ -178,6 +178,6 @@ module axi1to2
else if (is_M01_r_r)
s00_axi_rvalid = m01_axi_rvalid;
else
s00_axi_rvalid = 0;
s00_axi_rvalid = 1;
endmodule
\ No newline at end of file
examples/hdl4se_riscv/verilog/axi/axi1to4.v 0 → 100644
浏览文件 @ 3f382ea4
module axi1to4
#(
parameter integer M00_ADDR_MASK = 32'hfffff000,
parameter integer M00_ADDR_START = 32'h00000000,
parameter integer M01_ADDR_MASK = 32'hfffff000,
parameter integer M01_ADDR_START = 32'h00001000
parameter integer M02_ADDR_MASK = 32'he0000000,
parameter integer M02_ADDR_START = 32'h00000000,
parameter integer M03_ADDR_MASK = 32'hd0000000,
parameter integer M03_ADDR_START = 32'h00000000
)
(
input wire axi_aclk,
input wire axi_aresetn,
input wire [31 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output reg s00_axi_awready,
input wire [31 : 0] s00_axi_wdata,
input wire [3 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output reg s00_axi_wready,
output reg [1 : 0] s00_axi_bresp,
output reg s00_axi_bvalid,
input wire s00_axi_bready,
input wire [31 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output reg s00_axi_arready,
output reg [31 : 0] s00_axi_rdata,
output reg [1 : 0] s00_axi_rresp,
output reg s00_axi_rvalid,
input wire s00_axi_rready,
output wire [31 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [31 : 0] m00_axi_wdata,
output wire [3 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [31 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [31 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready,
output wire [31 : 0] m01_axi_awaddr,
output wire [2 : 0] m01_axi_awprot,
output wire m01_axi_awvalid,
input wire m01_axi_awready,
output wire [31 : 0] m01_axi_wdata,
output wire [3 : 0] m01_axi_wstrb,
output wire m01_axi_wvalid,
input wire m01_axi_wready,
input wire [1 : 0] m01_axi_bresp,
input wire m01_axi_bvalid,
output wire m01_axi_bready,
output wire [31 : 0] m01_axi_araddr,
output wire [2 : 0] m01_axi_arprot,
output wire m01_axi_arvalid,
input wire m01_axi_arready,
input wire [31 : 0] m01_axi_rdata,
input wire [1 : 0] m01_axi_rresp,
input wire m01_axi_rvalid,
output wire m01_axi_rready,
output wire [31 : 0] m02_axi_awaddr,
output wire [2 : 0] m02_axi_awprot,
output wire m02_axi_awvalid,
input wire m02_axi_awready,
output wire [31 : 0] m02_axi_wdata,
output wire [3 : 0] m02_axi_wstrb,
output wire m02_axi_wvalid,
input wire m02_axi_wready,
input wire [1 : 0] m02_axi_bresp,
input wire m02_axi_bvalid,
output wire m02_axi_bready,
output wire [31 : 0] m02_axi_araddr,
output wire [2 : 0] m02_axi_arprot,
output wire m02_axi_arvalid,
input wire m02_axi_arready,
input wire [31 : 0] m02_axi_rdata,
input wire [1 : 0] m02_axi_rresp,
input wire m02_axi_rvalid,
output wire m02_axi_rready,
output wire [31 : 0] m03_axi_awaddr,
output wire [2 : 0] m03_axi_awprot,
output wire m03_axi_awvalid,
input wire m03_axi_awready,
output wire [31 : 0] m03_axi_wdata,
output wire [3 : 0] m03_axi_wstrb,
output wire m03_axi_wvalid,
input wire m03_axi_wready,
input wire [1 : 0] m03_axi_bresp,
input wire m03_axi_bvalid,
output wire m03_axi_bready,
output wire [31 : 0] m03_axi_araddr,
output wire [2 : 0] m03_axi_arprot,
output wire m03_axi_arvalid,
input wire m03_axi_arready,
input wire [31 : 0] m03_axi_rdata,
input wire [1 : 0] m03_axi_rresp,
input wire m03_axi_rvalid,
output wire m03_axi_rready
);
reg [31:0] axi_araddr;
reg axi_arvalid;
always @(posedge axi_aclk)
if (~axi_aresetn) begin
axi_araddr <= 0;
axi_arvalid <= 0;
end else if (s00_axi_arvalid) begin
axi_araddr <= s00_axi_araddr;
axi_arvalid <= 1'b1;
end else if (s00_axi_rready) begin
axi_arvalid <= 1'b0;
end
wire is_M00_w = ((s00_axi_awaddr & M00_ADDR_MASK) == M00_ADDR_START);
wire is_M01_w = ((s00_axi_awaddr & M01_ADDR_MASK) == M01_ADDR_START);
wire is_M02_w = ((s00_axi_awaddr & M00_ADDR_MASK) == M02_ADDR_START);
wire is_M03_w = ((s00_axi_awaddr & M01_ADDR_MASK) == M03_ADDR_START);
wire is_M00_r = ((s00_axi_araddr & M00_ADDR_MASK) == M00_ADDR_START);
wire is_M01_r = ((s00_axi_araddr & M01_ADDR_MASK) == M01_ADDR_START);
wire is_M02_r = ((s00_axi_araddr & M00_ADDR_MASK) == M02_ADDR_START);
wire is_M03_r = ((s00_axi_araddr & M01_ADDR_MASK) == M03_ADDR_START);
wire is_M00_r_r = axi_arvalid && ((axi_araddr & M00_ADDR_MASK) == M00_ADDR_START);
wire is_M01_r_r = axi_arvalid && ((axi_araddr & M01_ADDR_MASK) == M01_ADDR_START);
wire is_M02_r_r = axi_arvalid && ((axi_araddr & M02_ADDR_MASK) == M02_ADDR_START);
wire is_M03_r_r = axi_arvalid && ((axi_araddr & M03_ADDR_MASK) == M03_ADDR_START);
assign m00_axi_awaddr = s00_axi_awaddr;
assign m00_axi_awprot = s00_axi_awprot;
assign m00_axi_awvalid = s00_axi_awvalid && is_M00_w;
assign m00_axi_wdata = s00_axi_wdata;
assign m00_axi_wstrb = s00_axi_wstrb;
assign m00_axi_wvalid = s00_axi_wvalid && is_M00_w;
assign m00_axi_bready = s00_axi_bready;
assign m00_axi_araddr = s00_axi_araddr;
assign m00_axi_arprot = s00_axi_arprot;
assign m00_axi_arvalid = s00_axi_arvalid && is_M00_r;
assign m00_axi_rready = s00_axi_rready && is_M00_r;
assign m01_axi_awaddr = s00_axi_awaddr;
assign m01_axi_awprot = s00_axi_awprot;
assign m01_axi_awvalid = s00_axi_awvalid && is_M01_w;
assign m01_axi_wdata = s00_axi_wdata;
assign m01_axi_wstrb = s00_axi_wstrb;
assign m01_axi_wvalid = s00_axi_wvalid && is_M01_w;
assign m01_axi_bready = s00_axi_bready;
assign m01_axi_araddr = s00_axi_araddr;
assign m01_axi_arprot = s00_axi_arprot;
assign m01_axi_arvalid = s00_axi_arvalid && is_M01_r;
assign m01_axi_rready = s00_axi_rready && is_M01_r;
assign m02_axi_awaddr = s00_axi_awaddr;
assign m02_axi_awprot = s00_axi_awprot;
assign m02_axi_awvalid = s00_axi_awvalid && is_m02_w;
assign m02_axi_wdata = s00_axi_wdata;
assign m02_axi_wstrb = s00_axi_wstrb;
assign m02_axi_wvalid = s00_axi_wvalid && is_m02_w;
assign m02_axi_bready = s00_axi_bready;
assign m02_axi_araddr = s00_axi_araddr;
assign m02_axi_arprot = s00_axi_arprot;
assign m02_axi_arvalid = s00_axi_arvalid && is_m02_r;
assign m02_axi_rready = s00_axi_rready && is_m02_r;
assign m03_axi_awaddr = s00_axi_awaddr;
assign m03_axi_awprot = s00_axi_awprot;
assign m03_axi_awvalid = s00_axi_awvalid && is_m03_w;
assign m03_axi_wdata = s00_axi_wdata;
assign m03_axi_wstrb = s00_axi_wstrb;
assign m03_axi_wvalid = s00_axi_wvalid && is_m03_w;
assign m03_axi_bready = s00_axi_bready;
assign m03_axi_araddr = s00_axi_araddr;
assign m03_axi_arprot = s00_axi_arprot;
assign m03_axi_arvalid = s00_axi_arvalid && is_m03_r;
assign m03_axi_rready = s00_axi_rready && is_m03_r;
always @(*)
if (is_M00_w)
s00_axi_awready = m00_axi_awready;
else if (is_M01_w)
s00_axi_awready = m01_axi_awready;
else if (is_M02_w)
s00_axi_awready = m02_axi_awready;
else if (is_M03_w)
s00_axi_awready = m03_axi_awready;
else
s00_axi_awready = 1;
always @(*)
if (is_M00_w)
s00_axi_wready = m00_axi_wready;
else if (is_M01_w)
s00_axi_wready = m01_axi_wready;
else if (is_M02_w)
s00_axi_wready = m02_axi_wready;
else if (is_M03_w)
s00_axi_wready = m03_axi_wready;
else
s00_axi_wready = 1;
always @(*)
if (is_M00_w)
s00_axi_bresp = m00_axi_bresp;
else if (is_M01_w)
s00_axi_bresp = m01_axi_bresp;
else if (is_M02_w)
s00_axi_bresp = m02_axi_bresp;
else if (is_M03_w)
s00_axi_bresp = m03_axi_bresp;
else
s00_axi_bresp = 0;
always @(*)
if (is_M00_w)
s00_axi_bvalid = m00_axi_bvalid;
else if (is_M01_w)
s00_axi_bvalid = m01_axi_bvalid;
else if (is_M02_w)
s00_axi_bvalid = m02_axi_bvalid;
else if (is_M03_w)
s00_axi_bvalid = m03_axi_bvalid;
else
s00_axi_bvalid = 1;
always @(*)
if (is_M00_r_r)
s00_axi_arready = m00_axi_arready;
else if (is_M01_r_r)
s00_axi_arready = m01_axi_arready;
else if (is_M02_r_r)
s00_axi_arready = m02_axi_arready;
else if (is_M03_r_r)
s00_axi_arready = m03_axi_arready;
else
s00_axi_arready = 1;
always @(*)
if (is_M00_r_r)
s00_axi_rdata = m00_axi_rdata;
else if (is_M01_r_r)
s00_axi_rdata = m01_axi_rdata;
else if (is_M02_r_r)
s00_axi_rdata = m02_axi_rdata;
else if (is_M03_r_r)
s00_axi_rdata = m03_axi_rdata;
else
s00_axi_rdata = 32'hefbeadde;
always @(*)
if (is_M00_r_r)
s00_axi_rresp = m00_axi_rresp;
else if (is_M01_r_r)
s00_axi_rresp = m01_axi_rresp;
else if (is_M02_r_r)
s00_axi_rresp = m02_axi_rresp;
else if (is_M03_r_r)
s00_axi_rresp = m03_axi_rresp;
else
s00_axi_rresp = 0;
always @(*)
if (is_M00_r_r)
s00_axi_rvalid = m00_axi_rvalid;
else if (is_M01_r_r)
s00_axi_rvalid = m01_axi_rvalid;
else if (is_M02_r_r)
s00_axi_rvalid = m02_axi_rvalid;
else if (is_M03_r_r)
s00_axi_rvalid = m03_axi_rvalid;
else
s00_axi_rvalid = 1;
endmodule
\ No newline at end of file
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v
浏览文件 @ 3f382ea4
......@@ -89,7 +89,7 @@ module riscv_core_with_axi_master (
regfile regs(regno, regena, m00_axi_aclk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, m00_axi_aclk, regwrdata2, regwren2, regrddata2);
`define ALTERA_
`define ALTERA
`ifdef ALTERA
ram4kB ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(isramwriteaddr ? wWrite : 1'b0), .q(bReadDataRam));
......
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