202109172123

examples/hdl4se_riscv/verilog/led_key/led_key.v

@@ -94,6 +94,8 @@
 
 	reg [1 : 0] 	axi_bresp;
 	reg  			axi_bvalid;
+
+	reg		        wen;
 	
 	assign s00_axi_bresp	= axi_bresp;
 	assign s00_axi_bvalid	= axi_bvalid;	
@@ -114,7 +116,9 @@
 	begin
 		if (~s00_axi_aresetn) begin
 			cpucount <= 32'hffffffff;
-	    end else if (axi_awvalid && axi_wvalid) begin
+			wen <= 1;
+	    end else if (axi_awvalid && axi_wvalid && wen) begin
+			wen <= 0;
 			if (axi_awaddr == 4) begin
 				cpucount <= {axi_wstrb[3] ? axi_wdata[31:24] : cpucount[31:24], 
 							 axi_wstrb[2] ? axi_wdata[23:16] : cpucount[23:16],
@@ -122,7 +126,9 @@
 							 axi_wstrb[0] ? axi_wdata[7:0]   : cpucount[7:0]
 							 };
 			end
-	    end
+	    end else begin
+			wen <= 1;
+		end
 	end    
 
 	reg  			axi_arready;

examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v

@@ -89,7 +89,7 @@ module riscv_core_with_axi_master (
     regfile    regs(regno, regena, m00_axi_aclk, regwrdata, regwren, regrddata);
     regfile    regs2(regno2, regena2, m00_axi_aclk, regwrdata2, regwren2, regrddata2);
 
-`define ALTERA_
+`define ALTERA
 
 `ifdef ALTERA
 	ram4kB    ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(isramwriteaddr ? wWrite : 1'b0), .q(bReadDataRam));
@@ -177,8 +177,7 @@ module riscv_core_with_axi_master (
 		writeready <= 1'b0;
 	else if (~writeready) 
 		writeready <= m00_axi_bvalid || write_local || isramwriteaddr;
-	else
-		writeready <= 0;
+	
 
 	always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
 	begin

examples/hdl4se_riscv/verilog/uart/hdl4se_uart_ctrl_axi.v

@@ -179,6 +179,8 @@ module hdl4se_uart_ctrl_axi
 
 	reg [1 : 0] 	axi_bresp;
 	reg  			axi_bvalid;
+
+	reg		        wen;
 	
 	assign s00_axi_bresp	= axi_bresp;
 	assign s00_axi_bvalid	= axi_bvalid;	
@@ -200,8 +202,10 @@ module hdl4se_uart_ctrl_axi
 		if (~s00_axi_aresetn) begin
 			divsor <= 50000000 / 115200;
 			send_buf_write <= 0;
-	    end else if (axi_awvalid && axi_wvalid) begin
+			wen <= 1;
+	    end else if (axi_awvalid && axi_wvalid && wen) begin
 			send_buf_write <= 0;
+			wen <= 0;
 			if ((axi_awaddr & 4'hf) == 4'h4) begin
 				send_buf_data <= axi_wdata[7:0];
 				send_buf_write <= ~recv_buf_full;
@@ -210,6 +214,7 @@ module hdl4se_uart_ctrl_axi
 			end
 	    end else begin
 			send_buf_write <= 0;
+			wen <= 1;
 		end
 	end