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提交 585e01f6 编写于 作者: 饶先宏's avatar 饶先宏
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Revert "Revert "202109140638"" 

This reverts commit 9862c81c.
上级 9862c81c
展开全部 隐藏空白更改
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Showing with 1967 addition and 3476 deletion
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v
浏览文件 @ 585e01f6
......@@ -2,55 +2,44 @@
`timescale 1 ns / 1 ps
module riscv_core_with_axi_master (
// clock and reset
input wire wClk,
input wire nwReset,
// Write Address
output wire wAWValid,
output wire [31 : 0] bAWAddr,
output wire [2 : 0] bAWProt,
input wire wAWReady,
// Write Data
output wire wWValid,
output wire [31 : 0] bWData,
output wire [3 : 0] bWStrb,
input wire wWReady,
// Write Response
output wire wBReady,
input wire [1 : 0] bBResp,
input wire wBValid,
// ReadAddr
output wire wARValid,
output wire [31 : 0] bARAddr,
output wire [2 : 0] bARProt,
input wire wARReady,
//ReadData
output wire wRReady,
input wire wRValid,
input wire [31 : 0] bRData,
input wire [1 : 0] bRResp
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [31 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [31 : 0] m00_axi_wdata,
output wire [3 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [31 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [31 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
reg axi_awvalid; assign wAWValid = axi_awvalid;
reg [31:0] axi_awaddr; assign bAWAddr = axi_awaddr;
assign bAWProt = 3'b000;
reg axi_awvalid; assign m00_axi_awaddr = axi_awvalid;
reg [31:0] axi_awaddr; assign m00_axi_awaddr = axi_awaddr;
assign m00_axi_awprot = 3'b000;
reg axi_wvalid; assign wWValid = axi_wvalid;
reg [31:0] axi_wdata; assign bWData = axi_wdata;
reg [3:0] axi_wstrb; assign bWStrb = axi_wstrb;
reg axi_wvalid; assign m00_axi_wvalid = axi_wvalid;
reg [31:0] axi_wdata; assign m00_axi_wdata = axi_wdata;
reg [3:0] axi_wstrb; assign m00_axi_wstrb = axi_wstrb;
assign wBReady = 1'b1;
assign m00_axi_bready = 1'b1;
reg axi_arvalid; assign wARValid = axi_arvalid;
reg [31:0] axi_araddr; assign bARAddr = axi_araddr;
assign bARProt = 3'b001;
reg axi_arvalid; assign m00_axi_arvalid = axi_arvalid;
reg [31:0] axi_araddr; assign m00_axi_araddr = axi_araddr;
assign m00_axi_arprot = 3'b001;
assign wRReady = 1'b1;
assign m00_axi_rready = 1'b1;
wire wWrite, wRead, wReadReady, wWriteReady;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
......@@ -70,8 +59,8 @@ module riscv_core_with_axi_master (
reg [31:0] lastreadaddr;
reg lastread;
always @(posedge wClk)
if (~nwReset) begin
always @(posedge m00_axi_aclk)
if (~m00_axi_aresetn) begin
lastreadaddr <= 0;
lastread <= 0;
end else begin
......@@ -80,11 +69,11 @@ module riscv_core_with_axi_master (
end
assign bReadData =
((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? bRData : (
((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? m00_axi_rdata : (
((lastreadaddr & 32'hff00_0000) == 32'h0000_0000) ? bReadDataRam : (32'h0)
);
assign wReadReady = ((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? wRValid : (
assign wReadReady = ((lastreadaddr & 32'hf000_0000) == 32'hf000_0000) ? m00_axi_rvalid : (
((lastreadaddr & 32'hfff0_0000) == 32'h0000_0000) ? lastread : (0)
);
......@@ -95,24 +84,24 @@ module riscv_core_with_axi_master (
reg [4:0] lastregno;
reg [4:0] lastregno2;
always @(posedge wClk) begin
always @(posedge m00_axi_aclk) begin
lastregno <= regno;
lastregno2 <= regno2;
end
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
regfile regs(regno, regena, m00_axi_aclk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, m00_axi_aclk, regwrdata2, regwren2, regrddata2);
`define ALTERA_
`ifdef ALTERA
ram4kB ram(.clock(wClk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam));
ram4kB ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam));
`else
ram4KB ram(.clka(wClk), .ena(1'b1), .addra(ramaddr), .wea(((bWriteAddr & 32'hff000000) == 0 && wWrite)?(~bWriteMask):4'b0), .dina(bWriteData) , .douta(bReadDataRam));
ram4KB ram(.clka(m00_axi_aclk), .ena(1'b1), .addra(ramaddr), .wea(((bWriteAddr & 32'hff000000) == 0 && wWrite)?(~bWriteMask):4'b0), .dina(bWriteData) , .douta(bReadDataRam));
`endif
riscv_core_v5 core(
wClk,
nwReset,
m00_axi_aclk,
m00_axi_aresetn,
wWrite,
bWriteAddr,
bWriteData,
......@@ -139,13 +128,13 @@ module riscv_core_with_axi_master (
wire writeaxi = (wWrite && ((bWriteAddr & 32'hfff00000) != 0));
reg [31:0] awaddr;
reg awvalid;
always @(posedge wClk)
if (~nwReset) begin
always @(posedge m00_axi_aclk)
if (~m00_axi_aresetn) begin
awvalid <= 1'b0;
end else if (writeaxi) begin
awaddr <= bWriteAddr;
awvalid <= 1'b1;
end else if (wAWReady) begin
end else if (m00_axi_awready) begin
awvalid <= 1'b0;
end
......@@ -159,20 +148,20 @@ module riscv_core_with_axi_master (
reg [31:0] wdata;
reg [3:0] wstrb;
reg wvalid;
always @(posedge wClk)
always @(posedge m00_axi_aclk)
begin
if (~nwReset) begin
if (~m00_axi_aresetn) begin
wvalid <= 1'b0;
end if (writeaxi) begin
wdata <= bWriteData;
wstrb <= ~bWriteMask;
wvalid <= 1'b1;
end if (wWReady) begin
end if (m00_axi_wready) begin
wvalid <= 1'b0;
end
end
assign wWriteReady = ((wWrite || wvalid) && wWReady) || writeaxi;
assign wWriteReady = ((wWrite || wvalid) && m00_axi_wready) || writeaxi;
always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
begin
......@@ -185,13 +174,13 @@ module riscv_core_with_axi_master (
//Read Address
reg [31:0] araddr;
reg arvalid;
always @(posedge wClk)
if (~nwReset) begin
always @(posedge m00_axi_aclk)
if (~m00_axi_aresetn) begin
arvalid <= 1'b0;
end else if (readaxi) begin
araddr <= bReadAddr;
arvalid <= 1'b1;
end else if (wARReady) begin
end else if (m00_axi_arready) begin
arvalid <= 1'b0;
end
......@@ -203,61 +192,3 @@ module riscv_core_with_axi_master (
endmodule
`timescale 1 ns / 1 ps
module riscv_core_with_axi_master_xilinxwrap
(
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [31 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [31 : 0] m00_axi_wdata,
output wire [3 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [31 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [31 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
riscv_core_with_axi_master riscv_core_inst (
.wClk(m00_axi_aclk),
.nwReset(m00_axi_aresetn),
.bAWAddr(m00_axi_awaddr),
.bAWProt(m00_axi_awprot),
.wAWValid(m00_axi_awvalid),
.wAWReady(m00_axi_awready),
.bWData(m00_axi_wdata),
.bWStrb(m00_axi_wstrb),
.wWValid(m00_axi_wvalid),
.wWReady(m00_axi_wready),
.bBResp(m00_axi_bresp),
.wBValid(m00_axi_bvalid),
.wBReady(m00_axi_bready),
.bARAddr(m00_axi_araddr),
.bARProt(m00_axi_arprot),
.wARValid(m00_axi_arvalid),
.wARReady(m00_axi_arready),
.bRData(m00_axi_rdata),
.bRResp(m00_axi_rresp),
.wRValid(m00_axi_rvalid),
.wRReady(m00_axi_rready)
);
endmodule
\ No newline at end of file
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.cache/wt/webtalk_pa.xml
浏览文件 @ 585e01f6
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Sep 13 22:06:07 2021">
<application name="pa" timeStamp="Tue Sep 14 06:26:18 2021">
<section name="Project Information" visible="false">
<property name="ProjectID" value="a22297d9082e42c7bf714eb0954ec847" type="ProjectID"/>
<property name="ProjectIteration" value="37" type="ProjectIteration"/>
<property name="ProjectIteration" value="40" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
......@@ -18,29 +18,29 @@ This means code written to parse this file will need to be revisited each subseq
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="7" type="JavaHandler"/>
<property name="AutoConnectTarget" value="5" type="JavaHandler"/>
<property name="AutoConnectTarget" value="6" type="JavaHandler"/>
<property name="CoreView" value="3" type="JavaHandler"/>
<property name="CreateBlockDesign" value="1" type="JavaHandler"/>
<property name="CreateTopHDL" value="1" type="JavaHandler"/>
<property name="CustomizeCore" value="2" type="JavaHandler"/>
<property name="CustomizeRSBBlock" value="10" type="JavaHandler"/>
<property name="EditDelete" value="12" type="JavaHandler"/>
<property name="EditProperties" value="2" type="JavaHandler"/>
<property name="EditDelete" value="17" type="JavaHandler"/>
<property name="EditProperties" value="3" type="JavaHandler"/>
<property name="ExitApp" value="5" type="JavaHandler"/>
<property name="IPPackagerWizardHandler" value="4" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="21" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="7" type="JavaHandler"/>
<property name="OpenBlockDesign" value="13" type="JavaHandler"/>
<property name="OpenHardwareManager" value="27" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="23" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="8" type="JavaHandler"/>
<property name="OpenBlockDesign" value="17" type="JavaHandler"/>
<property name="OpenHardwareManager" value="30" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="OpenRecentTarget" value="6" type="JavaHandler"/>
<property name="ProgramDevice" value="21" type="JavaHandler"/>
<property name="ProjectSummary" value="8" type="JavaHandler"/>
<property name="RecustomizeCore" value="14" type="JavaHandler"/>
<property name="RunBitgen" value="37" type="JavaHandler"/>
<property name="OpenRecentTarget" value="7" type="JavaHandler"/>
<property name="ProgramDevice" value="23" type="JavaHandler"/>
<property name="ProjectSummary" value="9" type="JavaHandler"/>
<property name="RecustomizeCore" value="15" type="JavaHandler"/>
<property name="RunBitgen" value="40" type="JavaHandler"/>
<property name="RunImplementation" value="2" type="JavaHandler"/>
<property name="RunSynthesis" value="5" type="JavaHandler"/>
<property name="SaveRSBDesign" value="1" type="JavaHandler"/>
<property name="SaveRSBDesign" value="3" type="JavaHandler"/>
<property name="ShowProductGuide" value="1" type="JavaHandler"/>
<property name="ShowProductWebPage" value="2" type="JavaHandler"/>
<property name="ShowView" value="12" type="JavaHandler"/>
......@@ -49,16 +49,16 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SimulationRunForTime" value="46" type="JavaHandler"/>
<property name="TimingConstraintsWizard" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="2" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="10" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="13" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="ApplyRSBMultiAutomationDialog_CHECKBOX_TREE" value="6" type="GuiHandlerData"/>
<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="21" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="74" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="22" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="82" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="7" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="15" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="18" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="30" type="GuiHandlerData"/>
<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
......@@ -73,70 +73,70 @@ This means code written to parse this file will need to be revisited each subseq
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="CustomizeCoreDialog_DOCUMENTATION" value="3" type="GuiHandlerData"/>
<property name="DefineModulesDialog_ENTITY_NAME" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="183" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="145" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="193" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="161" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="11" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="2" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="9" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="10" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="20" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="22" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="32" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="21" type="GuiHandlerData"/>
<property name="MsgView_CRITICAL_WARNINGS" value="3" type="GuiHandlerData"/>
<property name="MsgView_INFORMATION_MESSAGES" value="5" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="6" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="22" type="GuiHandlerData"/>
<property name="MsgView_CRITICAL_WARNINGS" value="5" type="GuiHandlerData"/>
<property name="MsgView_INFORMATION_MESSAGES" value="6" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="7" type="GuiHandlerData"/>
<property name="NewIpWizard_CREATE_NEW_AXI4_IP_CREATE_AXI4" value="4" type="GuiHandlerData"/>
<property name="NewIpWizard_INTERFACE_MODE" value="2" type="GuiHandlerData"/>
<property name="NewIpWizard_NAME_MYIP" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_CREATE_TOP_HDL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_IP_PACKAGER_WIZARD" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_PORTS_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_PROJECT_SUMMARY" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_SAVE_RSB_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_PROJECT_SUMMARY" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_SAVE_RSB_DESIGN" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SHOW_PRODUCT_GUIDE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SHOW_PRODUCT_WEBPAGE" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RESTART" value="18" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="94" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="15" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="PAViews_ADDRESS_EDITOR" value="2" type="GuiHandlerData"/>
<property name="PAViews_ADDRESS_EDITOR" value="3" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="13" type="GuiHandlerData"/>
<property name="PAViews_IP_CATALOG" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="34" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="39" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PAViews_SYSTEM" value="1" type="GuiHandlerData"/>
<property name="PlanAheadTab_REFRESH_CHANGED_MODULES" value="22" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="21" type="GuiHandlerData"/>
<property name="PAViews_SYSTEM" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_REFRESH_CHANGED_MODULES" value="26" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="23" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
<property name="PropertiesView_NEXT_OBJECT" value="5" type="GuiHandlerData"/>
<property name="PropertiesView_PREVIOUS_OBJECT" value="17" type="GuiHandlerData"/>
<property name="QuickHelp_HELP" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_PROPERTIES" value="2" type="GuiHandlerData"/>
<property name="RDICommands_PROPERTIES" value="3" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="11" type="GuiHandlerData"/>
<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="241" type="GuiHandlerData"/>
<property name="RSBAddModuleDialog_HIDE_INCOMPATIBLE_MODULES" value="2" type="GuiHandlerData"/>
<property name="RSBAddModuleDialog_MODULE_LIST" value="6" type="GuiHandlerData"/>
<property name="RSBAddModuleDialog_MODULE_LIST" value="11" type="GuiHandlerData"/>
<property name="RSBAddModuleDialog_MODULE_TYPE" value="2" type="GuiHandlerData"/>
<property name="RSBApplyAutomationBar_RUN_CONNECTION_AUTOMATION" value="7" type="GuiHandlerData"/>
<property name="RSBApplyAutomationBar_RUN_CONNECTION_AUTOMATION" value="9" type="GuiHandlerData"/>
<property name="RSBBasePortTablePanel_PINS_TABLE" value="2" type="GuiHandlerData"/>
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="2" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="5" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="6" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="1" type="GuiHandlerData"/>
<property name="SignalTreePanel_SIGNAL_TREE_TABLE" value="37" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="18" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="20" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_SYNTHESIZE_DESIGN_GLOBALLY" value="3" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="145" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="83" type="GuiHandlerData"/>
......@@ -144,14 +144,15 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="8" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="9" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_ADD_IP" value="2" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_ADD_MODULE" value="18" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_ADD_MODULE" value="26" type="GuiHandlerData"/>
<property name="SystemBuilderMenu_CREATE_PORT" value="6" type="GuiHandlerData"/>
<property name="SystemBuilderView_ADD_IP" value="1" type="GuiHandlerData"/>
<property name="SystemBuilderView_PINNING" value="8" type="GuiHandlerData"/>
<property name="SystemBuilderView_ORIENTATION" value="2" type="GuiHandlerData"/>
<property name="SystemBuilderView_PINNING" value="10" type="GuiHandlerData"/>
<property name="SystemTreeView_SYSTEM_TREE" value="6" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="15" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="16" type="GuiHandlerData"/>
<property name="TclConsoleView_CLEAR_ALL_OUTPUT_IN_TCL_CONSOLE" value="1" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="TclObjectTreeTable_TREETABLE" value="10" type="GuiHandlerData"/>
......@@ -163,11 +164,6 @@ This means code written to parse this file will need to be revisited each subseq
<property name="WaveformView_NEXT_TRANSITION" value="865" type="GuiHandlerData"/>
<property name="WaveformView_PREVIOUS_TRANSITION" value="50" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="16" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="11" type="TclMode"/>
</item>
</section>
</application>
</document>
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/mref/riscv_core_with_axi_master_xilinxwrap/component.xml
浏览文件 @ 585e01f6
......@@ -234,7 +234,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c3e09eb8</spirit:value>
<spirit:value>a9f2775f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -247,7 +247,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c3e09eb8</spirit:value>
<spirit:value>a9f2775f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -637,7 +637,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2021-09-13T13:23:31Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2021-09-13T22:09:00Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hdl/risc_axi_v5_top_wrapper.v
浏览文件 @ 585e01f6
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date : Mon Sep 13 21:54:53 2021
//Date : Tue Sep 14 06:26:15 2021
//Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
//Command : generate_target risc_axi_v5_top_wrapper.bd
//Design : risc_axi_v5_top_wrapper
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hw_handoff/risc_axi_v5_top_bd.tcl
浏览文件 @ 585e01f6
......@@ -40,7 +40,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# The design that will be created by this Tcl script contains the following
# module references:
# led_key, riscv_core_with_axi_master_xilinxwrap
# led_key, riscv_core_with_axi_master
# Please add the sources of those modules before sourcing this Tcl script.
......@@ -189,7 +189,7 @@ proc create_root_design { parentCell } {
}
# Create instance: riscv_core_with_axi_0, and set properties
set block_name riscv_core_with_axi_master_xilinxwrap
set block_name riscv_core_with_axi_master
set block_cell_name riscv_core_with_axi_0
if { [catch {set riscv_core_with_axi_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/risc_axi_v5_top_led_key_0_0.xml
浏览文件 @ 585e01f6
......@@ -1058,36 +1058,36 @@
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/synth/risc_axi_v5_top_riscv_core_with_axi_0_0.v 已删除 100644 → 0
浏览文件 @ 9862c81c
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0
// IP Revision: 1
(* X_CORE_INFO = "riscv_core_with_axi_master_xilinxwrap,Vivado 2021.1" *)
(* CHECK_LICENSE_TYPE = "risc_axi_v5_top_riscv_core_with_axi_0_0,riscv_core_with_axi_master_xilinxwrap,{}" *)
(* CORE_GENERATION_INFO = "risc_axi_v5_top_riscv_core_with_axi_0_0,riscv_core_with_axi_master_xilinxwrap,{x_ipProduct=Vivado 2021.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=riscv_core_with_axi_master_xilinxwrap,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module risc_axi_v5_top_riscv_core_with_axi_0_0 (
m00_axi_aclk,
m00_axi_aresetn,
m00_axi_awaddr,
m00_axi_awprot,
m00_axi_awvalid,
m00_axi_awready,
m00_axi_wdata,
m00_axi_wstrb,
m00_axi_wvalid,
m00_axi_wready,
m00_axi_bresp,
m00_axi_bvalid,
m00_axi_bready,
m00_axi_araddr,
m00_axi_arprot,
m00_axi_arvalid,
m00_axi_arready,
m00_axi_rdata,
m00_axi_rresp,
m00_axi_rvalid,
m00_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_BUSIF m00_axi, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN risc_axi_v5_top_wClk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m00_axi_aclk CLK" *)
input wire m00_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m00_axi_aresetn RST" *)
input wire m00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWADDR" *)
output wire [31 : 0] m00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWPROT" *)
output wire [2 : 0] m00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWVALID" *)
output wire m00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWREADY" *)
input wire m00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WDATA" *)
output wire [31 : 0] m00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WSTRB" *)
output wire [3 : 0] m00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WVALID" *)
output wire m00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WREADY" *)
input wire m00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BRESP" *)
input wire [1 : 0] m00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BVALID" *)
input wire m00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BREADY" *)
output wire m00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARADDR" *)
output wire [31 : 0] m00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARPROT" *)
output wire [2 : 0] m00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARVALID" *)
output wire m00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARREADY" *)
input wire m00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RDATA" *)
input wire [31 : 0] m00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RRESP" *)
input wire [1 : 0] m00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RVALID" *)
input wire m00_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN risc_axi_v5_top_wClk, NUM_READ_THREADS 1, NUM_WRITE_THREADS\
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *)
output wire m00_axi_rready;
riscv_core_with_axi_master_xilinxwrap inst (
.m00_axi_aclk(m00_axi_aclk),
.m00_axi_aresetn(m00_axi_aresetn),
.m00_axi_awaddr(m00_axi_awaddr),
.m00_axi_awprot(m00_axi_awprot),
.m00_axi_awvalid(m00_axi_awvalid),
.m00_axi_awready(m00_axi_awready),
.m00_axi_wdata(m00_axi_wdata),
.m00_axi_wstrb(m00_axi_wstrb),
.m00_axi_wvalid(m00_axi_wvalid),
.m00_axi_wready(m00_axi_wready),
.m00_axi_bresp(m00_axi_bresp),
.m00_axi_bvalid(m00_axi_bvalid),
.m00_axi_bready(m00_axi_bready),
.m00_axi_araddr(m00_axi_araddr),
.m00_axi_arprot(m00_axi_arprot),
.m00_axi_arvalid(m00_axi_arvalid),
.m00_axi_arready(m00_axi_arready),
.m00_axi_rdata(m00_axi_rdata),
.m00_axi_rresp(m00_axi_rresp),
.m00_axi_rvalid(m00_axi_rvalid),
.m00_axi_rready(m00_axi_rready)
);
endmodule
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/risc_axi_v5_top_xbar_0.xml
浏览文件 @ 585e01f6
......@@ -27362,7 +27362,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 13 13:48:32 UTC 2021</spirit:value>
<spirit:value>Mon Sep 13 22:26:15 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
......@@ -27417,7 +27417,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 13 13:48:32 UTC 2021</spirit:value>
<spirit:value>Mon Sep 13 22:26:15 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
......@@ -27445,7 +27445,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 13 13:48:32 UTC 2021</spirit:value>
<spirit:value>Mon Sep 13 22:26:15 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
......@@ -27465,7 +27465,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 13 13:48:33 UTC 2021</spirit:value>
<spirit:value>Mon Sep 13 22:26:15 UTC 2021</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/risc_axi_v5_top.bxml
浏览文件 @ 585e01f6
......@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="39">
<CompositeFile CompositeFileTopName="risc_axi_v5_top" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1631541294"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1631541294"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1631541294"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1631541294"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1631571976"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1631571976"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1631571976"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1631571976"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\risc_axi_v5_top.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/sim/risc_axi_v5_top.v
浏览文件 @ 585e01f6
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date : Mon Sep 13 21:54:53 2021
//Date : Tue Sep 14 06:26:15 2021
//Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
//Command : generate_target risc_axi_v5_top.bd
//Design : risc_axi_v5_top
......@@ -287,7 +287,7 @@ module m01_couplers_imp_15DQFTV
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=7,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *)
(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=8,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *)
module risc_axi_v5_top
(key,
led,
......@@ -417,7 +417,7 @@ module risc_axi_v5_top
.s00_axi_wready(riscv_core_with_axi_0_axi_periph_M01_AXI_WREADY),
.s00_axi_wstrb(riscv_core_with_axi_0_axi_periph_M01_AXI_WSTRB),
.s00_axi_wvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_WVALID));
risc_axi_v5_top_riscv_core_with_axi_0_0 riscv_core_with_axi_0
risc_axi_v5_top_riscv_core_with_axi_0_5 riscv_core_with_axi_0
(.m00_axi_aclk(wClk_1),
.m00_axi_araddr(riscv_core_with_axi_0_m00_axi_ARADDR),
.m00_axi_aresetn(rst_wClk_50M_peripheral_aresetn),
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v
浏览文件 @ 585e01f6
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date : Mon Sep 13 21:54:53 2021
//Date : Tue Sep 14 06:26:15 2021
//Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
//Command : generate_target risc_axi_v5_top.bd
//Design : risc_axi_v5_top
......@@ -287,7 +287,7 @@ module m01_couplers_imp_15DQFTV
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=7,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *)
(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=8,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *)
module risc_axi_v5_top
(key,
led,
......@@ -417,7 +417,7 @@ module risc_axi_v5_top
.s00_axi_wready(riscv_core_with_axi_0_axi_periph_M01_AXI_WREADY),
.s00_axi_wstrb(riscv_core_with_axi_0_axi_periph_M01_AXI_WSTRB),
.s00_axi_wvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_WVALID));
risc_axi_v5_top_riscv_core_with_axi_0_0 riscv_core_with_axi_0
risc_axi_v5_top_riscv_core_with_axi_0_5 riscv_core_with_axi_0
(.m00_axi_aclk(wClk_1),
.m00_axi_araddr(riscv_core_with_axi_0_m00_axi_ARADDR),
.m00_axi_aresetn(rst_wClk_50M_peripheral_aresetn),
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v 已删除 100644 → 0
浏览文件 @ 9862c81c
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module risc_axi_v5_top_riscv_core_with_axi_0_0 (
m00_axi_aclk,
m00_axi_aresetn,
m00_axi_awaddr,
m00_axi_awprot,
m00_axi_awvalid,
m00_axi_awready,
m00_axi_wdata,
m00_axi_wstrb,
m00_axi_wvalid,
m00_axi_wready,
m00_axi_bresp,
m00_axi_bvalid,
m00_axi_bready,
m00_axi_araddr,
m00_axi_arprot,
m00_axi_arvalid,
m00_axi_arready,
m00_axi_rdata,
m00_axi_rresp,
m00_axi_rvalid,
m00_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_BUSIF m00_axi, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN risc_axi_v5_top_wClk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m00_axi_aclk CLK" *)
input wire m00_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m00_axi_aresetn RST" *)
input wire m00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWADDR" *)
output wire [31 : 0] m00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWPROT" *)
output wire [2 : 0] m00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWVALID" *)
output wire m00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWREADY" *)
input wire m00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WDATA" *)
output wire [31 : 0] m00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WSTRB" *)
output wire [3 : 0] m00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WVALID" *)
output wire m00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WREADY" *)
input wire m00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BRESP" *)
input wire [1 : 0] m00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BVALID" *)
input wire m00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BREADY" *)
output wire m00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARADDR" *)
output wire [31 : 0] m00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARPROT" *)
output wire [2 : 0] m00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARVALID" *)
output wire m00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARREADY" *)
input wire m00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RDATA" *)
input wire [31 : 0] m00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RRESP" *)
input wire [1 : 0] m00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RVALID" *)
input wire m00_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN risc_axi_v5_top_wClk, NUM_READ_THREADS 1, NUM_WRITE_THREADS\
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *)
output wire m00_axi_rready;
riscv_core_with_axi_master_xilinxwrap inst (
.m00_axi_aclk(m00_axi_aclk),
.m00_axi_aresetn(m00_axi_aresetn),
.m00_axi_awaddr(m00_axi_awaddr),
.m00_axi_awprot(m00_axi_awprot),
.m00_axi_awvalid(m00_axi_awvalid),
.m00_axi_awready(m00_axi_awready),
.m00_axi_wdata(m00_axi_wdata),
.m00_axi_wstrb(m00_axi_wstrb),
.m00_axi_wvalid(m00_axi_wvalid),
.m00_axi_wready(m00_axi_wready),
.m00_axi_bresp(m00_axi_bresp),
.m00_axi_bvalid(m00_axi_bvalid),
.m00_axi_bready(m00_axi_bready),
.m00_axi_araddr(m00_axi_araddr),
.m00_axi_arprot(m00_axi_arprot),
.m00_axi_arvalid(m00_axi_arvalid),
.m00_axi_arready(m00_axi_arready),
.m00_axi_rdata(m00_axi_rdata),
.m00_axi_rresp(m00_axi_rresp),
.m00_axi_rvalid(m00_axi_rvalid),
.m00_axi_rready(m00_axi_rready)
);
endmodule
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v → examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v
浏览文件 @ 585e01f6
......@@ -47,14 +47,14 @@
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0
// IP VLNV: xilinx.com:module_ref:riscv_core_with_axi_master:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module risc_axi_v5_top_riscv_core_with_axi_0_0 (
module risc_axi_v5_top_riscv_core_with_axi_0_5 (
m00_axi_aclk,
m00_axi_aresetn,
m00_axi_awaddr,
......@@ -125,7 +125,7 @@ input wire m00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *)
output wire m00_axi_rready;
riscv_core_with_axi_master_xilinxwrap inst (
riscv_core_with_axi_master inst (
.m00_axi_aclk(m00_axi_aclk),
.m00_axi_aresetn(m00_axi_aresetn),
.m00_axi_awaddr(m00_axi_awaddr),
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/sim/risc_axi_v5_top_xbar_0.v
浏览文件 @ 585e01f6
......@@ -193,8 +193,8 @@ output wire [1 : 0] m_axi_rready;
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H00000000f000000000000000f0000100),
.C_M_AXI_ADDR_WIDTH(64'H0000000700000007),
.C_M_AXI_BASE_ADDR(128'H0000000044a000000000000040600000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/bd/risc_axi_v5_top/sim/risc_axi_v5_top.v
浏览文件 @ 585e01f6
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date : Mon Sep 13 21:54:53 2021
//Date : Tue Sep 14 06:13:57 2021
//Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
//Command : generate_target risc_axi_v5_top.bd
//Design : risc_axi_v5_top
......@@ -287,7 +287,7 @@ module m01_couplers_imp_15DQFTV
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=7,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *)
(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=8,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *)
module risc_axi_v5_top
(key,
led,
......@@ -417,7 +417,7 @@ module risc_axi_v5_top
.s00_axi_wready(riscv_core_with_axi_0_axi_periph_M01_AXI_WREADY),
.s00_axi_wstrb(riscv_core_with_axi_0_axi_periph_M01_AXI_WSTRB),
.s00_axi_wvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_WVALID));
risc_axi_v5_top_riscv_core_with_axi_0_0 riscv_core_with_axi_0
risc_axi_v5_top_riscv_core_with_axi_0_5 riscv_core_with_axi_0
(.m00_axi_aclk(wClk_1),
.m00_axi_araddr(riscv_core_with_axi_0_m00_axi_ARADDR),
.m00_axi_aresetn(rst_wClk_50M_peripheral_aresetn),
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/mem_init_files/risc_axi_v5_top.bda
浏览文件 @ 585e01f6
......@@ -21,15 +21,20 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="BA">0xF0000000</data>
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n1">
<data key="BA">0x44A00000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0xF000007F</data>
<data key="HA">0x44A0FFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">m00_axi</data>
<data key="MX">/riscv_core_with_axi_0</data>
<data key="MI">m00_axi</data>
<data key="MS">SEG_led_key_0_reg0</data>
<data key="MV">xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0</data>
<data key="MV">xilinx.com:module_ref:riscv_core_with_axi_master:1.0</data>
<data key="TM">both</data>
<data key="SX">/led_key_0</data>
<data key="SI">s00_axi</data>
......@@ -38,30 +43,20 @@
<data key="TU">register</data>
<data key="VT">AC</data>
</node>
<node id="n1">
<data key="VM">risc_axi_v5_top</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="VH">2</data>
<data key="VM">risc_axi_v5_top</data>
<data key="VT">VR</data>
<data key="VT">BC</data>
</node>
<node id="n3">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n4">
<data key="BA">0xF0000100</data>
<data key="BA">0x40600000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0xF000017F</data>
<data key="HA">0x4060FFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">m00_axi</data>
<data key="MX">/riscv_core_with_axi_0</data>
<data key="MI">m00_axi</data>
<data key="MS">SEG_axi_uartlite_0_Reg</data>
<data key="MV">xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0</data>
<data key="MV">xilinx.com:module_ref:riscv_core_with_axi_master:1.0</data>
<data key="TM">both</data>
<data key="SX">/axi_uartlite_0</data>
<data key="SI">S_AXI</data>
......@@ -70,14 +65,19 @@
<data key="TU">register</data>
<data key="VT">AC</data>
</node>
<edge id="e0" source="n1" target="n2">
<node id="n4">
<data key="VH">2</data>
<data key="VM">risc_axi_v5_top</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n2" target="n4">
</edge>
<edge id="e1" source="n2" target="n3">
<edge id="e1" source="n4" target="n0">
</edge>
<edge id="e2" source="n0" target="n3">
<edge id="e2" source="n3" target="n0">
<data key="EH">2</data>
</edge>
<edge id="e3" source="n4" target="n3">
<edge id="e3" source="n1" target="n0">
<data key="EH">2</data>
</edge>
</graph>
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/activehdl/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/activehdl/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/ies/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/ies/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/modelsim/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/modelsim/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/questa/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/questa/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/riviera/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/riviera/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/vcs/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/vcs/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/xcelium/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/xcelium/file_info.txt
浏览文件 @ 585e01f6
......@@ -14,11 +14,11 @@ lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_13,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_28,../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/xsim/README.txt
浏览文件 @ 585e01f6
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Mon Sep 13 21:54:56 +0800 2021
# Generated by export_simulation on Tue Sep 14 06:14:00 +0800 2021
#
################################################################################
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/xsim/file_info.txt
浏览文件 @ 585e01f6
risc_axi_v5_top_xbar_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/sim/risc_axi_v5_top_xbar_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_rst_wClk_50M_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_led_key_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_0.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_axi_uartlite_0_0.vhd,vhdl,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/sim/risc_axi_v5_top_axi_uartlite_0_0.vhd,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top_riscv_core_with_axi_0_5.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
risc_axi_v5_top.v,verilog,xil_defaultlib,../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v,incdir="$ref_dir/../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"incdir="../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/sim_scripts/risc_axi_v5_top/xsim/vlog.prj
浏览文件 @ 585e01f6
verilog xil_defaultlib --include "../../../../riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ec67/hdl" \
"../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/sim/risc_axi_v5_top_xbar_0.v" \
"../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/sim/risc_axi_v5_top_led_key_0_0.v" \
"../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/sim/risc_axi_v5_top_riscv_core_with_axi_0_0.v" \
"../../../bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/sim/risc_axi_v5_top_riscv_core_with_axi_0_5.v" \
"../../../bd/risc_axi_v5_top/sim/risc_axi_v5_top.v" \
verilog xil_defaultlib "glbl.v"
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/gen_run.xml
浏览文件 @ 585e01f6
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7z020clg400-2" LaunchTime="1631541563">
<GenRun Id="impl_1" LaunchPart="xc7z020clg400-2" LaunchTime="1631571978">
<File Type="ROUTE-PWR" Name="risc_axi_v5_top_wrapper_power_routed.rpt"/>
<File Type="PA-TCL" Name="risc_axi_v5_top_wrapper.tcl"/>
<File Type="BITSTR-MMI" Name="risc_axi_v5_top_wrapper.mmi"/>
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper.tcl
浏览文件 @ 585e01f6
......@@ -150,7 +150,6 @@ OPTRACE "add files" START { }
set_param project.isImplRun true
read_ip -quiet D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/ip/ram4KB/ram4KB.xci
add_files D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/bd/risc_axi_v5_top/risc_axi_v5_top.bd
read_ip -quiet D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xci
set_param project.isImplRun false
OPTRACE "read constraints: implementation" START { }
read_xdc D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_bus_skew_routed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:30 2021
| Date : Tue Sep 14 06:28:25 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file risc_axi_v5_top_wrapper_bus_skew_routed.rpt -pb risc_axi_v5_top_wrapper_bus_skew_routed.pb -rpx risc_axi_v5_top_wrapper_bus_skew_routed.rpx
| Design : risc_axi_v5_top_wrapper
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_clock_utilization_routed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:30 2021
| Date : Tue Sep 14 06:28:25 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_clock_utilization -file risc_axi_v5_top_wrapper_clock_utilization_routed.rpt
| Design : risc_axi_v5_top_wrapper
......@@ -45,7 +45,7 @@ Table of Contents
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 922 | 0 | | | wClk_IBUF_BUFG_inst/O | wClk_IBUF_BUFG |
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 892 | 0 | | | wClk_IBUF_BUFG_inst/O | wClk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
......@@ -72,9 +72,9 @@ Table of Contents
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 778 | 3200 | 303 | 850 | 1 | 60 | 1 | 30 | 0 | 40 |
| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 650 | 3200 | 205 | 850 | 0 | 60 | 1 | 30 | 0 | 40 |
| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 119 | 2600 | 60 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 217 | 2600 | 64 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
| X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
......@@ -100,7 +100,7 @@ All Modules
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+
| g0 | BUFG/O | n/a | | | | 919 | 0 | 0 | 0 | wClk_IBUF_BUFG |
| g0 | BUFG/O | n/a | | | | 889 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
......@@ -112,8 +112,8 @@ All Modules
| | X0 | X1 | HORIZONTAL PROG DELAY |
+----+----+------+-----------------------+
| Y2 | 0 | 0 | 0 |
| Y1 | 0 | 129 | 0 |
| Y0 | 0 | 790 | 0 |
| Y1 | 0 | 235 | 0 |
| Y0 | 0 | 654 | 0 |
+----+----+------+-----------------------+
......@@ -123,7 +123,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| g0 | n/a | BUFG/O | None | 790 | 0 | 778 | 9 | 2 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
| g0 | n/a | BUFG/O | None | 654 | 0 | 650 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
......@@ -136,7 +136,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| g0 | n/a | BUFG/O | None | 129 | 0 | 119 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
| g0 | n/a | BUFG/O | None | 235 | 0 | 217 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_drc_opted.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:01 2021
| Date : Tue Sep 14 06:27:56 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_drc -file risc_axi_v5_top_wrapper_drc_opted.rpt -pb risc_axi_v5_top_wrapper_drc_opted.pb -rpx risc_axi_v5_top_wrapper_drc_opted.rpx
| Design : risc_axi_v5_top_wrapper
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_drc_routed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:28 2021
| Date : Tue Sep 14 06:28:23 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_drc -file risc_axi_v5_top_wrapper_drc_routed.rpt -pb risc_axi_v5_top_wrapper_drc_routed.pb -rpx risc_axi_v5_top_wrapper_drc_routed.rpx
| Design : risc_axi_v5_top_wrapper
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_io_placed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:06 2021
| Date : Tue Sep 14 06:28:01 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_io -file risc_axi_v5_top_wrapper_io_placed.rpt
| Design : risc_axi_v5_top_wrapper
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_power_routed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:30 2021
| Date : Tue Sep 14 06:28:25 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_power -file risc_axi_v5_top_wrapper_power_routed.rpt -pb risc_axi_v5_top_wrapper_power_summary_routed.pb -rpx risc_axi_v5_top_wrapper_power_routed.rpx
| Design : risc_axi_v5_top_wrapper
......@@ -30,10 +30,10 @@ Table of Contents
----------
+--------------------------+----------------------------------+
| Total On-Chip Power (W) | 23.945 (Junction temp exceeded!) |
| Total On-Chip Power (W) | 28.470 (Junction temp exceeded!) |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 22.900 |
| Dynamic (W) | 27.425 |
| Device Static (W) | 1.045 |
| Effective TJA (C/W) | 11.5 |
| Max Ambient (C) | 0.0 |
......@@ -52,19 +52,18 @@ Table of Contents
+-------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+-------------------------+-----------+----------+-----------+-----------------+
| Slice Logic | 8.574 | 4165 | --- | --- |
| LUT as Logic | 7.899 | 2654 | 53200 | 4.99 |
| CARRY4 | 0.467 | 174 | 13300 | 1.31 |
| Register | 0.202 | 897 | 106400 | 0.84 |
| Slice Logic | 10.581 | 4057 | --- | --- |
| LUT as Logic | 9.874 | 2594 | 53200 | 4.88 |
| CARRY4 | 0.534 | 174 | 13300 | 1.31 |
| Register | 0.167 | 867 | 106400 | 0.81 |
| BUFG | 0.006 | 1 | 32 | 3.13 |
| F7/F8 Muxes | <0.001 | 1 | 53200 | <0.01 |
| LUT as Shift Register | <0.001 | 11 | 17400 | 0.06 |
| Others | 0.000 | 53 | --- | --- |
| Signals | 8.172 | 3478 | --- | --- |
| Block RAM | 0.321 | 2 | 140 | 1.43 |
| Signals | 10.674 | 3380 | --- | --- |
| Block RAM | 0.339 | 2 | 140 | 1.43 |
| I/O | 5.832 | 8 | 125 | 6.40 |
| Static Power | 1.045 | | | |
| Total | 23.945 | | | |
| Total | 28.470 | | | |
+-------------------------+-----------+----------+-----------+-----------------+
......@@ -74,7 +73,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 17.365 | 17.065 | 0.300 | NA | Unspecified | NA |
| Vccint | 1.000 | 21.891 | 21.590 | 0.300 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.313 | 0.213 | 0.100 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 1.648 | 1.647 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
......@@ -148,18 +147,18 @@ Table of Contents
+--------------------------------------+-----------+
| Name | Power (W) |
+--------------------------------------+-----------+
| risc_axi_v5_top_wrapper | 22.900 |
| risc_axi_v5_top_i | 16.986 |
| axi_uartlite_0 | 0.223 |
| U0 | 0.223 |
| led_key_0 | 0.082 |
| inst | 0.082 |
| riscv_core_with_axi_0 | 16.187 |
| inst | 16.187 |
| riscv_core_with_axi_0_axi_periph | 0.456 |
| xbar | 0.456 |
| rst_wClk_50M | 0.038 |
| U0 | 0.038 |
| risc_axi_v5_top_wrapper | 27.425 |
| risc_axi_v5_top_i | 21.513 |
| axi_uartlite_0 | 0.220 |
| U0 | 0.220 |
| led_key_0 | 0.080 |
| inst | 0.080 |
| riscv_core_with_axi_0 | 20.848 |
| inst | 20.848 |
| riscv_core_with_axi_0_axi_periph | 0.321 |
| xbar | 0.321 |
| rst_wClk_50M | 0.044 |
| U0 | 0.044 |
+--------------------------------------+-----------+
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_route_status.rpt
浏览文件 @ 585e01f6
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 4740 :
# of nets not needing routing.......... : 1260 :
# of internally routed nets........ : 1260 :
# of routable nets..................... : 3480 :
# of fully routed nets............. : 3480 :
# of logical nets.......................... : 4624 :
# of nets not needing routing.......... : 1242 :
# of internally routed nets........ : 1242 :
# of routable nets..................... : 3382 :
# of fully routed nets............. : 3382 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_timing_summary_routed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:30 2021
| Date : Tue Sep 14 06:28:25 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file risc_axi_v5_top_wrapper_timing_summary_routed.rpt -pb risc_axi_v5_top_wrapper_timing_summary_routed.pb -rpx risc_axi_v5_top_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design : risc_axi_v5_top_wrapper
......@@ -41,7 +41,7 @@ Timing Summary Report
Rule Severity Description Violations
--------- ---------------- --------------------------- ----------
TIMING-17 Critical Warning Non-clocked sequential cell 921
TIMING-17 Critical Warning Non-clocked sequential cell 891
Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
......@@ -51,10 +51,10 @@ check_timing report
Table of Contents
-----------------
1. checking no_clock (921)
1. checking no_clock (891)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (2229)
4. checking unconstrained_internal_endpoints (2171)
5. checking no_input_delay (2)
6. checking no_output_delay (5)
7. checking multiple_clock (0)
......@@ -64,9 +64,9 @@ Table of Contents
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (921)
1. checking no_clock (891)
--------------------------
There are 921 register/latch pins with no clock driven by root clock pin: wClk (HIGH)
There are 891 register/latch pins with no clock driven by root clock pin: wClk (HIGH)
2. checking constant_clock (0)
......@@ -79,9 +79,9 @@ Table of Contents
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (2229)
4. checking unconstrained_internal_endpoints (2171)
---------------------------------------------------
There are 2229 pins that are not constrained for maximum delay. (HIGH)
There are 2171 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper_utilization_placed.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:01:06 2021
| Date : Tue Sep 14 06:28:01 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_utilization -file risc_axi_v5_top_wrapper_utilization_placed.rpt -pb risc_axi_v5_top_wrapper_utilization_placed.pb
| Design : risc_axi_v5_top_wrapper
......@@ -31,15 +31,15 @@ Table of Contents
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs | 2665 | 0 | 0 | 53200 | 5.01 |
| LUT as Logic | 2654 | 0 | 0 | 53200 | 4.99 |
| Slice LUTs | 2605 | 0 | 0 | 53200 | 4.90 |
| LUT as Logic | 2594 | 0 | 0 | 53200 | 4.88 |
| LUT as Memory | 11 | 0 | 0 | 17400 | 0.06 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 11 | 0 | | | |
| Slice Registers | 897 | 0 | 0 | 106400 | 0.84 |
| Register as Flip Flop | 897 | 0 | 0 | 106400 | 0.84 |
| Slice Registers | 867 | 0 | 0 | 106400 | 0.81 |
| Register as Flip Flop | 867 | 0 | 0 | 106400 | 0.81 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 1 | 0 | 0 | 26600 | <0.01 |
| F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
......@@ -59,7 +59,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 53 | Yes | Set | - |
| 844 | Yes | Reset | - |
| 814 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,25 +69,25 @@ Table of Contents
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
| Slice | 803 | 0 | 0 | 13300 | 6.04 |
| SLICEL | 553 | 0 | | | |
| SLICEM | 250 | 0 | | | |
| LUT as Logic | 2654 | 0 | 0 | 53200 | 4.99 |
| Slice | 756 | 0 | 0 | 13300 | 5.68 |
| SLICEL | 518 | 0 | | | |
| SLICEM | 238 | 0 | | | |
| LUT as Logic | 2594 | 0 | 0 | 53200 | 4.88 |
| using O5 output only | 0 | | | | |
| using O6 output only | 2288 | | | | |
| using O5 and O6 | 366 | | | | |
| using O6 output only | 2245 | | | | |
| using O5 and O6 | 349 | | | | |
| LUT as Memory | 11 | 0 | 0 | 17400 | 0.06 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 11 | 0 | | | |
| using O5 output only | 2 | | | | |
| using O6 output only | 1 | | | | |
| using O5 and O6 | 8 | | | | |
| Slice Registers | 897 | 0 | 0 | 106400 | 0.84 |
| Register driven from within the Slice | 659 | | | | |
| Register driven from outside the Slice | 238 | | | | |
| LUT in front of the register is unused | 96 | | | | |
| LUT in front of the register is used | 142 | | | | |
| Unique Control Sets | 45 | | 0 | 13300 | 0.34 |
| Slice Registers | 867 | 0 | 0 | 106400 | 0.81 |
| Register driven from within the Slice | 645 | | | | |
| Register driven from outside the Slice | 222 | | | | |
| LUT in front of the register is unused | 61 | | | | |
| LUT in front of the register is used | 161 | | | | |
| Unique Control Sets | 44 | | 0 | 13300 | 0.33 |
+--------------------------------------------+------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
......@@ -181,12 +181,12 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 1420 | LUT |
| FDRE | 844 | Flop & Latch |
| LUT5 | 563 | LUT |
| LUT3 | 380 | LUT |
| LUT4 | 304 | LUT |
| LUT2 | 212 | LUT |
| LUT6 | 1480 | LUT |
| FDRE | 814 | Flop & Latch |
| LUT5 | 512 | LUT |
| LUT3 | 319 | LUT |
| LUT2 | 246 | LUT |
| LUT4 | 245 | LUT |
| CARRY4 | 174 | CarryLogic |
| LUT1 | 141 | LUT |
| FDSE | 53 | Flop & Latch |
......@@ -195,7 +195,6 @@ Table of Contents
| IBUF | 3 | IO |
| RAMB18E1 | 2 | Block Memory |
| RAMB36E1 | 1 | Block Memory |
| MUXF7 | 1 | MuxFx |
| BUFG | 1 | Clock |
+----------+------+---------------------+
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/vivado.jou
浏览文件 @ 585e01f6
......@@ -2,8 +2,8 @@
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Mon Sep 13 22:00:36 2021
# Process ID: 55704
# Start of session at: Tue Sep 14 06:27:31 2021
# Process ID: 34692
# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1
# Command line: vivado.exe -log risc_axi_v5_top_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source risc_axi_v5_top_wrapper.tcl -notrace
# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/impl_1/risc_axi_v5_top_wrapper.vdi
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc
浏览文件 @ 585e01f6
......@@ -21,17 +21,14 @@ set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==risc_axi_v5
# IP: bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/risc_axi_v5_top_led_key_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_led_key_0_0 || ORIG_REF_NAME==risc_axi_v5_top_led_key_0_0} -quiet] -quiet
# IP: bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_0/risc_axi_v5_top_riscv_core_with_axi_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_riscv_core_with_axi_0_0 || ORIG_REF_NAME==risc_axi_v5_top_riscv_core_with_axi_0_0} -quiet] -quiet
# IP: ip/ram4KB/ram4KB.xci
#dup# set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==ram4KB || ORIG_REF_NAME==ram4KB} -quiet] -quiet
# IP: bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_axi_uartlite_0_0 || ORIG_REF_NAME==risc_axi_v5_top_axi_uartlite_0_0} -quiet] -quiet
# IP: ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==hdl4se_uart_fifo || ORIG_REF_NAME==hdl4se_uart_fifo} -quiet] -quiet
# IP: bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/risc_axi_v5_top_riscv_core_with_axi_0_5.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_riscv_core_with_axi_0_5 || ORIG_REF_NAME==risc_axi_v5_top_riscv_core_with_axi_0_5} -quiet] -quiet
# IP: ip/ram4KB/ram4KB.xci
#dup# set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==ram4KB || ORIG_REF_NAME==ram4KB} -quiet] -quiet
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/ram4KB_ooc.xdc
......@@ -41,8 +38,6 @@ set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filte
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0.xdc
#dup# set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_rst_wClk_50M_0 || ORIG_REF_NAME==risc_axi_v5_top_rst_wClk_50M_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/ram4KB_ooc.xdc
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_board.xdc
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_axi_uartlite_0_0 || ORIG_REF_NAME==risc_axi_v5_top_axi_uartlite_0_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
......@@ -51,7 +46,6 @@ set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filte
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0.xdc
#dup# set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==risc_axi_v5_top_axi_uartlite_0_0 || ORIG_REF_NAME==risc_axi_v5_top_axi_uartlite_0_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/risc_axi_v5_top_ooc.xdc
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/ram4KB_ooc.xdc
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/hdl4se_uart_fifo/hdl4se_uart_fifo.xdc
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==hdl4se_uart_fifo || ORIG_REF_NAME==hdl4se_uart_fifo} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
# XDC: d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/risc_axi_v5_top_ooc.xdc
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/gen_run.xml
浏览文件 @ 585e01f6
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7z020clg400-2" LaunchTime="1631541563">
<GenRun Id="synth_1" LaunchPart="xc7z020clg400-2" LaunchTime="1631571978">
<File Type="PA-TCL" Name="risc_axi_v5_top_wrapper.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="risc_axi_v5_top_wrapper_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="risc_axi_v5_top_wrapper_reports.tcl"/>
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/risc_axi_v5_top_wrapper_utilization_synth.rpt
浏览文件 @ 585e01f6
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Mon Sep 13 22:00:28 2021
| Date : Tue Sep 14 06:27:24 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_utilization -file risc_axi_v5_top_wrapper_utilization_synth.rpt -pb risc_axi_v5_top_wrapper_utilization_synth.pb
| Design : risc_axi_v5_top_wrapper
......@@ -30,15 +30,15 @@ Table of Contents
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 2678 | 0 | 0 | 53200 | 5.03 |
| LUT as Logic | 2659 | 0 | 0 | 53200 | 5.00 |
| Slice LUTs* | 2616 | 0 | 0 | 53200 | 4.92 |
| LUT as Logic | 2597 | 0 | 0 | 53200 | 4.88 |
| LUT as Memory | 19 | 0 | 0 | 17400 | 0.11 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 19 | 0 | | | |
| Slice Registers | 897 | 0 | 0 | 106400 | 0.84 |
| Register as Flip Flop | 897 | 0 | 0 | 106400 | 0.84 |
| Slice Registers | 867 | 0 | 0 | 106400 | 0.81 |
| Register as Flip Flop | 867 | 0 | 0 | 106400 | 0.81 |
| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
| F7 Muxes | 1 | 0 | 0 | 26600 | <0.01 |
| F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
......@@ -59,7 +59,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 53 | Yes | Set | - |
| 844 | Yes | Reset | - |
| 814 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -150,12 +150,12 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 1422 | LUT |
| FDRE | 844 | Flop & Latch |
| LUT5 | 563 | LUT |
| LUT3 | 378 | LUT |
| LUT4 | 304 | LUT |
| LUT2 | 212 | LUT |
| LUT6 | 1482 | LUT |
| FDRE | 814 | Flop & Latch |
| LUT5 | 512 | LUT |
| LUT3 | 317 | LUT |
| LUT2 | 246 | LUT |
| LUT4 | 245 | LUT |
| CARRY4 | 174 | CarryLogic |
| LUT1 | 145 | LUT |
| FDSE | 53 | Flop & Latch |
......@@ -164,7 +164,6 @@ Table of Contents
| IBUF | 3 | IO |
| RAMB18E1 | 2 | Block Memory |
| RAMB36E1 | 1 | Block Memory |
| MUXF7 | 1 | MuxFx |
| BUFG | 1 | Clock |
+----------+------+---------------------+
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/vivado.jou
浏览文件 @ 585e01f6
......@@ -2,8 +2,8 @@
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Mon Sep 13 21:59:25 2021
# Process ID: 44720
# Start of session at: Tue Sep 14 06:26:20 2021
# Process ID: 46244
# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1
# Command line: vivado.exe -log risc_axi_v5_top_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source risc_axi_v5_top_wrapper.tcl
# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/risc_axi_v5_top_wrapper.vds
......
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.xpr
浏览文件 @ 585e01f6
......@@ -71,13 +71,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="21"/>
<Option Name="WTModelSimExportSim" Val="21"/>
<Option Name="WTQuestaExportSim" Val="21"/>
<Option Name="WTIesExportSim" Val="21"/>
<Option Name="WTVcsExportSim" Val="21"/>
<Option Name="WTRivieraExportSim" Val="21"/>
<Option Name="WTActivehdlExportSim" Val="20"/>
<Option Name="WTXSimExportSim" Val="22"/>
<Option Name="WTModelSimExportSim" Val="22"/>
<Option Name="WTQuestaExportSim" Val="22"/>
<Option Name="WTIesExportSim" Val="22"/>
<Option Name="WTVcsExportSim" Val="22"/>
<Option Name="WTRivieraExportSim" Val="22"/>
<Option Name="WTActivehdlExportSim" Val="21"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
......
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