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202109131717

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examples/hdl4se_riscv/de1/de1_riscv_axi.v
浏览文件 @ 6e8b1bac
...@@ -175,8 +175,8 @@ module de1_riscv_axi( ...@@ -175,8 +175,8 @@ module de1_riscv_axi(
.m00_axi_rready(m00_axi_rready) .m00_axi_rready(m00_axi_rready)
); );
wire is_led_key_w = ((m00_axi_awaddr & 32'hffff_fff0) == 32'hf000_0000); wire is_led_key_w = ((m00_axi_awaddr & 32'hffff_ff00) == 32'hf000_0000);
wire is_led_key_r = ((m00_axi_araddr & 32'hffff_fff0) == 32'hf000_0000); wire is_led_key_r = ((m00_axi_araddr & 32'hffff_ff00) == 32'hf000_0000);
wire [3 : 0] s00_axi_awaddr = m00_axi_awaddr[3:0]; wire [3 : 0] s00_axi_awaddr = m00_axi_awaddr[3:0];
wire [2 : 0] s00_axi_awprot = m00_axi_awprot; wire [2 : 0] s00_axi_awprot = m00_axi_awprot;
wire s00_axi_awvalid = m00_axi_awvalid && is_led_key_w; wire s00_axi_awvalid = m00_axi_awvalid && is_led_key_w;
...@@ -225,27 +225,27 @@ module de1_riscv_axi( ...@@ -225,27 +225,27 @@ module de1_riscv_axi(
.led(LEDR[5:2]) .led(LEDR[5:2])
); );
wire is_uart_w = ((m00_axi_awaddr & 32'hffff_fff0) == 32'hf000_0100); wire is_uart_w = ((m00_axi_awaddr & 32'hffff_ff00) == 32'hf000_0100);
wire is_uart_r = ((m00_axi_araddr & 32'hffff_fff0) == 32'hf000_0100); wire is_uart_r = ((m00_axi_araddr & 32'hffff_ff00) == 32'hf000_0100);
wire [3 : 0] s01_axi_awaddr = m00_axi_awaddr[3:0]; wire [3 : 0] s01_axi_awaddr = m00_axi_awaddr[3:0];
wire [2 : 0] s01_axi_awprot = m00_axi_awprot; wire [2 : 0] s01_axi_awprot = m00_axi_awprot;
wire s01_axi_awvalid = m00_axi_awvalid && is_led_key_w; wire s01_axi_awvalid = m00_axi_awvalid && is_uart_w;
wire s01_axi_awready; wire s01_axi_awready;
wire [31 : 0] s01_axi_wdata = m00_axi_wdata; wire [31 : 0] s01_axi_wdata = m00_axi_wdata;
wire [3 : 0] s01_axi_wstrb = m00_axi_wstrb; wire [3 : 0] s01_axi_wstrb = m00_axi_wstrb;
wire s01_axi_wvalid = m00_axi_wvalid && is_led_key_w; wire s01_axi_wvalid = m00_axi_wvalid && is_uart_w;
wire s01_axi_wready; wire s01_axi_wready;
wire [1 : 0] s01_axi_bresp; wire [1 : 0] s01_axi_bresp;
wire s01_axi_bvalid; wire s01_axi_bvalid;
wire s01_axi_bready = m00_axi_bready;//?? && is_led_key_w; wire s01_axi_bready = m00_axi_bready;//?? && is_uart_w;
wire [3 : 0] s01_axi_araddr = m00_axi_araddr; wire [3 : 0] s01_axi_araddr = m00_axi_araddr;
wire [2 : 0] s01_axi_arprot = m00_axi_arprot; wire [2 : 0] s01_axi_arprot = m00_axi_arprot;
wire s01_axi_arvalid = m00_axi_arvalid && is_led_key_r; wire s01_axi_arvalid = m00_axi_arvalid && is_uart_r;
wire s01_axi_arready; wire s01_axi_arready;
wire [31 : 0] s01_axi_rdata; wire [31 : 0] s01_axi_rdata;
wire [1 : 0] s01_axi_rresp; wire [1 : 0] s01_axi_rresp;
wire s01_axi_rvalid; wire s01_axi_rvalid;
wire s01_axi_rready = m00_axi_rready && is_led_key_r; wire s01_axi_rready = m00_axi_rready && is_uart_r;
hdl4se_uart_ctrl_axi ( hdl4se_uart_ctrl_axi (
.s00_axi_aclk(wClk), .s00_axi_aclk(wClk),
...@@ -270,7 +270,11 @@ module de1_riscv_axi( ...@@ -270,7 +270,11 @@ module de1_riscv_axi(
.s00_axi_rvalid(s01_axi_rvalid), .s00_axi_rvalid(s01_axi_rvalid),
.s00_axi_rready(s01_axi_rready), .s00_axi_rready(s01_axi_rready),
.uart_tx(uart_tx), .uart_tx(uart_tx),
.uart_rx(uart_rx) .uart_rx(uart_rx),
.dataready(LEDR[6]),
.sendready(LEDR[7]),
.sendfull(LEDR[8]),
.recvempty(LEDR[9])
); );
always @(*) always @(*)
......
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v
浏览文件 @ 6e8b1bac
...@@ -103,7 +103,7 @@ module riscv_core_with_axi_master ( ...@@ -103,7 +103,7 @@ module riscv_core_with_axi_master (
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata); regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2); regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
`define ALTERA_ `define ALTERA
`ifdef ALTERA `ifdef ALTERA
ram4kB ram(.clock(wClk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam)); ram4kB ram(.clock(wClk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam));
...@@ -136,12 +136,13 @@ module riscv_core_with_axi_master ( ...@@ -136,12 +136,13 @@ module riscv_core_with_axi_master (
//Write Address //Write Address
wire writeaxi = (wWrite && ((bWriteAddr & 32'hfff00000) != 0));
reg [31:0] awaddr; reg [31:0] awaddr;
reg awvalid; reg awvalid;
always @(posedge wClk) always @(posedge wClk)
if (~nwReset) begin if (~nwReset) begin
awvalid <= 1'b0; awvalid <= 1'b0;
end else if ((wWrite && ((bWriteAddr & 32'hfff00000) != 0))) begin end else if (writeaxi) begin
awaddr <= bWriteAddr; awaddr <= bWriteAddr;
awvalid <= 1'b1; awvalid <= 1'b1;
end else if (wAWReady) begin end else if (wAWReady) begin
...@@ -150,7 +151,7 @@ module riscv_core_with_axi_master ( ...@@ -150,7 +151,7 @@ module riscv_core_with_axi_master (
always @(wWrite or awvalid or bWriteAddr or awaddr) always @(wWrite or awvalid or bWriteAddr or awaddr)
begin begin
axi_awvalid = (wWrite && ((bWriteAddr & 32'hfff00000) != 0)) ? 1'b1 : awvalid; axi_awvalid = writeaxi ? 1'b1 : awvalid;
axi_awaddr = wWrite ? bWriteAddr : awaddr; axi_awaddr = wWrite ? bWriteAddr : awaddr;
end end
...@@ -162,7 +163,7 @@ module riscv_core_with_axi_master ( ...@@ -162,7 +163,7 @@ module riscv_core_with_axi_master (
begin begin
if (~nwReset) begin if (~nwReset) begin
wvalid <= 1'b0; wvalid <= 1'b0;
end if ((wWrite && ((bWriteAddr & 32'hfff00000) != 0))) begin end if (writeaxi) begin
wdata <= bWriteData; wdata <= bWriteData;
wstrb <= ~bWriteMask; wstrb <= ~bWriteMask;
wvalid <= 1'b1; wvalid <= 1'b1;
...@@ -171,22 +172,23 @@ module riscv_core_with_axi_master ( ...@@ -171,22 +172,23 @@ module riscv_core_with_axi_master (
end end
end end
assign wWriteReady = ((wWrite || wvalid) && wWReady) || (wWrite && ((bWriteAddr & 32'hfff00000) != 0)); assign wWriteReady = ((wWrite || wvalid) && wWReady) || writeaxi;
always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb) always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
begin begin
axi_wvalid = (wWrite && ((bWriteAddr & 32'hfff00000) != 0)) ? 1'b1 : wvalid; axi_wvalid = writeaxi ? 1'b1 : wvalid;
axi_wdata = (wWrite && ((bWriteAddr & 32'hfff00000) != 0)) ? bWriteData : wdata; axi_wdata = writeaxi ? bWriteData : wdata;
axi_wstrb = (wWrite && ((bWriteAddr & 32'hfff00000) != 0)) ? ~bWriteMask : wstrb; axi_wstrb = writeaxi ? ~bWriteMask : wstrb;
end end
wire readaxi = wRead && ((bReadAddr & 32'hfff00000) != 0);
//Read Address //Read Address
reg [31:0] araddr; reg [31:0] araddr;
reg arvalid; reg arvalid;
always @(posedge wClk) always @(posedge wClk)
if (~nwReset) begin if (~nwReset) begin
arvalid <= 1'b0; arvalid <= 1'b0;
end else if ((wRead && (bReadAddr & 32'hfff00000) != 0)) begin end else if (readaxi) begin
araddr <= bReadAddr; araddr <= bReadAddr;
arvalid <= 1'b1; arvalid <= 1'b1;
end else if (wARReady) begin end else if (wARReady) begin
...@@ -195,7 +197,7 @@ module riscv_core_with_axi_master ( ...@@ -195,7 +197,7 @@ module riscv_core_with_axi_master (
always @(wRead or arvalid or bReadAddr or araddr) always @(wRead or arvalid or bReadAddr or araddr)
begin begin
axi_arvalid = (wRead && (bReadAddr & 32'hfff00000) != 0) ? 1'b1 : arvalid; axi_arvalid = readaxi ? 1'b1 : arvalid;
axi_araddr = wRead ? bReadAddr : araddr; axi_araddr = wRead ? bReadAddr : araddr;
end end
......
examples/hdl4se_riscv/verilog/uart/hdl4se_uart_ctrl_axi.v
浏览文件 @ 6e8b1bac
...@@ -136,22 +136,17 @@ module hdl4se_uart_ctrl_axi ...@@ -136,22 +136,17 @@ module hdl4se_uart_ctrl_axi
assign ctl_state = {28'h0, send_buf_full, send_buf_empty, recv_buf_full, ~recv_buf_empty}; assign ctl_state = {28'h0, send_buf_full, send_buf_empty, recv_buf_full, ~recv_buf_empty};
/* axi bus */ /* axi bus */
reg [3 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp; reg [1 : 0] axi_bresp;
reg axi_bvalid; reg axi_bvalid;
reg [3 : 0] axi_araddr;
reg axi_arready; reg axi_arready;
reg [31 : 0] axi_rdata; reg [31 : 0] axi_rdata;
reg [1 : 0] axi_rresp; reg [1 : 0] axi_rresp;
reg axi_rvalid; reg axi_rvalid;
wire slv_reg_rden; wire slv_reg_rden;
wire slv_reg_wren; wire slv_reg_wren;
reg aw_en;
assign s00_axi_awready = axi_awready; assign s00_axi_awready = 1'b1;
assign s00_axi_wready = axi_wready; assign s00_axi_wready = 1'b1;
assign s00_axi_bresp = axi_bresp; assign s00_axi_bresp = axi_bresp;
assign s00_axi_bvalid = axi_bvalid; assign s00_axi_bvalid = axi_bvalid;
assign s00_axi_arready = axi_arready; assign s00_axi_arready = axi_arready;
...@@ -159,45 +154,7 @@ module hdl4se_uart_ctrl_axi ...@@ -159,45 +154,7 @@ module hdl4se_uart_ctrl_axi
assign s00_axi_rdata = axi_rdata; assign s00_axi_rdata = axi_rdata;
assign s00_axi_rresp = axi_rresp; assign s00_axi_rresp = axi_rresp;
always @( posedge s00_axi_aclk ) assign slv_reg_wren = s00_axi_wvalid && s00_axi_awvalid;
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end else begin
if (~axi_awready && s00_axi_awvalid && s00_axi_wvalid && aw_en) begin
axi_awready <= 1'b1;
aw_en <= 1'b0;
end else if (s00_axi_bready && axi_bvalid) begin
aw_en <= 1'b1;
axi_awready <= 1'b1;
end else begin
axi_awready <= 1'b1;
end
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_awaddr <= 0;
end else if (~axi_awready && s00_axi_awvalid && s00_axi_wvalid && aw_en) begin
axi_awaddr <= s00_axi_awaddr;
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_wready <= 1'b0;
end else if (~axi_wready && s00_axi_wvalid && s00_axi_awvalid && aw_en ) begin
axi_wready <= 1'b1;
end else begin
axi_wready <= 1'b1;
end
end
assign slv_reg_wren = axi_wready && s00_axi_wvalid && axi_awready && s00_axi_awvalid;
always @( posedge s00_axi_aclk ) always @( posedge s00_axi_aclk )
begin begin
...@@ -222,7 +179,7 @@ module hdl4se_uart_ctrl_axi ...@@ -222,7 +179,7 @@ module hdl4se_uart_ctrl_axi
if ( s00_axi_aresetn == 1'b0 ) begin if ( s00_axi_aresetn == 1'b0 ) begin
axi_bvalid <= 0; axi_bvalid <= 0;
axi_bresp <= 2'b0; axi_bresp <= 2'b0;
end else if (axi_awready && s00_axi_awvalid && ~axi_bvalid && axi_wready && s00_axi_wvalid) begin end else if (slv_reg_wren) begin
axi_bvalid <= 1'b1; axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response axi_bresp <= 2'b0; // 'OKAY' response
end else if (s00_axi_bready && axi_bvalid) begin end else if (s00_axi_bready && axi_bvalid) begin
...@@ -230,47 +187,27 @@ module hdl4se_uart_ctrl_axi ...@@ -230,47 +187,27 @@ module hdl4se_uart_ctrl_axi
end end
end end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end else if (~axi_arready && s00_axi_arvalid) begin
axi_arready <= 1'b1;
axi_araddr <= s00_axi_araddr;
end else begin
axi_arready <= 1'b0;
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end else if (axi_arready && s00_axi_arvalid && ~axi_rvalid) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end else if (axi_rvalid && s00_axi_rready) begin
axi_rvalid <= 1'b0;
end
end
assign slv_reg_rden = axi_arready & s00_axi_arvalid & ~axi_rvalid;
always @( posedge s00_axi_aclk ) always @( posedge s00_axi_aclk )
begin begin
if ( s00_axi_aresetn == 1'b0 ) begin if ( s00_axi_aresetn == 1'b0 ) begin
axi_rdata <= 0; axi_rdata <= 0;
axi_rvalid <= 0;
recv_buf_read <= 1'b0; recv_buf_read <= 1'b0;
end else if (slv_reg_rden) begin axi_rresp <= 0;
end else if (s00_axi_arvalid) begin
recv_buf_read <= 1'b0; recv_buf_read <= 1'b0;
if ((s00_axi_araddr & 4'hf) == 8) /* read state */ axi_rvalid <= 0;
if ((s00_axi_araddr & 4'hf) == 8) begin /* read state */
axi_rdata <= ctl_state; axi_rdata <= ctl_state;
else if ((s00_axi_araddr & 4'hf) == 0) /* read recv */ axi_rvalid <= 1;
end else if ((s00_axi_araddr & 4'hf) == 0) begin/* read recv */
axi_rdata <= {recv_buf_empty, 23'b0, recv_buf_q}; axi_rdata <= {recv_buf_empty, 23'b0, recv_buf_q};
recv_buf_read <= ~recv_buf_empty; recv_buf_read <= ~recv_buf_empty;
axi_rvalid <= 1;
end
end else begin end else begin
recv_buf_read <= 1'b0; recv_buf_read <= 0;
axi_rvalid <= 0;
end end
end end
......
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