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提交 836b7294 编写于 作者: 饶先宏's avatar 饶先宏
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202106291109 全部verilog版本的俄罗斯方块终于跑通了

上级 f3b209ca
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Showing with 728 addition and 671 deletion
examples/terris/src/main.c
浏览文件 @ 836b7294
......@@ -49,7 +49,7 @@ unsigned long long clocks = 0;
static int running = 1;
#define VCDOUTPUT 1
#define VCDOUTPUT 0
int StopRunning()
{
......@@ -73,10 +73,12 @@ int main(int argc, char* argv[])
{
int i;
int width;
int resetwidth;
int count, unitcount;
IHDL4SEUnit** sim_unit;
IHDL4SEWaveOutput** vcdfile;
srand((unsigned int)time(NULL));
resetwidth = 10 + rand() % 50;
A_u_t_o_registor_terrisctrl();
A_u_t_o_registor_terrisctrl1();
A_u_t_o_registor_terris_flushtodisp();
......@@ -107,10 +109,16 @@ int main(int argc, char* argv[])
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_tick", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_speed", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/cur_key", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/stateAfterCheckKey", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/testidwhencheckkey", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/cur_key", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/outputx", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposx", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/outputy", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposy", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_testid", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/bResult", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_testx", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_testy", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposx", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposy", "out");
objectCall1(vcdfile, SetTopModule, topmodule);
objectCall0(vcdfile, StartRecord);
......@@ -123,7 +131,7 @@ int main(int argc, char* argv[])
#endif
objectCall0(sim_unit, Setup);
clocks++;
if (clocks > 10 + (rand() % 50))
if (clocks == resetwidth)
objectCall1(sim, SetReset, 1);
} while (running);
#if VCDOUTPUT
......
examples/terris/verilog/terris_ctrl.v
浏览文件 @ 836b7294
......@@ -91,7 +91,7 @@ module turnright(input [63:0] inblock,
hdl4se_bind4 #(16, 16, 16, 16) bindline(line0, line1, line2, line3, outblock);
endmodule
`define MAXSPEED 32'd2000
`define MAXSPEED 32'd500
/* 俄罗斯方块控制器V1 */
(*
......@@ -159,13 +159,16 @@ module teris_ctrl
);
assign stateAfterFlushToDisp = (wireout_curblock == 64'h0) ? `ST_GENBLOCK
: (wStateComplete ? `ST_CHECKKEY : `ST_FLUSHTODISP);
assign stateAfterCheckBlockCanSetTo = wStateComplete ?
( ((bResult == 0) && (wireout_testid == 0)) ? `ST_BLOCKWRITE :`ST_FLUSHTODISP)
assign stateAfterCheckBlockCanSetTo = wStateComplete ? (
(wireout_testid == 0) ? (bResult?`ST_FLUSHTODISP:`ST_BLOCKWRITE) : (
(wireout_testid == 4) ? (bResult?`ST_GENBLOCK:`ST_INIT) : `ST_FLUSHTODISP )
)
: `ST_CHECKBLOCKCANSETTO;
assign stateAfterCheckLine = wStateComplete ? ( (bResult < `YCOUNT) ? `ST_COPYLINES : `ST_CHECKBLOCKCANSETTO)
: `ST_CHECKLINE;
assign stateAfterCheckKey = ((cur_key == 0) && (wireout_tick <= wireout_speed)) ? `ST_CHECKKEY : `ST_CHECKBLOCKCANSETTO;
assign stateAfterCheckKey = ((cur_key[0] || cur_key[1] || cur_key[3]) && (wireout_score == 0)) ? `ST_INIT :
(((cur_key == 0) && (wireout_tick <= wireout_speed)) ? `ST_CHECKKEY : `ST_CHECKBLOCKCANSETTO);
/* 内部变量 */
/* 测试块 testx, testy, testid */
......@@ -178,7 +181,7 @@ module teris_ctrl
testxwencheckkey, // 2: ST_CHECKKEY,
wireout_testx, // 3: ST_CHECKBLOCKCANSETTO,
wireout_testx, // 4: ST_BLOCKWRITE,
wireout_curposx, // 5: ST_CHECKLINE,
8'd8, // 5: ST_CHECKLINE,
wireout_testx, // 6: ST_COPYLINES
wireout_testx, // 7: ST_GENBLOCK
wirein_testx
......@@ -196,7 +199,7 @@ module teris_ctrl
testywencheckkey, // 2: ST_CHECKKEY,
wireout_testy, // 3: ST_CHECKBLOCKCANSETTO,
wireout_testy, // 4: ST_BLOCKWRITE,
wireout_curposy, // 5: ST_CHECKLINE,
8'd0, // 5: ST_CHECKLINE,
wireout_testy, // 6: ST_COPYLINES
wireout_testy, // 7: ST_GENBLOCK
wirein_testy
......@@ -211,7 +214,7 @@ module teris_ctrl
*/
wire [7:0] wirein_testid, wireout_testid;
hdl4se_reg #(8) reg_testid(wClk, wirein_testid, wireout_testid);
hdl4se_mux8 #(8) mux_textid(
hdl4se_mux8 #(8) mux_testid(
wireout_state,
wireout_testid, // 0: ST_INIT
wireout_testid, // 1: ST_FLUSHTODISP,
......@@ -257,8 +260,6 @@ module teris_ctrl
wire [31:0] scoreAfterCheckLine, scoreAfterCheckKey;
wire [31:0] wirein_score, wireout_score;
hdl4se_reg #(32) terris_score(wClk, wirein_score, wireout_score);
assign wirein_score = wStateComplete ? nextscore : wireout_score;
wire [31:0] nextscore;
hdl4se_mux8 #(32) mux_score(
wireout_state,
32'd200, // 0: ST_INIT
......@@ -269,10 +270,10 @@ module teris_ctrl
scoreAfterCheckLine,// 5: ST_CHECKLINE,
wireout_score, // 6: ST_COPYLINES
wireout_score, // 7: ST_GENBLOCK
nextscore
wirein_score
);
assign scoreAfterCheckKey = (cur_key & 8'b111) ? (wireout_score - 1) :
((cur_key & 8'b1000) ? (wireout_score + 2) : wireout_score);
assign scoreAfterCheckKey = ( (cur_key[3] || cur_key[1] || cur_key[0])) ? (wireout_score - 1) :
(cur_key[2] ? (wireout_score + 2) : wireout_score);
assign scoreAfterCheckLine = (wStateComplete && (bResult >= `YCOUNT)) ? (wireout_score + ((wireout_checklinecount > 0) ?linescore:0)) : wireout_score;
wire [31:0] linescore;
hdl4se_mux4 #(32) mux_linescore(
......@@ -335,7 +336,7 @@ module teris_ctrl
nextblockx
);
assign curposxAfterCheckLine = wireout_curposx;
assign curposxAfterCheckLine = 8'd8;
wire [7:0] curposyAfterCheckKey, curposyAfterCheckLine, cursoryAfterCheckBlock;
wire [7:0] wirein_curposy, wireout_curposy;
......@@ -355,7 +356,7 @@ module teris_ctrl
nextblocky
);
assign curposyAfterCheckKey = wireout_curposy;
assign curposyAfterCheckLine = wireout_curposy;
assign curposyAfterCheckLine = 8'd0;
assign cursoryAfterCheckBlock = (bResult && (wireout_testid == 0))?(wireout_curposy + 1):wireout_curposy;
......@@ -381,7 +382,7 @@ module teris_ctrl
assign curblockWhenFlushToDisp = (wireout_curblock == 64'b0) ? wireout_nextblock : wireout_curblock;
assign curblockAfterCheckBlock = (wStateComplete && bResult && (wireout_testid == 3)) ? curblockturnleft : wireout_curblock;
assign curblockAfterCheckLine = wireout_curblock;
assign curblockAfterCheckLine = (wStateComplete && (bResult >= `YCOUNT)) ? wireout_nextblock : wireout_curblock;
/* 下一块形状: INIT和CHECKLINE会修改，其他状态保持 */
wire [63:0] wirein_nextblock, wireout_nextblock;
......
examples/terris/verilog/terris_main_asm.v
浏览文件 @ 836b7294
......@@ -573,7 +573,6 @@ module teris_ctrl
wire [31:0] scoreAfterCheckKey;
wire [31:0] wirein_score;
wire [31:0] wireout_score;
wire [31:0] nextscore;
wire [31:0] linescore;
wire [31:0] levelAfterCheckLine;
wire [31:0] wirein_level;
......@@ -609,33 +608,32 @@ module teris_ctrl
wire [31:0] cur_key;
assign bState = wireout_state;
assign bScore = wireout_score;
assign bSpeed = (32'h7d0-wireout_speed);
assign bSpeed = (32'h1f4-wireout_speed);
assign bLevel = wireout_level;
assign bNextBlock = wireout_nextblock;
assign bCurBlock = ((cur_key [3] )?(curblockturnleft):(wireout_curblock));
assign wirein_state = ((nwReset)?(nextstate):(0));
assign stateAfterFlushToDisp = (((wireout_curblock==64'h0))?(7):(((wStateComplete)?(2):(1))));
assign stateAfterCheckBlockCanSetTo = ((wStateComplete)?(((((bResult==0)&&(wireout_testid==0)))?(4):(1))):(3));
assign stateAfterCheckBlockCanSetTo = ((wStateComplete)?((((wireout_testid==0))?(((bResult)?(1):(4))):((((wireout_testid==4))?(((bResult)?(7):(0))):(1))))):(3));
assign stateAfterCheckLine = ((wStateComplete)?((((bResult<24))?(6):(3))):(5));
assign stateAfterCheckKey = ((((cur_key==0)&&(wireout_tick<=wireout_speed)))?(2):(3));
assign stateAfterCheckKey = ((((cur_key [0] ||(cur_key [1] ||cur_key [3] ))&&(wireout_score==0)))?(0):(((((cur_key==0)&&(wireout_tick<=wireout_speed)))?(2):(3))));
assign wirein_startline = (((wStateComplete&&(bState==5)))?(bResult):(wireout_startline));
assign wirein_testparam = (((bState==2))?(cur_key):(wireout_testparam));
assign wirein_score = ((wStateComplete)?(nextscore):(wireout_score));
assign scoreAfterCheckKey = (((cur_key&8'b111))?((wireout_score-1)):((((cur_key&8'b1000))?((wireout_score+2)):(wireout_score))));
assign scoreAfterCheckKey = (((cur_key [3] ||(cur_key [1] ||cur_key [0] )))?((wireout_score-1)):(((cur_key [2] )?((wireout_score+2)):(wireout_score))));
assign scoreAfterCheckLine = (((wStateComplete&&(bResult>=24)))?((wireout_score+(((wireout_checklinecount>0))?(linescore):(0)))):(wireout_score));
assign wirein_level = ((wStateComplete)?(nextlevel):(wireout_level));
assign levelAfterCheckLine = (((wStateComplete&&(bResult>=24)))?((wireout_level+wireout_checklinecount)):(wireout_level));
assign wirein_speed = (((32'h7d0>scorediv4))?((32'd2000-scorediv4)):(1));
assign wirein_speed = (((32'h1f4>scorediv4))?((32'd500-scorediv4)):(1));
assign wirein_tick = ((((nwReset==0)||((cur_key!=0)||(wireout_state!=2))))?(0):((wireout_tick+1)));
assign wirein_curposx = ((wStateComplete)?(nextblockx):(wireout_curposx));
assign curposxAfterCheckLine = wireout_curposx;
assign curposxAfterCheckLine = 8;
assign wirein_curposy = ((wStateComplete)?(nextblocky):(wireout_curposy));
assign curposyAfterCheckKey = wireout_curposy;
assign curposyAfterCheckLine = wireout_curposy;
assign curposyAfterCheckLine = 0;
assign cursoryAfterCheckBlock = (((bResult&&(wireout_testid==0)))?((wireout_curposy+1)):(wireout_curposy));
assign curblockWhenFlushToDisp = (((wireout_curblock==64'b0))?(wireout_nextblock):(wireout_curblock));
assign curblockAfterCheckBlock = (((wStateComplete&&(bResult&&(wireout_testid==3))))?(curblockturnleft):(wireout_curblock));
assign curblockAfterCheckLine = wireout_curblock;
assign curblockAfterCheckLine = (((wStateComplete&&(bResult>=24)))?(wireout_nextblock):(wireout_curblock));
assign wirein_nextblock = (((wStateComplete&&(wireout_state==7)))?(bNewNextBlock):(wireout_nextblock));
assign wirein_key = bKeyData;
assign outputx = (((wireout_state==3))?((wireout_testx+1)):((((wireout_state==6))?(wireout_startline):((wireout_curposx+1)))));
......@@ -652,12 +650,12 @@ module teris_ctrl
, stateAfterCheckLine, ((wStateComplete)?(5):(6)), ((wStateComplete)?(1):(7)), nextstate );
hdl4se_reg #( 8 ) reg_testx( wClk, wirein_testx, wireout_testx );
hdl4se_mux8 #( 8 ) mux_testx( wireout_state, wireout_testx, wireout_testx, testxwencheckkey, wireout_testx, wireout_testx
, wireout_curposx, wireout_testx, wireout_testx, wirein_testx );
, 8, wireout_testx, wireout_testx, wirein_testx );
hdl4se_reg #( 8 ) reg_testy( wClk, wirein_testy, wireout_testy );
hdl4se_mux8 #( 8 ) mux_testy( wireout_state, wireout_testy, wireout_testy, testywencheckkey, wireout_testy, wireout_testy
, wireout_curposy, wireout_testy, wireout_testy, wirein_testy );
, 0, wireout_testy, wireout_testy, wirein_testy );
hdl4se_reg #( 8 ) reg_testid( wClk, wirein_testid, wireout_testid );
hdl4se_mux8 #( 8 ) mux_textid( wireout_state, wireout_testid, wireout_testid, testidwhencheckkey, wireout_testid, wireout_testid
hdl4se_mux8 #( 8 ) mux_testid( wireout_state, wireout_testid, wireout_testid, testidwhencheckkey, wireout_testid, wireout_testid
, 4, wireout_testid, wireout_testid, wirein_testid );
hdl4se_reg #( 8 ) reg_startline( wClk, wirein_startline, wireout_startline );
hdl4se_reg #( 32 ) reg_checklinecount( wClk, wirein_checklinecount, wireout_checklinecount );
......@@ -666,7 +664,7 @@ module teris_ctrl
hdl4se_reg #( 8 ) reg_testparam( wClk, wirein_testparam, wireout_testparam );
hdl4se_reg #( 32 ) terris_score( wClk, wirein_score, wireout_score );
hdl4se_mux8 #( 32 ) mux_score( wireout_state, 32'hc8, wireout_score, scoreAfterCheckKey, wireout_score, wireout_score
, scoreAfterCheckLine, wireout_score, wireout_score, nextscore );
, scoreAfterCheckLine, wireout_score, wireout_score, wirein_score );
hdl4se_mux4 #( 32 ) mux_linescore( (wireout_checklinecount-1), 32'ha, 32'h28, 32'ha0, 32'h280, linescore
);
hdl4se_reg #( 32 ) terris_level( wClk, wirein_level, wireout_level );
......
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