202109101725

examples/hdl4se_riscv/de1/de1_riscv_v5.qpf

+DATE = "14:35:32 September 10, 2021"
+QUARTUS_VERSION = "15.1.0"
+
+# Revisions
+
+PROJECT_REVISION = "de1_riscv_v5"

examples/hdl4se_riscv/de1/de1_riscv_v5.sdc

+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 20.000ns [get_ports CLOCK2_50]
+create_clock -period 20.000ns [get_ports CLOCK3_50]
+create_clock -period 20.000ns [get_ports CLOCK4_50]
+create_clock -period 20.000ns [get_ports CLOCK_50]
+
+create_clock -period "27 MHz"  -name tv_27m [get_ports TD_CLK27]
+create_clock -period "100 MHz" -name clk_dram [get_ports DRAM_CLK]
+# AUDIO : 48kHz 384fs 32-bit data
+create_clock -period "18.432 MHz" -name clk_audxck [get_ports AUD_XCK]
+create_clock -period "1.536 MH" -name clk_audbck [get_ports AUD_BCLK]
+# VGA : 640x480@60Hz
+#create_clock -period "25.18 MHz" -name clk_vga [get_ports VGA_CLK]
+# VGA : 800x600@60Hz
+#create_clock -period "40.0 MHz" -name clk_vga [get_ports VGA_CLK]
+# VGA : 1024x768@60Hz
+#create_clock -period "65.0 MHz" -name clk_vga [get_ports VGA_CLK]
+# VGA : 1280x1024@60Hz
+create_clock -period "108.0 MHz" -name clk_vga [get_ports VGA_CLK]
+
+# for enhancing USB BlasterII to be reliable, 25MHz
+create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+# Board Delay (Data) + Propagation Delay - Board Delay (Clock)
+set_input_delay -max -clock clk_dram -0.048 [get_ports DRAM_DQ*]
+set_input_delay -min -clock clk_dram -0.057 [get_ports DRAM_DQ*]
+
+set_input_delay -max -clock tv_27m 3.508 -clock_fall [get_ports TD_DATA*]
+set_input_delay -min -clock tv_27m -2.539 -clock_fall [get_ports TD_DATA*]
+set_input_delay -max -clock tv_27m 3.654 -clock_fall [get_ports TD_HS]
+set_input_delay -min -clock tv_27m -2.454 -clock_fall [get_ports TD_HS]
+set_input_delay -max -clock tv_27m 3.652 -clock_fall [get_ports TD_VS]
+set_input_delay -min -clock tv_27m -2.456 -clock_fall [get_ports TD_VS]
+
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)
+# min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
+set_output_delay -max -clock clk_dram 1.452  [get_ports DRAM_DQ*]
+set_output_delay -min -clock clk_dram -0.857 [get_ports DRAM_DQ*]
+set_output_delay -max -clock clk_dram 1.531 [get_ports DRAM_ADDR*]
+set_output_delay -min -clock clk_dram -0.805 [get_ports DRAM_ADDR*]
+set_output_delay -max -clock clk_dram 1.533  [get_ports DRAM_*DQM]
+set_output_delay -min -clock clk_dram -0.805 [get_ports DRAM_*DQM]
+set_output_delay -max -clock clk_dram 1.510  [get_ports DRAM_BA*]
+set_output_delay -min -clock clk_dram -0.800 [get_ports DRAM_BA*]
+set_output_delay -max -clock clk_dram 1.520  [get_ports DRAM_RAS_N]
+set_output_delay -min -clock clk_dram -0.780 [get_ports DRAM_RAS_N]
+set_output_delay -max -clock clk_dram 1.5000  [get_ports DRAM_CAS_N]
+set_output_delay -min -clock clk_dram -0.800 [get_ports DRAM_CAS_N]
+set_output_delay -max -clock clk_dram 1.545 [get_ports DRAM_WE_N]
+set_output_delay -min -clock clk_dram -0.755 [get_ports DRAM_WE_N]
+set_output_delay -max -clock clk_dram 1.496  [get_ports DRAM_CKE]
+set_output_delay -min -clock clk_dram -0.804 [get_ports DRAM_CKE]
+set_output_delay -max -clock clk_dram 1.508  [get_ports DRAM_CS_N]
+set_output_delay -min -clock clk_dram -0.792 [get_ports DRAM_CS_N]
+
+set_output_delay -max -clock clk_vga 0.220 [get_ports VGA_R*]
+set_output_delay -min -clock clk_vga -1.506 [get_ports VGA_R*]
+set_output_delay -max -clock clk_vga 0.212 [get_ports VGA_G*]
+set_output_delay -min -clock clk_vga -1.519 [get_ports VGA_G*]
+set_output_delay -max -clock clk_vga 0.264 [get_ports VGA_B*]
+set_output_delay -min -clock clk_vga -1.519 [get_ports VGA_B*]
+set_output_delay -max -clock clk_vga 0.215 [get_ports VGA_BLANK]
+set_output_delay -min -clock clk_vga -1.485 [get_ports VGA_BLANK]
+
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

examples/hdl4se_riscv/de1/de1_riscv_v5.v

+
+//=======================================================
+//  This code is generated by Terasic System Builder
+//=======================================================
+
+`define USECLOCK50
+
+module de1_riscv_v5(
+
+	//////////// ADC //////////
+	output		          		ADC_CONVST,
+	output		          		ADC_DIN,
+	input 		          		ADC_DOUT,
+	output		          		ADC_SCLK,
+
+	//////////// Audio //////////
+	input 		          		AUD_ADCDAT,
+	inout 		          		AUD_ADCLRCK,
+	inout 		          		AUD_BCLK,
+	output		          		AUD_DACDAT,
+	inout 		          		AUD_DACLRCK,
+	output		          		AUD_XCK,
+
+	//////////// CLOCK //////////
+	input 		          		CLOCK2_50,
+	input 		          		CLOCK3_50,
+	input 		          		CLOCK4_50,
+	input 		          		CLOCK_50,
+
+	//////////// SDRAM //////////
+	output		    [12:0]		DRAM_ADDR,
+	output		     [1:0]		DRAM_BA,
+	output		          		DRAM_CAS_N,
+	output		          		DRAM_CKE,
+	output		          		DRAM_CLK,
+	output		          		DRAM_CS_N,
+	inout 		    [15:0]		DRAM_DQ,
+	output		          		DRAM_LDQM,
+	output		          		DRAM_RAS_N,
+	output		          		DRAM_UDQM,
+	output		          		DRAM_WE_N,
+
+	//////////// I2C for Audio and Video-In //////////
+	output		          		FPGA_I2C_SCLK,
+	inout 		          		FPGA_I2C_SDAT,
+
+	//////////// SEG7 //////////
+	output		     [6:0]		HEX0,
+	output		     [6:0]		HEX1,
+	output		     [6:0]		HEX2,
+	output		     [6:0]		HEX3,
+	output		     [6:0]		HEX4,
+	output		     [6:0]		HEX5,
+
+	//////////// IR //////////
+	input 		          		IRDA_RXD,
+	output		          		IRDA_TXD,
+
+	//////////// KEY //////////
+	input 		     [3:0]		KEY,
+
+	//////////// LED //////////
+	output		     [9:0]		LEDR,
+
+	//////////// PS2 //////////
+	inout 		          		PS2_CLK,
+	inout 		          		PS2_CLK2,
+	inout 		          		PS2_DAT,
+	inout 		          		PS2_DAT2,
+
+	//////////// SW //////////
+	input 		     [9:0]		SW,
+
+	//////////// Video-In //////////
+	input 		          		TD_CLK27,
+	input 		     [7:0]		TD_DATA,
+	input 		          		TD_HS,
+	output		          		TD_RESET_N,
+	input 		          		TD_VS,
+
+	//////////// VGA //////////
+	output		          		VGA_BLANK_N,
+	output		     [7:0]		VGA_B,
+	output		          		VGA_CLK,
+	output		     [7:0]		VGA_G,
+	output		          		VGA_HS,
+	output		     [7:0]		VGA_R,
+	output		          		VGA_SYNC_N,
+	output		          		VGA_VS,
+
+	//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
+	inout 		    [35:0]		GPIO
+);
+
+
+  wire        uart_tx;
+  wire        uart_rx;
+  assign GPIO[5] = uart_tx;
+  assign GPIO[7] = 1'bz;
+  assign      uart_rx = GPIO[7];
+
+  assign LEDR[0] = uart_tx;
+  assign LEDR[1] = uart_rx;
+
+`ifdef USECLOCK50
+	wire wClk = CLOCK_50;
+`else
+	wire clk100MHz, clk75MHz, clklocked;
+	clk100M clk100(.refclk(CLOCK_50),
+	               .rst(~KEY[3]),
+				   .outclk_0(clk100MHz), 
+				   .outclk_1(clk75MHz),
+				   .locked(clklocked));
+				   
+	wire wClk = clk100MHz;
+`endif
+	wire nwReset = KEY[3];
+
+    wire wWrite, wRead;
+    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
+    wire [3:0]  bWriteMask;
+
+`define TESTALEXUART_
+
+`ifdef TESTALEXUART
+reg [7:0] uart_tx_axis_tdata;
+reg uart_tx_axis_tvalid;
+wire uart_tx_axis_tready;
+
+wire [7:0] uart_rx_axis_tdata;
+wire uart_rx_axis_tvalid;
+reg uart_rx_axis_tready;
+
+uart
+uart_inst (
+    .clk(wClk),
+    .rst(~nwReset),
+    // AXI input
+    .s_axis_tdata(uart_tx_axis_tdata),
+    .s_axis_tvalid(uart_tx_axis_tvalid),
+    .s_axis_tready(uart_tx_axis_tready),
+    // AXI output
+    .m_axis_tdata(uart_rx_axis_tdata),
+    .m_axis_tvalid(uart_rx_axis_tvalid),
+    .m_axis_tready(uart_rx_axis_tready),
+    // uart
+    .rxd(uart_rx),
+    .txd(uart_tx),
+    // status
+    .tx_busy(),
+    .rx_busy(),
+    .rx_overrun_error(),
+    .rx_frame_error(),
+    // configuration
+    .prescale(50000000/(115200*8))
+);
+
+always @(posedge wClk or negedge nwReset) begin
+    if (~nwReset) begin
+        uart_tx_axis_tdata <= 0;
+        uart_tx_axis_tvalid <= 0;
+        uart_rx_axis_tready <= 0;
+    end else begin
+        if (uart_tx_axis_tvalid) begin
+            // attempting to transmit a byte
+            // so can't receive one at the moment
+            uart_rx_axis_tready <= 0;
+            // if it has been received, then clear the valid flag
+            if (uart_tx_axis_tready) begin
+                uart_tx_axis_tvalid <= 0;
+            end
+        end else begin
+            // ready to receive byte
+            uart_rx_axis_tready <= 1;
+            if (uart_rx_axis_tvalid) begin
+                // got one, so make sure it gets the correct ready signal
+                // (either clear it if it was set or set it if we just got a
+                // byte out of waiting for the transmitter to send one)
+                uart_rx_axis_tready <= ~uart_rx_axis_tready;
+                // send byte back out
+                uart_tx_axis_tdata <= uart_rx_axis_tdata;
+                uart_tx_axis_tvalid <= 1;
+            end
+        end
+    end
+end
+
+`else
+	uart_ctrl uart_ctrl(
+		.wClk(wClk), 
+		.nwReset(nwReset),
+		.wRead(((bReadAddr & 32'hffffff00) == 32'hf0000100)?wRead:1'b0), 
+		.bReadAddr(bReadAddr),
+		.wWrite(((bWriteAddr & 32'hffffff00) == 32'hf0000100)?wWrite:1'b0), 
+		.bWriteAddr(bWriteAddr),
+		.bWriteData(bWriteData),
+		.bReadData(bReadDataUart),
+		.uart_tx(uart_tx), 
+		.uart_rx(uart_rx),
+		.dataready(LEDR[2]),
+		.sendready(LEDR[3]),
+		.sendfull(LEDR[4]),
+		.recvempty(LEDR[5])
+	);
+`endif
+
+		/* AXI signal */
+		// Write Address
+		wire			wAWValid;
+		wire [31 : 0]	bAWAddr;
+		wire [2 : 0]	bAWProt;
+		wire			wAWReady = 1'b1;
+
+		// Write Data 
+		wire			wWValid;
+		wire [31 : 0]	bWData;
+		wire [3 : 0]	bWStrb;
+		wire			wWReady = 1'b1;
+
+		// Write Response
+		wire			wBReady;
+		wire [1 : 0]	bBResp;
+		wire			wBValid = 1'b1;
+
+		assign wWrite = wAWValid;
+		assign bWriteAddr = bAWAddr;
+		assign bWriteData = bWData;
+		assign bWriteMask = ~bWStrb; 
+
+		reg            read_r;
+		always@(posedge wClk)
+			read_r <= wRead;
+		// ReadAddr
+		wire			wARValid;
+		wire [31 : 0]	bARAddr;
+		wire [2 : 0]	bARProt;
+		wire			wARReady = 1'b1;
+
+		assign bReadAddr = bARAddr;
+		assign wRead = wARValid;
+
+		//ReadData
+		wire			wRReady;
+		wire			wRValid = read_r;
+		wire [31 : 0]	bRData = bReadDataUart;
+		wire [1 : 0]	bRResp = 1'b0;
+
+		riscv_core_with_axi_master riscv_core_with_axi(
+			// clock and reset
+			wClk,
+			nwReset,
+	
+			// Write Address
+			wAWValid,
+			bAWAddr,
+			bAWProt,
+			wAWReady,
+	
+			// Write Data 
+			wWValid,
+			bWData,
+			bWStrb,
+			wWReady,
+	
+			// Write Response
+			wBReady,
+			bBResp,
+			wBValid,
+	
+			// ReadAddr
+			wARValid,
+			bARAddr,
+			bARProt,
+			wARReady,
+	
+			//ReadData
+			wRReady,
+			wRValid,
+			bRData,
+			bRResp
+		);
+
+	reg [6:0] led0;
+	reg [6:0] led1;
+	reg [6:0] led2;
+	reg [6:0] led3;
+	reg [6:0] led4;
+	reg [6:0] led5;
+	assign HEX0 = ~led0;
+	assign HEX1 = ~led1;
+	assign HEX2 = ~led2;
+	assign HEX3 = ~led3;
+	assign HEX4 = ~led4;
+	assign HEX5 = ~led5;
+
+	
+
+	always @(posedge wClk) begin
+		if (!nwReset) begin
+			led0 <= 7'h3f;
+			led1 <= 7'h3f;
+			led2 <= 7'h3f;
+			led3 <= 7'h3f;
+			led4 <= 7'h3f;
+			led5 <= 7'h3f;
+		end else begin
+			if (SW[8]) begin
+				led0 <= 7'h06;
+				led1 <= 7'h06;
+				led2 <= 7'h06;
+				led3 <= 7'h07;
+				led4 <= 7'h07;
+				led5 <= 7'h07;				
+			end
+			else if (SW[9]) begin
+				led0 <= 7'h3f;
+				led1 <= 7'h06;
+				led2 <= 7'h5b;
+				led3 <= 7'h4f;
+				led4 <= 7'h66;
+				led5 <= 7'h6d;				
+			end
+			else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin
+				if (bWriteAddr[7:0] == 8'h10) begin
+					led0 <= bWriteData[6:0];
+					led1 <= bWriteData[14:8];
+					led2 <= bWriteData[22:16];
+					led3 <= bWriteData[30:24];
+				end else if (bWriteAddr[7:0] == 8'h14) begin
+					led4 <= bWriteData[6:0];
+					led5 <= bWriteData[14:8];
+				end
+			end
+		end
+	end
+
+
+endmodule

examples/hdl4se_riscv/test_code/test_new.c

 int testadd()
 {
 	int i;
-	int a[16] = {863339516, 821515056, 1083581092, -1690958248, 1933660748, -1566795136, -186993932, -508514392, -878058340, 387704272, -1386576060, -1070867208, -511952148, -1018022624, 872587156, 715427400, };
-	int b[16] = {684048083, 417734967, -2021621029, -1690785857, -148925469, -2133357753, 1375212011, 1488055247, 1806900467, -716510889, -1714563845, -46554145, 202988035, 732511079, -180696053, -522661905, };
-	int c[16] = {1547387599, 1239250023, -938039937, 913223191, 1784735279, 594814407, 1188218079, 979540855, 928842127, -328806617, 1193827391, -1117421353, -308964113, -285511545, 691891103, 192765495, };
+	int a[16] = {-93274203, -76479575, -1782331155, 2052420465, 523347765, -582531015, -1687389571, 715301377, -1214618939, -176709431, -438992883, 1644848273, -911478187, 2052263257, -190850659, -763512031, };
+	int b[16] = {1118302168, 499397580, -1694632960, -1642068876, -929597144, 807904796, 1843273552, -1723418428, 64980600, -926098324, -2066919776, -898780908, 645732296, -926886212, 619217392, 532802916, };
+	int c[16] = {1025027965, 422918005, 818003181, 410351589, -406249379, 225373781, 155883981, -1008117051, -1149638339, -1102807755, 1789054637, 746067365, -265745891, 1125377045, 428366733, -230709115, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] + b[i] != c[i])
 			return i;
@@ -13,9 +13,9 @@ int testadd()
 int testsub()
 {
 	int i;
-	int a[16] = {863339516, 821515056, 1083581092, -1690958248, 1933660748, -1566795136, -186993932, -508514392, -878058340, 387704272, -1386576060, -1070867208, -511952148, -1018022624, 872587156, 715427400, };
-	int b[16] = {684048083, 417734967, -2021621029, -1690785857, -148925469, -2133357753, 1375212011, 1488055247, 1806900467, -716510889, -1714563845, -46554145, 202988035, 732511079, -180696053, -522661905, };
-	int c[16] = {179291433, 403780089, -1189765175, -172391, 2082586217, 566562617, -1562205943, -1996569639, 1610008489, 1104215161, 327987785, -1024313063, -714940183, -1750533703, 1053283209, 1238089305, };
+	int a[16] = {-93274203, -76479575, -1782331155, 2052420465, 523347765, -582531015, -1687389571, 715301377, -1214618939, -176709431, -438992883, 1644848273, -911478187, 2052263257, -190850659, -763512031, };
+	int b[16] = {1118302168, 499397580, -1694632960, -1642068876, -929597144, 807904796, 1843273552, -1723418428, 64980600, -926098324, -2066919776, -898780908, 645732296, -926886212, 619217392, 532802916, };
+	int c[16] = {-1211576371, -575877155, -87698195, -600477955, 1452944909, -1390435811, 764304173, -1856247491, -1279599539, 749388893, 1627926893, -1751338115, -1557210483, -1315817827, -810068051, -1296314947, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] - b[i] != c[i])
 			return i;
@@ -25,9 +25,9 @@ int testsub()
 int testmul()
 {
 	int i;
-	int a[16] = {863339516, 821515056, 1083581092, -1690958248, 1933660748, -1566795136, -186993932, -508514392, -878058340, 387704272, -1386576060, -1070867208, -511952148, -1018022624, 872587156, 715427400, };
-	int b[16] = {684048083, 417734967, -2021621029, -1690785857, -148925469, -2133357753, 1375212011, 1488055247, 1806900467, -716510889, -1714563845, -46554145, 202988035, 732511079, -180696053, -522661905, };
-	int c[16] = {-1833119564, -1543762096, 1275521612, -1229839448, 6397284, -489531008, -620463620, -498777896, -195489772, -1127913040, -449122388, -1625332728, 574073028, -93208608, 516868956, -345174728, };
+	int a[16] = {-93274203, -76479575, -1782331155, 2052420465, 523347765, -582531015, -1687389571, 715301377, -1214618939, -176709431, -438992883, 1644848273, -911478187, 2052263257, -190850659, -763512031, };
+	int b[16] = {1118302168, 499397580, -1694632960, -1642068876, -929597144, 807904796, 1843273552, -1723418428, 64980600, -926098324, -2066919776, -898780908, 645732296, -926886212, 619217392, 532802916, };
+	int c[16] = {548388408, -735210068, -1078270976, -257551564, 1611476296, 491772988, 639724048, 1849344196, 950823512, -2066706228, -253952480, 336927828, -224660120, -857328804, 751575088, -1304713756, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] * b[i] != c[i])
 			return i;
@@ -37,9 +37,9 @@ int testmul()
 int testdiv()
 {
 	int i;
-	int a[16] = {863339516, 821515056, 1083581092, -1690958248, 1933660748, -1566795136, -186993932, -508514392, -878058340, 387704272, -1386576060, -1070867208, -511952148, -1018022624, 872587156, 715427400, };
-	int b[16] = {684048083, 417734967, -2021621029, -1690785857, -148925469, -2133357753, 1375212011, 1488055247, 1806900467, -716510889, -1714563845, -46554145, 202988035, 732511079, -180696053, -522661905, };
-	int c[16] = {1, 1, 0, 1, -12, 0, 0, 0, 0, 0, 0, 23, -2, -1, -4, -1, };
+	int a[16] = {-93274203, -76479575, -1782331155, 2052420465, 523347765, -582531015, -1687389571, 715301377, -1214618939, -176709431, -438992883, 1644848273, -911478187, 2052263257, -190850659, -763512031, };
+	int b[16] = {1118302168, 499397580, -1694632960, -1642068876, -929597144, 807904796, 1843273552, -1723418428, 64980600, -926098324, -2066919776, -898780908, 645732296, -926886212, 619217392, 532802916, };
+	int c[16] = {0, 0, 1, -1, 0, 0, 0, 0, -18, 0, 0, -1, -1, -2, 0, -1, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] / b[i] != c[i])
 			return i;
@@ -49,9 +49,9 @@ int testdiv()
 int testmod()
 {
 	int i;
-	int a[16] = {863339516, 821515056, 1083581092, -1690958248, 1933660748, -1566795136, -186993932, -508514392, -878058340, 387704272, -1386576060, -1070867208, -511952148, -1018022624, 872587156, 715427400, };
-	int b[16] = {684048083, 417734967, -2021621029, -1690785857, -148925469, -2133357753, 1375212011, 1488055247, 1806900467, -716510889, -1714563845, -46554145, 202988035, 732511079, -180696053, -522661905, };
-	int c[16] = {179291433, 403780089, 1083581092, -172391, 146555120, -1566795136, -186993932, -508514392, -878058340, 387704272, -1386576060, -121873, -105976078, -285511545, 149802944, 192765495, };
+	int a[16] = {-93274203, -76479575, -1782331155, 2052420465, 523347765, -582531015, -1687389571, 715301377, -1214618939, -176709431, -438992883, 1644848273, -911478187, 2052263257, -190850659, -763512031, };
+	int b[16] = {1118302168, 499397580, -1694632960, -1642068876, -929597144, 807904796, 1843273552, -1723418428, 64980600, -926098324, -2066919776, -898780908, 645732296, -926886212, 619217392, 532802916, };
+	int c[16] = {-93274203, -76479575, -87698195, 410351589, 523347765, -582531015, -1687389571, 715301377, -44968139, -176709431, -438992883, 746067365, -265745891, 198490833, -190850659, -230709115, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] % b[i] != c[i])
 			return i;
@@ -61,9 +61,9 @@ int testmod()
 int testaddu()
 {
 	int i;
-	unsigned int a[16] = {0xc8fb2a4d, 0xb9e89321, 0x94f4fe35, 0xb2451f89, 0xb9b5eb1d, 0xe07094f1, 0xa4be9105, 0x7c1d9359, 0x27938fed, 0xa242bac1, 0xde3d87d5, 0xc39aab29, 0x25c918bd, 0xa3240491, 0xa2c6e2a5, 0xe4a166f9, };
-	unsigned int b[16] = {0xdb5893dc, 0x52e4a960, 0x4f6cb824, 0xa452a428, 0xe6cf916c, 0x0537e3f0, 0x637f3fb4, 0x20fc88b8, 0x6b6de2fc, 0x033cb280, 0x55019b44, 0xcc488148, 0x4394888c, 0xb5a41510, 0x93f4cad4, 0x66878dd8, };
-	unsigned int c[16] = {0xa453be29, 0x0ccd3c81, 0xe461b659, 0x5697c3b1, 0xa0857c89, 0xe5a878e1, 0x083dd0b9, 0x9d1a1c11, 0x930172e9, 0xa57f6d41, 0x333f2319, 0x8fe32c71, 0x695da149, 0x58c819a1, 0x36bbad79, 0x4b28f4d1, };
+	unsigned int a[16] = {0x2368eb3e, 0xdffcef62, 0xfff97ec6, 0x344e1d6a, 0xce038f4e, 0x6a1fd872, 0x94ca3cd6, 0xa7af407a, 0x67a4a75e, 0x258d7582, 0x667deee6, 0x571f978a, 0x8e55336e, 0xe31ec692, 0x59bd94f6, 0x6c18229a, };
+	unsigned int b[16] = {0x36225509, 0x5debd89d, 0xc238ba71, 0x7b4a6e85, 0x3616a8d9, 0xc09b5d6d, 0xb072c041, 0x57a74555, 0x7bc7a0a9, 0x833ac63d, 0x0cd3ea11, 0x25a68025, 0x911a3c79, 0xd73f130d, 0x0d6137e1, 0x8cdd1ef5, };
+	unsigned int c[16] = {0x598b4047, 0x3de8c7ff, 0xc2323937, 0xaf988bef, 0x041a3827, 0x2abb35df, 0x453cfd17, 0xff5685cf, 0xe36c4807, 0xa8c83bbf, 0x7351d8f7, 0x7cc617af, 0x1f6f6fe7, 0xba5dd99f, 0x671eccd7, 0xf8f5418f, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] + b[i] != c[i])
 			return i;
@@ -73,9 +73,9 @@ int testaddu()
 int testsubu()
 {
 	int i;
-	unsigned int a[16] = {0xc8fb2a4d, 0xb9e89321, 0x94f4fe35, 0xb2451f89, 0xb9b5eb1d, 0xe07094f1, 0xa4be9105, 0x7c1d9359, 0x27938fed, 0xa242bac1, 0xde3d87d5, 0xc39aab29, 0x25c918bd, 0xa3240491, 0xa2c6e2a5, 0xe4a166f9, };
-	unsigned int b[16] = {0xdb5893dc, 0x52e4a960, 0x4f6cb824, 0xa452a428, 0xe6cf916c, 0x0537e3f0, 0x637f3fb4, 0x20fc88b8, 0x6b6de2fc, 0x033cb280, 0x55019b44, 0xcc488148, 0x4394888c, 0xb5a41510, 0x93f4cad4, 0x66878dd8, };
-	unsigned int c[16] = {0xeda29671, 0x6703e9c1, 0x45884611, 0x0df27b61, 0xd2e659b1, 0xdb38b101, 0x413f5151, 0x5b210aa1, 0xbc25acf1, 0x9f060841, 0x893bec91, 0xf75229e1, 0xe2349031, 0xed7fef81, 0x0ed217d1, 0x7e19d921, };
+	unsigned int a[16] = {0x2368eb3e, 0xdffcef62, 0xfff97ec6, 0x344e1d6a, 0xce038f4e, 0x6a1fd872, 0x94ca3cd6, 0xa7af407a, 0x67a4a75e, 0x258d7582, 0x667deee6, 0x571f978a, 0x8e55336e, 0xe31ec692, 0x59bd94f6, 0x6c18229a, };
+	unsigned int b[16] = {0x36225509, 0x5debd89d, 0xc238ba71, 0x7b4a6e85, 0x3616a8d9, 0xc09b5d6d, 0xb072c041, 0x57a74555, 0x7bc7a0a9, 0x833ac63d, 0x0cd3ea11, 0x25a68025, 0x911a3c79, 0xd73f130d, 0x0d6137e1, 0x8cdd1ef5, };
+	unsigned int c[16] = {0xed469635, 0x821116c5, 0x3dc0c455, 0xb903aee5, 0x97ece675, 0xa9847b05, 0xe4577c95, 0x5007fb25, 0xebdd06b5, 0xa252af45, 0x59aa04d5, 0x31791765, 0xfd3af6f5, 0x0bdfb385, 0x4c5c5d15, 0xdf3b03a5, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] - b[i] != c[i])
 			return i;
@@ -85,9 +85,9 @@ int testsubu()
 int testmulu()
 {
 	int i;
-	unsigned int a[16] = {0xc8fb2a4d, 0xb9e89321, 0x94f4fe35, 0xb2451f89, 0xb9b5eb1d, 0xe07094f1, 0xa4be9105, 0x7c1d9359, 0x27938fed, 0xa242bac1, 0xde3d87d5, 0xc39aab29, 0x25c918bd, 0xa3240491, 0xa2c6e2a5, 0xe4a166f9, };
-	unsigned int b[16] = {0xdb5893dc, 0x52e4a960, 0x4f6cb824, 0xa452a428, 0xe6cf916c, 0x0537e3f0, 0x637f3fb4, 0x20fc88b8, 0x6b6de2fc, 0x033cb280, 0x55019b44, 0xcc488148, 0x4394888c, 0xb5a41510, 0x93f4cad4, 0x66878dd8, };
-	unsigned int c[16] = {0x5a9a912c, 0xdbbbf560, 0xa285d774, 0x00e2b168, 0x8d5d9d3c, 0xf26454f0, 0x9c293284, 0x17252ff8, 0x9139e74c, 0x8f739280, 0x8a6b0b94, 0xc347cc88, 0x4361ef5c, 0x98842e10, 0x7fcde2a4, 0x51350718, };
+	unsigned int a[16] = {0x2368eb3e, 0xdffcef62, 0xfff97ec6, 0x344e1d6a, 0xce038f4e, 0x6a1fd872, 0x94ca3cd6, 0xa7af407a, 0x67a4a75e, 0x258d7582, 0x667deee6, 0x571f978a, 0x8e55336e, 0xe31ec692, 0x59bd94f6, 0x6c18229a, };
+	unsigned int b[16] = {0x36225509, 0x5debd89d, 0xc238ba71, 0x7b4a6e85, 0x3616a8d9, 0xc09b5d6d, 0xb072c041, 0x57a74555, 0x7bc7a0a9, 0x833ac63d, 0x0cd3ea11, 0x25a68025, 0x911a3c79, 0xd73f130d, 0x0d6137e1, 0x8cdd1ef5, };
+	unsigned int c[16] = {0x6707db2e, 0x210f7f1a, 0x0a8cd166, 0x2bdcd412, 0xbbc3a91e, 0x4e36928a, 0xac45f256, 0x6f274a82, 0x985f3d0e, 0x810b8bfa, 0x9a4d1946, 0x98d1e6f2, 0xc57f16fe, 0x4d3aeb6a, 0x89d6c636, 0x5e192962, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] * b[i] != c[i])
 			return i;
@@ -97,9 +97,9 @@ int testmulu()
 int testdivu()
 {
 	int i;
-	unsigned int a[16] = {0xc8fb2a4d, 0xb9e89321, 0x94f4fe35, 0xb2451f89, 0xb9b5eb1d, 0xe07094f1, 0xa4be9105, 0x7c1d9359, 0x27938fed, 0xa242bac1, 0xde3d87d5, 0xc39aab29, 0x25c918bd, 0xa3240491, 0xa2c6e2a5, 0xe4a166f9, };
-	unsigned int b[16] = {0xdb5893dc, 0x52e4a960, 0x4f6cb824, 0xa452a428, 0xe6cf916c, 0x0537e3f0, 0x637f3fb4, 0x20fc88b8, 0x6b6de2fc, 0x033cb280, 0x55019b44, 0xcc488148, 0x4394888c, 0xb5a41510, 0x93f4cad4, 0x66878dd8, };
-	unsigned int c[16] = {0x00000000, 0x00000002, 0x00000001, 0x00000001, 0x00000000, 0x0000002b, 0x00000001, 0x00000003, 0x00000000, 0x00000032, 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002, };
+	unsigned int a[16] = {0x2368eb3e, 0xdffcef62, 0xfff97ec6, 0x344e1d6a, 0xce038f4e, 0x6a1fd872, 0x94ca3cd6, 0xa7af407a, 0x67a4a75e, 0x258d7582, 0x667deee6, 0x571f978a, 0x8e55336e, 0xe31ec692, 0x59bd94f6, 0x6c18229a, };
+	unsigned int b[16] = {0x36225509, 0x5debd89d, 0xc238ba71, 0x7b4a6e85, 0x3616a8d9, 0xc09b5d6d, 0xb072c041, 0x57a74555, 0x7bc7a0a9, 0x833ac63d, 0x0cd3ea11, 0x25a68025, 0x911a3c79, 0xd73f130d, 0x0d6137e1, 0x8cdd1ef5, };
+	unsigned int c[16] = {0x00000000, 0x00000002, 0x00000001, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000007, 0x00000002, 0x00000000, 0x00000001, 0x00000006, 0x00000000, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] / b[i] != c[i])
 			return i;
@@ -109,9 +109,9 @@ int testdivu()
 int testmodu()
 {
 	int i;
-	unsigned int a[16] = {0xc8fb2a4d, 0xb9e89321, 0x94f4fe35, 0xb2451f89, 0xb9b5eb1d, 0xe07094f1, 0xa4be9105, 0x7c1d9359, 0x27938fed, 0xa242bac1, 0xde3d87d5, 0xc39aab29, 0x25c918bd, 0xa3240491, 0xa2c6e2a5, 0xe4a166f9, };
-	unsigned int b[16] = {0xdb5893dc, 0x52e4a960, 0x4f6cb824, 0xa452a428, 0xe6cf916c, 0x0537e3f0, 0x637f3fb4, 0x20fc88b8, 0x6b6de2fc, 0x033cb280, 0x55019b44, 0xcc488148, 0x4394888c, 0xb5a41510, 0x93f4cad4, 0x66878dd8, };
-	unsigned int c[16] = {0xc8fb2a4d, 0x141f4061, 0x45884611, 0x0df27b61, 0xb9b5eb1d, 0x000d4ba1, 0x413f5151, 0x1927f931, 0x27938fed, 0x0067ddc1, 0x343a514d, 0xc39aab29, 0x25c918bd, 0xa3240491, 0x0ed217d1, 0x17924b49, };
+	unsigned int a[16] = {0x2368eb3e, 0xdffcef62, 0xfff97ec6, 0x344e1d6a, 0xce038f4e, 0x6a1fd872, 0x94ca3cd6, 0xa7af407a, 0x67a4a75e, 0x258d7582, 0x667deee6, 0x571f978a, 0x8e55336e, 0xe31ec692, 0x59bd94f6, 0x6c18229a, };
+	unsigned int b[16] = {0x36225509, 0x5debd89d, 0xc238ba71, 0x7b4a6e85, 0x3616a8d9, 0xc09b5d6d, 0xb072c041, 0x57a74555, 0x7bc7a0a9, 0x833ac63d, 0x0cd3ea11, 0x25a68025, 0x911a3c79, 0xd73f130d, 0x0d6137e1, 0x8cdd1ef5, };
+	unsigned int c[16] = {0x2368eb3e, 0x24253e28, 0x3dc0c455, 0x344e1d6a, 0x2bbf94c3, 0x6a1fd872, 0x94ca3cd6, 0x5007fb25, 0x67a4a75e, 0x258d7582, 0x0cb2886f, 0x0bd29740, 0x8e55336e, 0x0bdfb385, 0x097645b0, 0x6c18229a, };
 	for (i = 0; i < 16; i++) {
 		if (a[i] % b[i] != c[i])
 			return i;

examples/hdl4se_riscv/verilog/axi/riscv_core_with_axi_master.v

@@ -30,7 +30,7 @@ module riscv_core_with_axi_master (
 		input wire				wARReady,
 
 		//ReadData
-		output wire				wRReady
+		output wire				wRReady,
 		input wire				wRValid,
 		input wire [31 : 0]		bRData,
 		input wire [1 : 0]		bRResp
@@ -54,6 +54,7 @@ module riscv_core_with_axi_master (
 
     wire wWrite, wRead, wReadReady, wWriteReady;
     wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
+	wire [3:0]  bWriteMask;
 
 	wire [4:0]  regno;
     wire [3:0]  regena;
@@ -66,8 +67,34 @@ module riscv_core_with_axi_master (
     wire        regwren2;
     wire [31:0] regrddata2;
 
+	reg [31:0] lastreadaddr;
+	reg		   lastread;
+
+	always @(posedge wClk)
+	if (~nwReset) begin
+		lastreadaddr <= 0;
+		lastread <= 0;
+	end else begin
+		lastreadaddr <= bReadAddr;
+		lastread <= wRead;
+	end
+
+	assign bReadData = 
+            ((lastreadaddr & 32'hffffff00) == 32'hf0000000) ? bRData : (
+            ((lastreadaddr & 32'hff000000) == 32'h00000000) ? bReadDataRam : (32'h0)
+            );
+
+	assign wReadReady = ((lastreadaddr & 32'hf0000000) == 32'hf0000000) ? wRValid : (
+						((lastreadaddr & 32'hfff00000) == 32'h00000000) ? lastread : (0)
+						);
+
+
+    wire [29:0] ramaddr;
+    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];
+
     regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
     regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
+	ram4kB     ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
 	riscv_core core(wClk, nwReset, 
                 wWrite, bWriteAddr, bWriteData, bWriteMask, wWriteReady, 
                 wRead, bReadAddr, bReadData, wReadReady,
@@ -89,9 +116,7 @@ module riscv_core_with_axi_master (
 		awvalid <= 1'b0;
 	end
 
-	assign wWriteReady = (wWrite || awvalid) && wAWReady;
-
-	always @(*)
+	always @(wWrite or awvalid or bWriteAddr or awaddr)
 	begin
 		axi_awvalid = wWrite ? 1'b1 : awvalid;
 		axi_awaddr = wWrite ? bWriteAddr : awaddr;
@@ -101,7 +126,7 @@ module riscv_core_with_axi_master (
 	reg [31:0] wdata;
 	reg [3:0]  wstrb;
 	reg		   wvalid;
-	always @(wClk)
+	always @(posedge wClk)
 	begin
 		if (~nwReset) begin
 			wvalid <= 1'b0;
@@ -114,7 +139,9 @@ module riscv_core_with_axi_master (
 		end
 	end
 
-	always @(*)
+	assign wWriteReady = ((wWrite || wvalid) && wWReady) || ((bWriteAddr & 32'hfff00000) == 32'h00000000);
+
+	always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
 	begin
 		axi_wvalid = wWrite ? 1'b1 : wvalid;
 		axi_wdata = wWrite ? bWriteData : wdata;
@@ -134,14 +161,10 @@ module riscv_core_with_axi_master (
 		arvalid <= 1'b0;
 	end
 
-	assign wReadyReady = (wRead || arvalid) && wARReady;
-
-	always @(*)
+	always @(wRead or arvalid or bReadAddr or araddr)
 	begin
 		axi_arvalid = wRead ? 1'b1 : arvalid;
 		axi_araddr = wRead ? bReadAddr : araddr;
 	end
 
-	assign bReadData = bRData;
-
 endmodule

examples/hdl4se_riscv/verilog/axi/riscv_core_with_axi_master.v.bak

+
+`timescale 1 ns / 1 ps
+
+module riscv_core_with_axi_master (
+	    // clock and reset
+		input wire				wClk,
+		input wire				nwReset,
+
+		// Write Address
+		output wire				wAWValid,
+		output wire [31 : 0]	bAWAddr,
+		output wire [2 : 0]		bAWProt,
+		input wire				wAWReady,
+
+		// Write Data 
+		output wire				wWValid,
+		output wire [31 : 0]	bWData,
+		output wire [3 : 0]		bWStrb,
+		input wire				wWReady,
+
+		// Write Response
+		output wire				wBReady,
+		input wire [1 : 0]		bBResp,
+		input wire				wBValid,
+
+		// ReadAddr
+		output wire				wARValid,
+		output wire [31 : 0]	bARAddr,
+		output wire [2 : 0]		bARProt,
+		input wire				wARReady,
+
+		//ReadData
+		output wire				wRReady,
+		input wire				wRValid,
+		input wire [31 : 0]		bRData,
+		input wire [1 : 0]		bRResp
+);
+
+	reg			axi_awvalid;	assign wAWValid = axi_awvalid;
+	reg [31:0] 	axi_awaddr;		assign bAWAddr = axi_awaddr;
+								assign bAWProt = 3'b000;
+
+	reg			axi_wvalid;		assign wWValid = axi_wvalid;
+	reg [31:0] 	axi_wdata;		assign bWData = axi_wdata;
+	reg [3:0]   axi_wstrb;		assign bWStrb = axi_wstrb;
+
+								assign wBReady = 1'b1;
+
+	reg			axi_arvalid;	assign wARValid = axi_arvalid;
+	reg [31:0] 	axi_araddr;		assign bARAddr = axi_araddr;
+								assign bARProt = 3'b001;
+
+								assign wRReady = 1'b1;
+
+    wire wWrite, wRead, wReadReady, wWriteReady;
+    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
+
+	wire [4:0]  regno;
+    wire [3:0]  regena;
+    wire [31:0] regwrdata;
+    wire        regwren;
+    wire [31:0] regrddata;
+    wire [4:0]  regno2;
+    wire [3:0]  regena2;
+    wire [31:0] regwrdata2;
+    wire        regwren2;
+    wire [31:0] regrddata2;
+
+	reg [31:0] lastreadaddr;
+	reg		   lastread;
+
+	always @(posedge wClk)
+	if (~nwReset) begin
+		lastreadaddr <= 0;
+		lastread <= 0;
+	end else begin
+		lastreadaddr <= bReadAddr;
+		lastread <= wRead;
+	end
+
+	assign bReadData = 
+            ((lastreadaddr & 32'hffffff00) == 32'hf0000000) ? bRData : (
+            ((lastreadaddr & 32'hff000000) == 32'h00000000) ? bReadDataRam : (32'h0)
+            );
+
+	assign wReadReady = ((lastreadaddr & 32'hf0000000) == 32'hf0000000) ? bRData : (
+						((lastreadaddr & 32'hfff00000) == 32'h00000000) ? lastread : (0)
+						);
+
+
+    wire [29:0] ramaddr;
+    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];
+
+    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
+    regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
+	ram4kB     ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
+	riscv_core core(wClk, nwReset, 
+                wWrite, bWriteAddr, bWriteData, bWriteMask, wWriteReady, 
+                wRead, bReadAddr, bReadData, wReadReady,
+                regno, regena, regwrdata, regwren, regrddata,
+                regno2, regena2, regwrdata2, regwren2, regrddata2
+                );
+
+
+	//Write Address
+	reg [31:0] awaddr;
+	reg awvalid;
+	always @(posedge wClk)
+	if (~nwReset) begin
+		awvalid <= 1'b0;
+	end else if (wWrite) begin
+		awaddr <= bWriteAddr;
+		awvalid <= 1'b1;
+	end else if (wAWReady) begin
+		awvalid <= 1'b0;
+	end
+
+	always @(*)
+	begin
+		axi_awvalid = wWrite ? 1'b1 : awvalid;
+		axi_awaddr = wWrite ? bWriteAddr : awaddr;
+	end
+
+	/* Write Data */
+	reg [31:0] wdata;
+	reg [3:0]  wstrb;
+	reg		   wvalid;
+	always @(wClk)
+	begin
+		if (~nwReset) begin
+			wvalid <= 1'b0;
+		end if (wWrite) begin
+			wdata <= bWriteData;
+			wstrb <= ~bWriteMask;
+			wvalid <= 1'b1;
+		end if (wWReady) begin
+			wvalid <= 1'b0;
+		end
+	end
+
+	assign wWriteReady = ((wWrite || wvalid) && wWReady) || ((bWriteAddr & 32'hfff00000) == 32'h00000000);
+
+	always @(*)
+	begin
+		axi_wvalid = wWrite ? 1'b1 : wvalid;
+		axi_wdata = wWrite ? bWriteData : wdata;
+		axi_wstrb = wWrite ? ~bWriteMask : wstrb;
+	end
+
+	//Read Address
+	reg [31:0] araddr;
+	reg arvalid;
+	always @(posedge wClk)
+	if (~nwReset) begin
+		arvalid <= 1'b0;
+	end else if (wRead) begin
+		araddr <= bReadAddr;
+		arvalid <= 1'b1;
+	end else if (wARReady) begin
+		arvalid <= 1'b0;
+	end
+
+	always @(*)
+	begin
+		axi_arvalid = wRead ? 1'b1 : arvalid;
+		axi_araddr = wRead ? bReadAddr : araddr;
+	end
+
+endmodule