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examples/hdl4se_riscv/test_code/console.c
浏览文件 @ b16b62ed
#define UARTADDRESS (unsigned int *)0xf0000100
#define UARTADDRESS (unsigned int *)0xf0001000
#define REFFREQ 50000000
static int _canputchar()
......
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @ b16b62ed
@00000000
37 11 00 00 EF 00 10 24 6F F0 9F FF
37 11 00 00 EF 00 10 23 6F F0 9F FF
@0000000C
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 07 00 F0
93 87 07 10 23 26 F4 FE 83 27 C4 FE 93 87 87 00
83 A7 07 00 23 24 F4 FE 83 27 84 FE 93 F7 87 00
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 17 00 F0
23 26 F4 FE 83 27 C4 FE 93 87 87 00 83 A7 07 00
23 24 F4 FE 83 27 84 FE 93 F7 87 00 93 B7 17 00
93 F7 F7 0F 13 85 07 00 03 24 C1 01 13 01 01 02
67 80 00 00
@00000050
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 17 00 F0
23 26 F4 FE 83 27 C4 FE 93 87 87 00 83 A7 07 00
23 24 F4 FE 83 27 84 FE 93 F7 17 00 93 87 F7 FF
93 B7 17 00 93 F7 F7 0F 13 85 07 00 03 24 C1 01
13 01 01 02 67 80 00 00
@00000054
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 07 00 F0
93 87 07 10 23 26 F4 FE 83 27 C4 FE 93 87 87 00
83 A7 07 00 23 24 F4 FE 83 27 84 FE 93 F7 17 00
93 87 F7 FF 93 B7 17 00 93 F7 F7 0F 13 85 07 00
03 24 C1 01 13 01 01 02 67 80 00 00
@000000A0
@00000098
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC B7 07 00 F0 93 87 07 10 23 26 F4 FE
EF F0 DF F4 93 07 05 00 63 8E 07 00 83 27 C4 FE
93 87 47 00 03 27 C4 FD 23 A0 E7 00 93 07 00 00
6F 00 80 00 93 07 F0 FF 13 85 07 00 83 20 C1 02
03 24 81 02 13 01 01 03 67 80 00 00
@000000FC
23 2E A4 FC B7 17 00 F0 23 26 F4 FE EF F0 9F F5
93 07 05 00 63 8E 07 00 83 27 C4 FE 93 87 47 00
03 27 C4 FD 23 A0 E7 00 93 07 00 00 6F 00 80 00
93 07 F0 FF 13 85 07 00 83 20 C1 02 03 24 81 02
13 01 01 03 67 80 00 00
@000000F0
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
B7 07 00 F0 93 87 07 10 23 26 F4 FE EF F0 DF F3
93 07 05 00 63 88 07 00 83 27 C4 FE 83 A7 07 00
6F 00 80 00 93 07 F0 FF 13 85 07 00 83 20 C1 01
03 24 81 01 13 01 01 02 67 80 00 00
@00000148
B7 17 00 F0 23 26 F4 FE EF F0 9F F4 93 07 05 00
63 88 07 00 83 27 C4 FE 83 A7 07 00 6F 00 80 00
93 07 F0 FF 13 85 07 00 83 20 C1 01 03 24 81 01
13 01 01 02 67 80 00 00
@00000138
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
23 26 A4 FE 6F 00 00 03 13 00 00 00 83 27 C4 FE
83 C7 07 00 13 85 07 00 EF F0 1F F3 13 07 05 00
83 C7 07 00 13 85 07 00 EF F0 9F F3 13 07 05 00
93 07 F0 FF E3 04 F7 FE 83 27 C4 FE 93 87 17 00
23 26 F4 FE 83 27 C4 FE 83 C7 07 00 E3 96 07 FC
93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01
13 01 01 02 67 80 00 00
@000001B0
@000001A0
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC 23 2C B4 FC 23 26 04 FE 03 27 84 FD
93 07 10 00 63 C6 E7 00 93 07 00 00 6F 00 80 09
EF F0 DF F1 23 24 A4 FE 03 27 84 FE 93 07 F0 FF
EF F0 1F F2 23 24 A4 FE 03 27 84 FE 93 07 F0 FF
E3 08 F7 FE 83 27 C4 FE 13 87 17 00 23 26 E4 FE
13 87 07 00 83 27 C4 FD B3 87 E7 00 03 27 84 FE
13 77 F7 0F 23 80 E7 00 13 00 00 00 03 25 84 FE
EF F0 1F E8 13 07 05 00 93 07 F0 FF E3 08 F7 FE
EF F0 9F E8 13 07 05 00 93 07 F0 FF E3 08 F7 FE
83 27 84 FD 93 87 F7 FF 03 27 C4 FE 63 50 F7 02
03 27 84 FE 93 07 A0 00 63 0C F7 00 03 27 84 FE
93 07 D0 00 63 06 F7 00 6F F0 9F F8 13 00 00 00
83 27 C4 FE 03 27 C4 FD B3 07 F7 00 23 80 07 00
83 27 C4 FE 13 85 07 00 83 20 C1 02 03 24 81 02
13 01 01 03 67 80 00 00
@00000288
@00000278
13 01 01 FC 23 2E 81 02 13 04 01 04 23 26 A4 FC
23 24 B4 FC 23 24 04 FE 23 22 04 FE 83 27 84 FC
63 DA 07 00 83 27 84 FC B3 07 F0 40 23 24 F4 FC
......@@ -74,7 +74,7 @@ A3 0F F4 FC 83 27 04 FE 03 27 C4 FC 33 07 F7 00
83 27 84 FE 03 27 C4 FC B3 07 F7 00 23 80 07 00
83 27 84 FE 13 85 07 00 03 24 C1 03 13 01 01 04
67 80 00 00
@0000040C
@000003FC
13 01 01 FB 23 26 81 04 13 04 01 05 23 26 A4 FC
23 20 B4 FC 23 22 C4 FC 23 24 D4 FC 93 07 07 00
A3 0F F4 FA 23 24 04 FE 6F 00 00 09 83 27 04 FC
......@@ -102,7 +102,7 @@ B3 07 F7 00 93 D7 17 40 13 87 07 00 83 27 C4 FE
E3 C0 E7 F8 83 27 84 FE 03 27 C4 FC B3 07 F7 00
23 80 07 00 83 27 84 FE 13 85 07 00 03 24 C1 04
13 01 01 05 67 80 00 00
@000005B4
@000005A4
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 93 07 10 00
23 22 F4 FE 6F 00 C0 08 83 27 C4 FD 83 C7 07 00
......@@ -119,7 +119,7 @@ E3 C0 E7 F8 83 27 84 FE 03 27 C4 FC B3 07 F7 00
23 24 F4 FE 83 27 84 FD 63 88 07 00 83 27 84 FD
03 27 C4 FD 23 A0 E7 00 83 27 84 FE 13 85 07 00
03 24 C1 02 13 01 01 03 67 80 00 00
@000006B0
@000006A0
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 6F 00 00 0E
83 27 C4 FD 83 C7 07 00 23 22 F4 FE 03 27 44 FE
......@@ -140,27 +140,27 @@ B3 07 F7 00 93 87 97 FC 23 24 F4 FE 6F 00 40 01
83 27 84 FD 63 88 07 00 83 27 84 FD 03 27 C4 FD
23 A0 E7 00 83 27 84 FE 13 85 07 00 03 24 C1 02
13 01 01 03 67 80 00 00
@000007E8
@000007D8
13 01 01 FB 23 26 11 04 23 24 81 04 23 22 21 05
23 20 31 05 23 2E 41 03 23 2C 51 03 13 04 01 05
B7 17 00 00 83 A7 87 E8 93 F7 07 FF 23 2A F4 FC
B7 17 00 00 83 A7 07 E7 93 F7 07 FF 23 2A F4 FC
23 2C 04 FC 6F 00 C0 1B 83 27 44 FD 13 89 07 00
93 09 00 00 93 07 C4 FB 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 9F BC
93 07 C4 FB 13 85 07 00 EF F0 9F 8F B7 17 00 00
13 85 07 E4 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
13 85 87 E2 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
83 27 44 FD 23 26 F4 FC 03 27 C4 FD 83 27 44 FD
33 07 F7 00 B7 17 00 00 83 A7 87 E8 63 7A F7 00
B7 17 00 00 13 85 47 E4 EF F0 9F 8B 6F 00 00 05
33 07 F7 00 B7 17 00 00 83 A7 07 E7 63 7A F7 00
B7 17 00 00 13 85 C7 E2 EF F0 9F 8B 6F 00 00 05
83 27 C4 FD 03 27 C4 FC B3 07 F7 00 83 C7 07 00
13 8A 07 00 93 0A 00 00 93 07 C4 FB 13 07 00 03
93 06 20 00 93 05 0A 00 13 86 0A 00 13 85 07 00
EF F0 5F B4 93 07 C4 FB 13 85 07 00 EF F0 5F 87
B7 17 00 00 13 85 87 E4 EF F0 9F 86 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 C7 E4
B7 17 00 00 13 85 07 E3 EF F0 9F 86 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 47 E3
EF F0 1F 85 83 27 C4 FD 93 87 17 00 23 2E F4 FC
03 27 C4 FD 93 07 F0 00 E3 DC E7 F4 B7 17 00 00
13 85 07 E5 EF F0 DF 82 23 2E 04 FC 6F 00 80 07
13 85 87 E3 EF F0 DF 82 23 2E 04 FC 6F 00 80 07
83 27 44 FD 23 28 F4 FC 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 03 C7 07 00 93 07 F0 01 63 FA E7 02
83 27 C4 FD 03 27 04 FD B3 07 F7 00 03 C7 07 00
......@@ -169,87 +169,87 @@ B3 07 F7 00 83 C7 07 00 23 0E F4 FA 6F 00 C0 00
93 07 E0 02 23 0E F4 FA A3 0E 04 FA 93 07 C4 FB
13 85 07 00 EF F0 CF FB 83 27 C4 FD 93 87 17 00
23 2E F4 FC 03 27 C4 FD 93 07 F0 00 E3 D2 E7 F8
B7 17 00 00 13 85 47 E5 EF F0 8F F9 83 27 44 FD
B7 17 00 00 13 85 C7 E3 EF F0 8F F9 83 27 44 FD
93 87 07 01 23 2A F4 FC 83 27 44 FD 93 F7 F7 0F
63 80 07 02 83 27 84 FD 93 87 17 00 23 2C F4 FC
03 27 84 FD 93 07 F0 00 E3 D0 E7 E4 6F 00 80 00
13 00 00 00 B7 17 00 00 13 85 87 E5 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A4 E7 E8 13 00 00 00
13 00 00 00 B7 17 00 00 13 85 07 E4 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A8 E7 E6 13 00 00 00
83 20 C1 04 03 24 81 04 03 29 41 04 83 29 01 04
03 2A C1 03 83 2A 81 03 13 01 01 05 67 80 00 00
@00000A28
@00000A18
13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00
03 24 C1 00 13 01 01 01 67 80 00 00
@00000A44
@00000A34
13 01 01 F7 23 26 11 08 23 24 81 08 23 22 21 09
23 20 31 09 23 2E 41 07 23 2C 51 07 13 04 01 09
23 2E A4 F6 23 2C B4 F6 93 07 10 00 23 2E F4 FC
B7 07 00 F0 93 87 07 10 23 2A F4 FC 83 27 44 FD
93 87 C7 00 13 07 20 1B 23 A0 E7 00 EF F0 CF D7
93 07 05 00 63 88 07 00 B7 17 00 00 13 85 C7 E5
EF F0 4F EA 83 27 C4 FD 93 87 17 00 23 2E F4 FC
B7 07 00 F0 93 87 47 00 03 27 C4 FD 23 A0 E7 00
EF F0 0F D9 93 07 05 00 63 86 07 04 93 07 44 F8
93 05 70 02 13 85 07 00 EF F0 4F ED 13 00 00 00
B7 17 00 00 13 85 07 E6 EF F0 CF E5 93 07 44 F8
13 85 07 00 EF F0 0F E5 B7 17 00 00 13 85 87 E5
EF F0 4F E4 03 47 44 F8 93 07 20 06 63 1E F7 06
6F 00 40 02 83 27 C4 FD 93 87 17 00 23 2E F4 FC
B7 07 00 F0 93 87 47 00 03 27 C4 FD 23 A0 E7 00
6F F0 1F F9 93 07 44 F8 93 87 27 00 93 05 00 00
13 85 07 00 EF F0 DF A6 23 2C A4 FA 83 27 84 FB
63 58 F0 02 B7 07 00 F0 93 87 07 10 23 2A F4 FA
B7 F7 FA 02 13 87 07 08 83 27 84 FB 33 47 F7 02
83 27 44 FB 93 87 C7 00 23 A0 E7 00 6F 00 C0 2A
EF F0 5F EA 6F 00 40 2A 03 47 44 F8 93 07 40 06
63 1C F7 02 93 07 44 F8 93 87 27 00 93 05 00 00
13 85 07 00 EF F0 9F B0 23 2E A4 FA 83 27 C4 FB
63 58 F0 00 03 27 C4 FB B7 17 00 00 23 A4 E7 E8
EF F0 5F C2 6F 00 40 26 03 47 44 F8 93 07 70 07
63 1C F7 0A 93 07 44 F8 93 87 27 00 13 07 04 FB
93 05 07 00 13 85 07 00 EF F0 5F AC 23 24 A4 FC
B7 17 00 F0 23 2A F4 FC 83 27 44 FD 93 87 C7 00
13 07 20 1B 23 A0 E7 00 EF F0 0F D9 93 07 05 00
63 88 07 00 B7 17 00 00 13 85 47 E4 EF F0 8F EA
83 27 C4 FD 93 87 17 00 23 2E F4 FC B7 07 00 F0
93 87 47 00 03 27 C4 FD 23 A0 E7 00 EF F0 0F DA
93 07 05 00 63 86 07 04 93 07 44 F8 93 05 70 02
13 85 07 00 EF F0 8F ED 13 00 00 00 B7 17 00 00
13 85 87 E4 EF F0 0F E6 93 07 44 F8 13 85 07 00
EF F0 4F E5 B7 17 00 00 13 85 07 E4 EF F0 8F E4
03 47 44 F8 93 07 20 06 63 1C F7 06 6F 00 40 02
83 27 C4 FD 93 87 17 00 23 2E F4 FC B7 07 00 F0
93 87 47 00 03 27 C4 FD 23 A0 E7 00 6F F0 1F F9
93 07 44 F8 93 87 27 00 93 05 00 00 13 85 07 00
EF F0 1F A7 23 2C A4 FA 83 27 84 FB 63 56 F0 02
B7 17 00 F0 23 2A F4 FA B7 F7 FA 02 13 87 07 08
83 27 84 FB 33 47 F7 02 83 27 44 FB 93 87 C7 00
23 A0 E7 00 6F 00 C0 2A EF F0 DF EA 6F 00 40 2A
03 47 44 F8 93 07 40 06 63 1C F7 02 93 07 44 F8
93 87 27 00 93 05 00 00 13 85 07 00 EF F0 1F B1
23 2E A4 FA 83 27 C4 FB 63 58 F0 00 03 27 C4 FB
B7 17 00 00 23 A8 E7 E6 EF F0 DF C2 6F 00 40 26
03 47 44 F8 93 07 70 07 63 1C F7 0A 93 07 44 F8
93 87 27 00 13 07 04 FB 93 05 07 00 13 85 07 00
EF F0 DF AC 23 24 A4 FC 83 27 04 FB 13 07 04 FB
93 05 07 00 13 85 07 00 EF F0 5F AB 23 22 A4 FC
83 27 04 FB 13 07 04 FB 93 05 07 00 13 85 07 00
EF F0 DF AA 23 22 A4 FC 83 27 04 FB 13 07 04 FB
93 05 07 00 13 85 07 00 EF F0 5F A9 23 20 A4 FC
03 27 04 FC 93 07 10 00 63 1C F7 00 83 27 84 FC
03 27 44 FC 13 77 F7 0F 23 80 E7 00 6F 00 C0 1E
03 27 04 FC 93 07 20 00 63 1E F7 00 83 27 84 FC
03 27 44 FC 13 17 07 01 13 57 07 41 23 90 E7 00
6F 00 80 1C 03 27 04 FC 93 07 40 00 63 1A F7 00
83 27 84 FC 03 27 44 FC 23 A0 E7 00 6F 00 C0 1A
EF F0 5F DA 6F 00 40 1A 03 47 44 F8 93 07 20 07
63 1A F7 18 23 2C 04 FC 93 07 44 F8 93 87 27 00
13 07 C4 FA 93 05 07 00 13 85 07 00 EF F0 1F A0
93 07 05 00 23 28 F4 FC 83 27 C4 FA 13 07 C4 FA
93 05 07 00 13 85 07 00 EF F0 5F 9E 23 26 A4 FC
03 27 C4 FC 93 07 10 00 63 10 F7 02 83 27 04 FD
83 C7 07 00 23 2C F4 FC B7 17 00 00 13 85 47 E6
EF F0 4F C5 6F 00 80 05 03 27 C4 FC 93 07 20 00
63 10 F7 02 83 27 04 FD 83 D7 07 00 23 2C F4 FC
B7 17 00 00 13 85 C7 E6 EF F0 CF C2 6F 00 00 03
03 27 C4 FC 93 07 40 00 63 10 F7 02 83 27 04 FD
83 A7 07 00 23 2C F4 FC B7 17 00 00 13 85 47 E7
EF F0 4F C0 6F 00 80 00 EF F0 DF CD 03 27 C4 FC
93 07 10 00 63 0E F7 00 03 27 C4 FC 93 07 20 00
63 08 F7 00 03 27 C4 FC 93 07 40 00 63 1E F7 0A
83 27 04 FD 13 89 07 00 93 09 00 00 93 07 44 F8
13 07 00 03 93 06 80 00 93 05 09 00 13 86 09 00
13 85 07 00 EF F0 4F E7 93 07 44 F8 13 85 07 00
EF F0 4F BA B7 17 00 00 13 85 C7 E7 EF F0 8F B9
03 27 84 FD 93 07 44 F8 93 05 07 00 13 85 07 00
EF F0 4F CC 93 07 44 F8 13 85 07 00 EF F0 8F B7
B7 17 00 00 13 85 07 E8 EF F0 CF B6 83 27 84 FD
13 8A 07 00 93 0A 00 00 83 27 C4 FC 93 96 17 00
93 07 44 F8 13 07 00 03 93 05 0A 00 13 86 0A 00
13 85 07 00 EF F0 4F E0 93 07 44 F8 13 85 07 00
EF F0 4F B3 B7 17 00 00 13 85 47 E8 EF F0 8F B2
6F 00 80 00 EF F0 1F C0 13 00 00 00 EF F0 CF 9D
93 07 05 00 E3 8C 07 FE 6F F0 5F C5
@00000E40
EF F0 DF A9 23 20 A4 FC 03 27 04 FC 93 07 10 00
63 1C F7 00 83 27 84 FC 03 27 44 FC 13 77 F7 0F
23 80 E7 00 6F 00 C0 1E 03 27 04 FC 93 07 20 00
63 1E F7 00 83 27 84 FC 03 27 44 FC 13 17 07 01
13 57 07 41 23 90 E7 00 6F 00 80 1C 03 27 04 FC
93 07 40 00 63 1A F7 00 83 27 84 FC 03 27 44 FC
23 A0 E7 00 6F 00 C0 1A EF F0 DF DA 6F 00 40 1A
03 47 44 F8 93 07 20 07 63 1A F7 18 23 2C 04 FC
93 07 44 F8 93 87 27 00 13 07 C4 FA 93 05 07 00
13 85 07 00 EF F0 9F A0 93 07 05 00 23 28 F4 FC
83 27 C4 FA 13 07 C4 FA 93 05 07 00 13 85 07 00
EF F0 DF 9E 23 26 A4 FC 03 27 C4 FC 93 07 10 00
63 10 F7 02 83 27 04 FD 83 C7 07 00 23 2C F4 FC
B7 17 00 00 13 85 C7 E4 EF F0 CF C5 6F 00 80 05
03 27 C4 FC 93 07 20 00 63 10 F7 02 83 27 04 FD
83 D7 07 00 23 2C F4 FC B7 17 00 00 13 85 47 E5
EF F0 4F C3 6F 00 00 03 03 27 C4 FC 93 07 40 00
63 10 F7 02 83 27 04 FD 83 A7 07 00 23 2C F4 FC
B7 17 00 00 13 85 C7 E5 EF F0 CF C0 6F 00 80 00
EF F0 5F CE 03 27 C4 FC 93 07 10 00 63 0E F7 00
03 27 C4 FC 93 07 20 00 63 08 F7 00 03 27 C4 FC
93 07 40 00 63 1E F7 0A 83 27 04 FD 13 89 07 00
93 09 00 00 93 07 44 F8 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 CF E7
93 07 44 F8 13 85 07 00 EF F0 CF BA B7 17 00 00
13 85 47 E6 EF F0 0F BA 03 27 84 FD 93 07 44 F8
93 05 07 00 13 85 07 00 EF F0 CF CC 93 07 44 F8
13 85 07 00 EF F0 0F B8 B7 17 00 00 13 85 87 E6
EF F0 4F B7 83 27 84 FD 13 8A 07 00 93 0A 00 00
83 27 C4 FC 93 96 17 00 93 07 44 F8 13 07 00 03
93 05 0A 00 13 86 0A 00 13 85 07 00 EF F0 CF E0
93 07 44 F8 13 85 07 00 EF F0 CF B3 B7 17 00 00
13 85 C7 E6 EF F0 0F B3 6F 00 80 00 EF F0 9F C0
13 00 00 00 EF F0 4F 9F 93 07 05 00 E3 8C 07 FE
6F F0 9F C5
@00000E28
20 20 00 00 20 20 20 00 20 00 00 00 2D 20 00 00
20 20 7C 00 7C 0A 00 00 0A 0D 00 00 3E 3E 00 00
0A 0D 3A 00 63 68 61 72 20 40 00 00 73 68 6F 72
74 20 40 00 69 6E 74 20 40 00 00 00 20 3D 20 00
28 00 00 00 29 0A 0D 00
@00000E88
@00000E70
01 00 00 00
examples/hdl4se_riscv/test_code/test.coe
浏览文件 @ b16b62ed
memory_initialization_radix = 16;
memory_initialization_vector =
1137,
241000EF,
231000EF,
FF9FF06F,
FE010113,
812E23,
2010413,
F00007B7,
10078793,
F00017B7,
FEF42623,
FEC42783,
878793,
......@@ -24,8 +23,7 @@ FF7F793,
FE010113,
812E23,
2010413,
F00007B7,
10078793,
F00017B7,
FEF42623,
FEC42783,
878793,
......@@ -45,10 +43,9 @@ FD010113,
2812423,
3010413,
FCA42E23,
F00007B7,
10078793,
F00017B7,
FEF42623,
F4DFF0EF,
F59FF0EF,
50793,
78E63,
FEC42783,
......@@ -67,10 +64,9 @@ FE010113,
112E23,
812C23,
2010413,
F00007B7,
10078793,
F00017B7,
FEF42623,
F3DFF0EF,
F49FF0EF,
50793,
78863,
FEC42783,
......@@ -92,7 +88,7 @@ FEA42623,
FEC42783,
7C783,
78513,
F31FF0EF,
F39FF0EF,
50713,
FFF00793,
FEF704E3,
......@@ -120,7 +116,7 @@ FD842703,
E7C663,
793,
980006F,
F1DFF0EF,
F21FF0EF,
FEA42423,
FE842703,
FFF00793,
......@@ -136,7 +132,7 @@ FF77713,
E78023,
13,
FE842503,
E81FF0EF,
E89FF0EF,
50713,
FFF00793,
FEF708E3,
......@@ -515,7 +511,7 @@ FB010113,
3512C23,
5010413,
17B7,
E887A783,
E707A783,
FF07F793,
FCF42A23,
FC042C23,
......@@ -534,7 +530,7 @@ FBC40793,
78513,
8F9FF0EF,
17B7,
E4078513,
E2878513,
8EDFF0EF,
FC042E23,
A40006F,
......@@ -544,10 +540,10 @@ FDC42703,
FD442783,
F70733,
17B7,
E887A783,
E707A783,
F77A63,
17B7,
E4478513,
E2C78513,
8B9FF0EF,
500006F,
FDC42783,
......@@ -567,13 +563,13 @@ FBC40793,
78513,
875FF0EF,
17B7,
E4878513,
E3078513,
869FF0EF,
FDC42703,
700793,
F71863,
17B7,
E4C78513,
E3478513,
851FF0EF,
FDC42783,
178793,
......@@ -582,7 +578,7 @@ FDC42703,
F00793,
F4E7DCE3,
17B7,
E5078513,
E3878513,
82DFF0EF,
FC042E23,
780006F,
......@@ -619,7 +615,7 @@ FDC42703,
F00793,
F8E7D2E3,
17B7,
E5478513,
E3C78513,
F98FF0EF,
FD442783,
1078793,
......@@ -636,11 +632,11 @@ E4E7D0E3,
80006F,
13,
17B7,
E5878513,
E4078513,
F54FF0EF,
17B7,
FD442703,
E8E7A423,
E6E7A823,
13,
4C12083,
4812403,
......@@ -669,19 +665,18 @@ F6A42E23,
F6B42C23,
100793,
FCF42E23,
F00007B7,
10078793,
F00017B7,
FCF42A23,
FD442783,
C78793,
1B200713,
E7A023,
D7CFF0EF,
D90FF0EF,
50793,
78863,
17B7,
E5C78513,
EA4FF0EF,
E4478513,
EA8FF0EF,
FDC42783,
178793,
FCF42E23,
......@@ -689,26 +684,26 @@ F00007B7,
478793,
FDC42703,
E7A023,
D90FF0EF,
DA0FF0EF,
50793,
4078663,
F8440793,
2700593,
78513,
ED4FF0EF,
ED8FF0EF,
13,
17B7,
E6078513,
E5CFF0EF,
E4878513,
E60FF0EF,
F8440793,
78513,
E50FF0EF,
E54FF0EF,
17B7,
E5878513,
E44FF0EF,
E4078513,
E48FF0EF,
F8444703,
6200793,
6F71E63,
6F71C63,
240006F,
FDC42783,
178793,
......@@ -722,12 +717,11 @@ F8440793,
278793,
593,
78513,
A6DFF0EF,
A71FF0EF,
FAA42C23,
FB842783,
2F05863,
F00007B7,
10078793,
2F05663,
F00017B7,
FAF42A23,
2FAF7B7,
8078713,
......@@ -737,7 +731,7 @@ FB442783,
C78793,
E7A023,
2AC0006F,
EA5FF0EF,
EADFF0EF,
2A40006F,
F8444703,
6400793,
......@@ -746,14 +740,14 @@ F8440793,
278793,
593,
78513,
B09FF0EF,
B11FF0EF,
FAA42E23,
FBC42783,
F05863,
FBC42703,
17B7,
E8E7A423,
C25FF0EF,
E6E7A823,
C2DFF0EF,
2640006F,
F8444703,
7700793,
......@@ -763,19 +757,19 @@ F8440793,
FB040713,
70593,
78513,
AC5FF0EF,
ACDFF0EF,
FCA42423,
FB042783,
FB040713,
70593,
78513,
AADFF0EF,
AB5FF0EF,
FCA42223,
FB042783,
FB040713,
70593,
78513,
A95FF0EF,
A9DFF0EF,
FCA42023,
FC042703,
100793,
......@@ -801,7 +795,7 @@ FC842783,
FC442703,
E7A023,
1AC0006F,
DA5FF0EF,
DADFF0EF,
1A40006F,
F8444703,
7200793,
......@@ -812,14 +806,14 @@ F8440793,
FAC40713,
70593,
78513,
A01FF0EF,
A09FF0EF,
50793,
FCF42823,
FAC42783,
FAC40713,
70593,
78513,
9E5FF0EF,
9EDFF0EF,
FCA42623,
FCC42703,
100793,
......@@ -828,8 +822,8 @@ FD042783,
7C783,
FCF42C23,
17B7,
E6478513,
C54FF0EF,
E4C78513,
C5CFF0EF,
580006F,
FCC42703,
200793,
......@@ -838,8 +832,8 @@ FD042783,
7D783,
FCF42C23,
17B7,
E6C78513,
C2CFF0EF,
E5478513,
C34FF0EF,
300006F,
FCC42703,
400793,
......@@ -848,10 +842,10 @@ FD042783,
7A783,
FCF42C23,
17B7,
E7478513,
C04FF0EF,
E5C78513,
C0CFF0EF,
80006F,
CDDFF0EF,
CE5FF0EF,
FCC42703,
100793,
F70E63,
......@@ -870,24 +864,24 @@ F8440793,
90593,
98613,
78513,
E74FF0EF,
E7CFF0EF,
F8440793,
78513,
BA4FF0EF,
BACFF0EF,
17B7,
E7C78513,
B98FF0EF,
E6478513,
BA0FF0EF,
FD842703,
F8440793,
70593,
78513,
CC4FF0EF,
CCCFF0EF,
F8440793,
78513,
B78FF0EF,
B80FF0EF,
17B7,
E8078513,
B6CFF0EF,
E6878513,
B74FF0EF,
FD842783,
78A13,
A93,
......@@ -898,20 +892,20 @@ F8440793,
A0593,
A8613,
78513,
E04FF0EF,
E0CFF0EF,
F8440793,
78513,
B34FF0EF,
B3CFF0EF,
17B7,
E8478513,
B28FF0EF,
E6C78513,
B30FF0EF,
80006F,
C01FF0EF,
C09FF0EF,
13,
9DCFF0EF,
9F4FF0EF,
50793,
FE078CE3,
C55FF06F,
C59FF06F,
2020,
202020,
20,
......@@ -1024,4 +1018,10 @@ CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
;
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ b16b62ed
......@@ -10,7 +10,7 @@ ELF Header:
Version: 0x1
Entry point address: 0x0
Start of program headers: 52 (bytes into file)
Start of section headers: 8840 (bytes into file)
Start of section headers: 8816 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
......@@ -23,26 +23,26 @@ Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000000 001000 00000c 00 AX 0 0 4
[ 2] .text._canputchar PROGBITS 0000000c 00100c 000048 00 AX 0 0 4
[ 3] .text._haschar PROGBITS 00000054 001054 00004c 00 AX 0 0 4
[ 4] .text._putchar PROGBITS 000000a0 0010a0 00005c 00 AX 0 0 4
[ 5] .text._getchar PROGBITS 000000fc 0010fc 00004c 00 AX 0 0 4
[ 6] .text._puts PROGBITS 00000148 001148 000068 00 AX 0 0 4
[ 7] .text._gets PROGBITS 000001b0 0011b0 0000d8 00 AX 0 0 4
[ 8] .text._i2s PROGBITS 00000288 001288 000184 00 AX 0 0 4
[ 9] .text._h2s PROGBITS 0000040c 00140c 0001a8 00 AX 0 0 4
[10] .text._s2d PROGBITS 000005b4 0015b4 0000fc 00 AX 0 0 4
[11] .text._s2h PROGBITS 000006b0 0016b0 000138 00 AX 0 0 4
[12] .text.dispmem PROGBITS 000007e8 0017e8 000240 00 AX 0 0 4
[13] .text.printhelp PROGBITS 00000a28 001a28 00001c 00 AX 0 0 4
[14] .text.main PROGBITS 00000a44 001a44 0003fc 00 AX 0 0 4
[15] .rodata PROGBITS 00000e40 001e40 000048 00 A 0 0 4
[16] .sdata.displ[...] PROGBITS 00000e88 001e88 000004 00 WA 0 0 4
[17] .comment PROGBITS 00000000 001e8c 000012 01 MS 0 0 1
[18] .riscv.attributes RISCV_ATTRIBUTE 00000000 001e9e 000021 00 0 0 1
[19] .symtab SYMTAB 00000000 001ec0 000240 10 20 33 4
[20] .strtab STRTAB 00000000 002100 000082 00 0 0 1
[21] .shstrtab STRTAB 00000000 002182 000103 00 0 0 1
[ 2] .text._canputchar PROGBITS 0000000c 00100c 000044 00 AX 0 0 4
[ 3] .text._haschar PROGBITS 00000050 001050 000048 00 AX 0 0 4
[ 4] .text._putchar PROGBITS 00000098 001098 000058 00 AX 0 0 4
[ 5] .text._getchar PROGBITS 000000f0 0010f0 000048 00 AX 0 0 4
[ 6] .text._puts PROGBITS 00000138 001138 000068 00 AX 0 0 4
[ 7] .text._gets PROGBITS 000001a0 0011a0 0000d8 00 AX 0 0 4
[ 8] .text._i2s PROGBITS 00000278 001278 000184 00 AX 0 0 4
[ 9] .text._h2s PROGBITS 000003fc 0013fc 0001a8 00 AX 0 0 4
[10] .text._s2d PROGBITS 000005a4 0015a4 0000fc 00 AX 0 0 4
[11] .text._s2h PROGBITS 000006a0 0016a0 000138 00 AX 0 0 4
[12] .text.dispmem PROGBITS 000007d8 0017d8 000240 00 AX 0 0 4
[13] .text.printhelp PROGBITS 00000a18 001a18 00001c 00 AX 0 0 4
[14] .text.main PROGBITS 00000a34 001a34 0003f4 00 AX 0 0 4
[15] .rodata PROGBITS 00000e28 001e28 000048 00 A 0 0 4
[16] .sdata.displ[...] PROGBITS 00000e70 001e70 000004 00 WA 0 0 4
[17] .comment PROGBITS 00000000 001e74 000012 01 MS 0 0 1
[18] .riscv.attributes RISCV_ATTRIBUTE 00000000 001e86 000021 00 0 0 1
[19] .symtab SYMTAB 00000000 001ea8 000240 10 20 33 4
[20] .strtab STRTAB 00000000 0020e8 000082 00 0 0 1
[21] .shstrtab STRTAB 00000000 00216a 000103 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -53,7 +53,7 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x00000000 0x00000000 0x00e8c 0x00e8c RWE 0x1000
LOAD 0x001000 0x00000000 0x00000000 0x00e74 0x00e74 RWE 0x1000
Section to Segment mapping:
Segment Sections...
......@@ -70,39 +70,39 @@ Symbol table '.symtab' contains 36 entries:
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1 .text
2: 0000000c 0 SECTION LOCAL DEFAULT 2 .text._canputchar
3: 00000054 0 SECTION LOCAL DEFAULT 3 .text._haschar
4: 000000a0 0 SECTION LOCAL DEFAULT 4 .text._putchar
5: 000000fc 0 SECTION LOCAL DEFAULT 5 .text._getchar
6: 00000148 0 SECTION LOCAL DEFAULT 6 .text._puts
7: 000001b0 0 SECTION LOCAL DEFAULT 7 .text._gets
8: 00000288 0 SECTION LOCAL DEFAULT 8 .text._i2s
9: 0000040c 0 SECTION LOCAL DEFAULT 9 .text._h2s
10: 000005b4 0 SECTION LOCAL DEFAULT 10 .text._s2d
11: 000006b0 0 SECTION LOCAL DEFAULT 11 .text._s2h
12: 000007e8 0 SECTION LOCAL DEFAULT 12 .text.dispmem
13: 00000a28 0 SECTION LOCAL DEFAULT 13 .text.printhelp
14: 00000a44 0 SECTION LOCAL DEFAULT 14 .text.main
15: 00000e40 0 SECTION LOCAL DEFAULT 15 .rodata
16: 00000e88 0 SECTION LOCAL DEFAULT 16 .sdata.displayaddr
3: 00000050 0 SECTION LOCAL DEFAULT 3 .text._haschar
4: 00000098 0 SECTION LOCAL DEFAULT 4 .text._putchar
5: 000000f0 0 SECTION LOCAL DEFAULT 5 .text._getchar
6: 00000138 0 SECTION LOCAL DEFAULT 6 .text._puts
7: 000001a0 0 SECTION LOCAL DEFAULT 7 .text._gets
8: 00000278 0 SECTION LOCAL DEFAULT 8 .text._i2s
9: 000003fc 0 SECTION LOCAL DEFAULT 9 .text._h2s
10: 000005a4 0 SECTION LOCAL DEFAULT 10 .text._s2d
11: 000006a0 0 SECTION LOCAL DEFAULT 11 .text._s2h
12: 000007d8 0 SECTION LOCAL DEFAULT 12 .text.dispmem
13: 00000a18 0 SECTION LOCAL DEFAULT 13 .text.printhelp
14: 00000a34 0 SECTION LOCAL DEFAULT 14 .text.main
15: 00000e28 0 SECTION LOCAL DEFAULT 15 .rodata
16: 00000e70 0 SECTION LOCAL DEFAULT 16 .sdata.displayaddr
17: 00000000 0 SECTION LOCAL DEFAULT 17 .comment
18: 00000000 0 SECTION LOCAL DEFAULT 18 .riscv.attributes
19: 00000000 0 FILE LOCAL DEFAULT ABS console.c
20: 0000000c 72 FUNC LOCAL DEFAULT 2 _canputchar
21: 00000054 76 FUNC LOCAL DEFAULT 3 _haschar
22: 000000a0 92 FUNC LOCAL DEFAULT 4 _putchar
23: 000000fc 76 FUNC LOCAL DEFAULT 5 _getchar
24: 00000148 104 FUNC LOCAL DEFAULT 6 _puts
25: 000001b0 216 FUNC LOCAL DEFAULT 7 _gets
26: 00000288 388 FUNC LOCAL DEFAULT 8 _i2s
27: 0000040c 424 FUNC LOCAL DEFAULT 9 _h2s
28: 000005b4 252 FUNC LOCAL DEFAULT 10 _s2d
29: 000006b0 312 FUNC LOCAL DEFAULT 11 _s2h
30: 00000e88 4 OBJECT LOCAL DEFAULT 16 displayaddr
31: 000007e8 576 FUNC LOCAL DEFAULT 12 dispmem
32: 00000a28 28 FUNC LOCAL DEFAULT 13 printhelp
20: 0000000c 68 FUNC LOCAL DEFAULT 2 _canputchar
21: 00000050 72 FUNC LOCAL DEFAULT 3 _haschar
22: 00000098 88 FUNC LOCAL DEFAULT 4 _putchar
23: 000000f0 72 FUNC LOCAL DEFAULT 5 _getchar
24: 00000138 104 FUNC LOCAL DEFAULT 6 _puts
25: 000001a0 216 FUNC LOCAL DEFAULT 7 _gets
26: 00000278 388 FUNC LOCAL DEFAULT 8 _i2s
27: 000003fc 424 FUNC LOCAL DEFAULT 9 _h2s
28: 000005a4 252 FUNC LOCAL DEFAULT 10 _s2d
29: 000006a0 312 FUNC LOCAL DEFAULT 11 _s2h
30: 00000e70 4 OBJECT LOCAL DEFAULT 16 displayaddr
31: 000007d8 576 FUNC LOCAL DEFAULT 12 dispmem
32: 00000a18 28 FUNC LOCAL DEFAULT 13 printhelp
33: 00000000 12 FUNC GLOBAL DEFAULT 1 __start
34: 00000a44 1020 FUNC GLOBAL DEFAULT 14 main
35: 00000e8c 0 NOTYPE GLOBAL DEFAULT 16 _end
34: 00000a34 1012 FUNC GLOBAL DEFAULT 14 main
35: 00000e74 0 NOTYPE GLOBAL DEFAULT 16 _end
No version information found in this file.
Attribute Section: riscv
......
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.ip_user_files/README.txt 0 → 100644
浏览文件 @ b16b62ed
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.ip_user_files/ip/ram4KB/ram4KB.veo 0 → 100644
浏览文件 @ b16b62ed
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 2
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ram4KB your_instance_name (
.clka(clka), // input wire clka
.ena(ena), // input wire ena
.wea(wea), // input wire [3 : 0] wea
.addra(addra), // input wire [9 : 0] addra
.dina(dina), // input wire [31 : 0] dina
.douta(douta) // output wire [31 : 0] douta
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file ram4KB.v when simulating
// the core, ram4KB. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.ip_user_files/ip/ram4KB/ram4KB.vho 0 → 100644
浏览文件 @ b16b62ed
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 2
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT ram4KB
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ram4KB
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file ram4KB.vhd when simulating
-- the core, ram4KB. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/constrs_1/new/riscv.xdc 0 → 100644
浏览文件 @ b16b62ed
set_property PACKAGE_PIN U18 [get_ports wClk]
set_property PACKAGE_PIN Y17 [get_ports uart_rx]
set_property PACKAGE_PIN R14 [get_ports uart_tx]
set_property PACKAGE_PIN R17 [get_ports nwReset]
set_property PACKAGE_PIN N15 [get_ports {key[0]}]
set_property PACKAGE_PIN N16 [get_ports {key[1]}]
set_property PACKAGE_PIN T17 [get_ports {key[2]}]
set_property PACKAGE_PIN M14 [get_ports {led[0]}]
set_property PACKAGE_PIN M15 [get_ports {led[1]}]
set_property PACKAGE_PIN K16 [get_ports {led[2]}]
set_property PACKAGE_PIN J16 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports wClk]
set_property IOSTANDARD LVCMOS33 [get_ports {key[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports nwReset]
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/mref/led_key/xgui/led_key_v1_0.tcl 0 → 100644
浏览文件 @ b16b62ed
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/mref/riscv_core_with_axi_master/xgui/riscv_core_with_axi_master_v1_0.tcl 0 → 100644
浏览文件 @ b16b62ed
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/hdl/riscv_top_wrapper.v 0 → 100644
浏览文件 @ b16b62ed
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
//Date : Tue Sep 14 18:04:05 2021
//Host : RG6MXLMTA6KAGXI running 64-bit Service Pack 1 (build 7601)
//Command : generate_target riscv_top_wrapper.bd
//Design : riscv_top_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module riscv_top_wrapper
(key,
led,
nwReset,
uart_rx,
uart_tx,
wClk);
input [2:0]key;
output [3:0]led;
input nwReset;
input uart_rx;
output uart_tx;
input wClk;
wire [2:0]key;
wire [3:0]led;
wire nwReset;
wire uart_rx;
wire uart_tx;
wire wClk;
riscv_top riscv_top_i
(.key(key),
.led(led),
.nwReset(nwReset),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.wClk(wClk));
endmodule
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/hw_handoff/riscv_top_bd.tcl 0 → 100644
浏览文件 @ b16b62ed
################################################################
# This is a generated script based on design: riscv_top
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source riscv_top_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# led_key, riscv_core_with_axi_master
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z020clg400-2
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name riscv_top
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
set key [ create_bd_port -dir I -from 2 -to 0 -type data key ]
set led [ create_bd_port -dir O -from 3 -to 0 -type data led ]
set nwReset [ create_bd_port -dir I -type rst nwReset ]
set uart_rx [ create_bd_port -dir I -type data uart_rx ]
set uart_tx [ create_bd_port -dir O -type data uart_tx ]
set wClk [ create_bd_port -dir I -type clk wClk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {50000000} \
] $wClk
# Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
set_property -dict [ list \
CONFIG.C_BAUDRATE {115200} \
CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {50} \
] $axi_uartlite_0
# Create instance: led_key_0, and set properties
set block_name led_key
set block_cell_name led_key_0
if { [catch {set led_key_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $led_key_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: riscv_core_with_axi_0, and set properties
set block_name riscv_core_with_axi_master
set block_cell_name riscv_core_with_axi_0
if { [catch {set riscv_core_with_axi_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $riscv_core_with_axi_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: riscv_core_with_axi_0_axi_periph, and set properties
set riscv_core_with_axi_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 riscv_core_with_axi_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {2} \
] $riscv_core_with_axi_0_axi_periph
# Create instance: rst_wClk_50M, and set properties
set rst_wClk_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wClk_50M ]
# Create interface connections
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M01_AXI [get_bd_intf_pins led_key_0/s00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_m00_axi [get_bd_intf_pins riscv_core_with_axi_0/m00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/S00_AXI]
# Create port connections
connect_bd_net -net axi_uartlite_0_tx [get_bd_ports uart_tx] [get_bd_pins axi_uartlite_0/tx]
connect_bd_net -net key_1 [get_bd_ports key] [get_bd_pins led_key_0/key]
connect_bd_net -net led_key_0_led [get_bd_ports led] [get_bd_pins led_key_0/led]
connect_bd_net -net nwReset_1 [get_bd_ports nwReset] [get_bd_pins rst_wClk_50M/ext_reset_in]
connect_bd_net -net rst_wClk_50M_peripheral_aresetn [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins led_key_0/s00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0/m00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0_axi_periph/ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ARESETN] [get_bd_pins rst_wClk_50M/peripheral_aresetn]
connect_bd_net -net uart_rx_1 [get_bd_ports uart_rx] [get_bd_pins axi_uartlite_0/rx]
connect_bd_net -net wClk_1 [get_bd_ports wClk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins led_key_0/s00_axi_aclk] [get_bd_pins riscv_core_with_axi_0/m00_axi_aclk] [get_bd_pins riscv_core_with_axi_0_axi_periph/ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ACLK] [get_bd_pins rst_wClk_50M/slowest_sync_clk]
# Create address segments
create_bd_addr_seg -range 0x00001000 -offset 0xF0001000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
create_bd_addr_seg -range 0x00001000 -offset 0xF0000000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs led_key_0/s00_axi/reg0] SEG_led_key_0_reg0
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0.xci 0 → 100644
浏览文件 @ b16b62ed
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
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<spirit:componentInstance>
<spirit:instanceName>riscv_top_axi_uartlite_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_uartlite" spirit:version="2.0"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">riscv_top_wClk</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_BITS">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ">50000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_BITS">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PARITY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BAUDRATE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ_d" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0.xdc 0 → 100644
浏览文件 @ b16b62ed
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *cdc_to*/D]
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0_ooc.xdc 0 → 100644
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################################################################################
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# User should update the correct clock period before proceeding further
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# For best results the frequencies should be modified# to match the target
# frequencies.
# create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
create_clock -name s_axi_clk -period 20.000 [get_ports s_axi_aclk]
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
################################################################################
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0_stub.v 0 → 100644
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
// Date : Tue Sep 14 18:05:03 2021
// Host : RG6MXLMTA6KAGXI running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0_stub.v
// Design : riscv_top_axi_uartlite_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_uartlite,Vivado 2018.3" *)
module riscv_top_axi_uartlite_0_0(s_axi_aclk, s_axi_aresetn, interrupt,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, rx, tx)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,interrupt,s_axi_awaddr[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,rx,tx" */;
input s_axi_aclk;
input s_axi_aresetn;
output interrupt;
input [3:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input rx;
output tx;
endmodule
examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0_stub.vhdl 0 → 100644
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-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
-- Date : Tue Sep 14 18:05:03 2021
-- Host : RG6MXLMTA6KAGXI running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_2018/riscv_2018.srcs/sources_1/bd/riscv_top/ip/riscv_top_axi_uartlite_0_0/riscv_top_axi_uartlite_0_0_stub.vhdl
-- Design : riscv_top_axi_uartlite_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity riscv_top_axi_uartlite_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
end riscv_top_axi_uartlite_0_0;
architecture stub of riscv_top_axi_uartlite_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,interrupt,s_axi_awaddr[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,rx,tx";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_uartlite,Vivado 2018.3";
begin
end;
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examples/hdl4se_riscv/z7/riscv_axi_2018/hw_1/hw.xml 0 → 100644
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此差异已折叠。
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