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提交 f6da6054 编写于 作者: 饶先宏's avatar 饶先宏
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Merge branch 'master' of https://codechina.csdn.net/m0_56903617/hdl4se

上级 10137b71 56b6929b
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examples/hdl4se_riscv/verilog/axi/riscv_core_with_axi_master.v 0 → 100644
浏览文件 @ f6da6054
`timescale 1 ns / 1 ps
module riscv_core_with_axi_master (
// clock and reset
input wire wClk,
input wire nwReset,
// Write Address
output wire wAWValid,
output wire [31 : 0] bAWAddr,
output wire [2 : 0] bAWProt,
input wire wAWReady,
// Write Data
output wire wWValid,
output wire [31 : 0] bWData,
output wire [3 : 0] bWStrb,
input wire wWReady,
// Write Response
output wire wBReady,
input wire [1 : 0] bBResp,
input wire wBValid,
// ReadAddr
output wire wARValid,
output wire [31 : 0] bARAddr,
output wire [2 : 0] bARProt,
input wire wARReady,
//ReadData
output wire wRReady
input wire wRValid,
input wire [31 : 0] bRData,
input wire [1 : 0] bRResp
);
reg axi_awvalid; assign wAWValid = axi_awvalid;
reg [31:0] axi_awaddr; assign bAWAddr = axi_awaddr;
assign bAWProt = 3'b000;
reg axi_wvalid; assign wWValid = axi_wvalid;
reg [31:0] axi_wdata; assign bWData = axi_wdata;
reg [3:0] axi_wstrb; assign bWStrb = axi_wstrb;
assign wBReady = 1'b1;
reg axi_arvalid; assign wARValid = axi_arvalid;
reg [31:0] axi_araddr; assign bARAddr = axi_araddr;
assign bARProt = 3'b001;
assign wRReady = 1'b1;
wire wWrite, wRead, wReadReady, wWriteReady;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
wire [4:0] regno;
wire [3:0] regena;
wire [31:0] regwrdata;
wire regwren;
wire [31:0] regrddata;
wire [4:0] regno2;
wire [3:0] regena2;
wire [31:0] regwrdata2;
wire regwren2;
wire [31:0] regrddata2;
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
riscv_core core(wClk, nwReset,
wWrite, bWriteAddr, bWriteData, bWriteMask, wWriteReady,
wRead, bReadAddr, bReadData, wReadReady,
regno, regena, regwrdata, regwren, regrddata,
regno2, regena2, regwrdata2, regwren2, regrddata2
);
//Write Address
reg [31:0] awaddr;
reg awvalid;
always @(posedge wClk)
if (~nwReset) begin
awvalid <= 1'b0;
end else if (wWrite) begin
awaddr <= bWriteAddr;
awvalid <= 1'b1;
end else if (wAWReady) begin
awvalid <= 1'b0;
end
assign wWriteReady = (wWrite || awvalid) && wAWReady;
always @(*)
begin
axi_awvalid = wWrite ? 1'b1 : awvalid;
axi_awaddr = wWrite ? bWriteAddr : awaddr;
end
/* Write Data */
reg [31:0] wdata;
reg [3:0] wstrb;
reg wvalid;
always @(wClk)
begin
if (~nwReset) begin
wvalid <= 1'b0;
end if (wWrite) begin
wdata <= bWriteData;
wstrb <= ~bWriteMask;
wvalid <= 1'b1;
end if (wWReady) begin
wvalid <= 1'b0;
end
end
always @(*)
begin
axi_wvalid = wWrite ? 1'b1 : wvalid;
axi_wdata = wWrite ? bWriteData : wdata;
axi_wstrb = wWrite ? ~bWriteMask : wstrb;
end
//Read Address
reg [31:0] araddr;
reg arvalid;
always @(posedge wClk)
if (~nwReset) begin
arvalid <= 1'b0;
end else if (wRead) begin
araddr <= bReadAddr;
arvalid <= 1'b1;
end else if (wARReady) begin
arvalid <= 1'b0;
end
assign wReadyReady = (wRead || arvalid) && wARReady;
always @(*)
begin
axi_arvalid = wRead ? 1'b1 : arvalid;
axi_araddr = wRead ? bReadAddr : araddr;
end
assign bReadData = bRData;
endmodule
examples/hdl4se_riscv/verilog/axi/riscv_cpu_axi_v1_0.v 已删除 100644 → 0
浏览文件 @ 10137b71
`timescale 1 ns / 1 ps
module riscv_cpu_axi_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_TRANSACTIONS_NUM = 4
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_init_axi_txn,
output wire m00_axi_error,
output wire m00_axi_txn_done,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
riscv_cpu_axi_v1_0_M00_AXI # (
.C_M_START_DATA_VALUE(C_M00_AXI_START_DATA_VALUE),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_TRANSACTIONS_NUM(C_M00_AXI_TRANSACTIONS_NUM)
) riscv_cpu_axi_v1_0_M00_AXI_inst (
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.ERROR(m00_axi_error),
.TXN_DONE(m00_axi_txn_done),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
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