DE1 SoC Board Configuration



Pin Assignments:




Pin Assignment Table:



ADC
Name Location Direction Standard
ADC_CONVST AJ4 output 3.3-V LVTTL
ADC_DIN AK4 output 3.3-V LVTTL
ADC_DOUT AK3 input 3.3-V LVTTL
ADC_SCLK AK2 output 3.3-V LVTTL



Audio
Name Location Direction Standard
AUD_ADCDAT K7 input 3.3-V LVTTL
AUD_ADCLRCK K8 inout 3.3-V LVTTL
AUD_BCLK H7 inout 3.3-V LVTTL
AUD_DACDAT J7 output 3.3-V LVTTL
AUD_DACLRCK H8 inout 3.3-V LVTTL
AUD_XCK G7 output 3.3-V LVTTL



CLOCK
Name Location Direction Standard
CLOCK2_50 AA16 input 3.3-V LVTTL
CLOCK3_50 Y26 input 3.3-V LVTTL
CLOCK4_50 K14 input 3.3-V LVTTL
CLOCK_50 AF14 input 3.3-V LVTTL



SDRAM
Name Location Direction Standard
DRAM_ADDR[0] AK14 output 3.3-V LVTTL
DRAM_ADDR[1] AH14 output 3.3-V LVTTL
DRAM_ADDR[2] AG15 output 3.3-V LVTTL
DRAM_ADDR[3] AE14 output 3.3-V LVTTL
DRAM_ADDR[4] AB15 output 3.3-V LVTTL
DRAM_ADDR[5] AC14 output 3.3-V LVTTL
DRAM_ADDR[6] AD14 output 3.3-V LVTTL
DRAM_ADDR[7] AF15 output 3.3-V LVTTL
DRAM_ADDR[8] AH15 output 3.3-V LVTTL
DRAM_ADDR[9] AG13 output 3.3-V LVTTL
DRAM_ADDR[10] AG12 output 3.3-V LVTTL
DRAM_ADDR[11] AH13 output 3.3-V LVTTL
DRAM_ADDR[12] AJ14 output 3.3-V LVTTL
DRAM_BA[0] AF13 output 3.3-V LVTTL
DRAM_BA[1] AJ12 output 3.3-V LVTTL
DRAM_CAS_N AF11 output 3.3-V LVTTL
DRAM_CKE AK13 output 3.3-V LVTTL
DRAM_CLK AH12 output 3.3-V LVTTL
DRAM_CS_N AG11 output 3.3-V LVTTL
DRAM_DQ[0] AK6 inout 3.3-V LVTTL
DRAM_DQ[1] AJ7 inout 3.3-V LVTTL
DRAM_DQ[2] AK7 inout 3.3-V LVTTL
DRAM_DQ[3] AK8 inout 3.3-V LVTTL
DRAM_DQ[4] AK9 inout 3.3-V LVTTL
DRAM_DQ[5] AG10 inout 3.3-V LVTTL
DRAM_DQ[6] AK11 inout 3.3-V LVTTL
DRAM_DQ[7] AJ11 inout 3.3-V LVTTL
DRAM_DQ[8] AH10 inout 3.3-V LVTTL
DRAM_DQ[9] AJ10 inout 3.3-V LVTTL
DRAM_DQ[10] AJ9 inout 3.3-V LVTTL
DRAM_DQ[11] AH9 inout 3.3-V LVTTL
DRAM_DQ[12] AH8 inout 3.3-V LVTTL
DRAM_DQ[13] AH7 inout 3.3-V LVTTL
DRAM_DQ[14] AJ6 inout 3.3-V LVTTL
DRAM_DQ[15] AJ5 inout 3.3-V LVTTL
DRAM_LDQM AB13 output 3.3-V LVTTL
DRAM_RAS_N AE13 output 3.3-V LVTTL
DRAM_UDQM AK12 output 3.3-V LVTTL
DRAM_WE_N AA13 output 3.3-V LVTTL



I2C for Audio and Video-In
Name Location Direction Standard
FPGA_I2C_SCLK J12 output 3.3-V LVTTL
FPGA_I2C_SDAT K12 inout 3.3-V LVTTL



SEG7
Name Location Direction Standard
HEX0[0] AE26 output 3.3-V LVTTL
HEX0[1] AE27 output 3.3-V LVTTL
HEX0[2] AE28 output 3.3-V LVTTL
HEX0[3] AG27 output 3.3-V LVTTL
HEX0[4] AF28 output 3.3-V LVTTL
HEX0[5] AG28 output 3.3-V LVTTL
HEX0[6] AH28 output 3.3-V LVTTL
HEX1[0] AJ29 output 3.3-V LVTTL
HEX1[1] AH29 output 3.3-V LVTTL
HEX1[2] AH30 output 3.3-V LVTTL
HEX1[3] AG30 output 3.3-V LVTTL
HEX1[4] AF29 output 3.3-V LVTTL
HEX1[5] AF30 output 3.3-V LVTTL
HEX1[6] AD27 output 3.3-V LVTTL
HEX2[0] AB23 output 3.3-V LVTTL
HEX2[1] AE29 output 3.3-V LVTTL
HEX2[2] AD29 output 3.3-V LVTTL
HEX2[3] AC28 output 3.3-V LVTTL
HEX2[4] AD30 output 3.3-V LVTTL
HEX2[5] AC29 output 3.3-V LVTTL
HEX2[6] AC30 output 3.3-V LVTTL
HEX3[0] AD26 output 3.3-V LVTTL
HEX3[1] AC27 output 3.3-V LVTTL
HEX3[2] AD25 output 3.3-V LVTTL
HEX3[3] AC25 output 3.3-V LVTTL
HEX3[4] AB28 output 3.3-V LVTTL
HEX3[5] AB25 output 3.3-V LVTTL
HEX3[6] AB22 output 3.3-V LVTTL
HEX4[0] AA24 output 3.3-V LVTTL
HEX4[1] Y23 output 3.3-V LVTTL
HEX4[2] Y24 output 3.3-V LVTTL
HEX4[3] W22 output 3.3-V LVTTL
HEX4[4] W24 output 3.3-V LVTTL
HEX4[5] V23 output 3.3-V LVTTL
HEX4[6] W25 output 3.3-V LVTTL
HEX5[0] V25 output 3.3-V LVTTL
HEX5[1] AA28 output 3.3-V LVTTL
HEX5[2] Y27 output 3.3-V LVTTL
HEX5[3] AB27 output 3.3-V LVTTL
HEX5[4] AB26 output 3.3-V LVTTL
HEX5[5] AA26 output 3.3-V LVTTL
HEX5[6] AA25 output 3.3-V LVTTL



IR
Name Location Direction Standard
IRDA_RXD AA30 input 3.3-V LVTTL
IRDA_TXD AB30 output 3.3-V LVTTL



KEY
Name Location Direction Standard
KEY[0] AA14 input 3.3-V LVTTL
KEY[1] AA15 input 3.3-V LVTTL
KEY[2] W15 input 3.3-V LVTTL
KEY[3] Y16 input 3.3-V LVTTL



LED
Name Location Direction Standard
LEDR[0] V16 output 3.3-V LVTTL
LEDR[1] W16 output 3.3-V LVTTL
LEDR[2] V17 output 3.3-V LVTTL
LEDR[3] V18 output 3.3-V LVTTL
LEDR[4] W17 output 3.3-V LVTTL
LEDR[5] W19 output 3.3-V LVTTL
LEDR[6] Y19 output 3.3-V LVTTL
LEDR[7] W20 output 3.3-V LVTTL
LEDR[8] W21 output 3.3-V LVTTL
LEDR[9] Y21 output 3.3-V LVTTL



PS2
Name Location Direction Standard
PS2_CLK AD7 inout 3.3-V LVTTL
PS2_CLK2 AD9 inout 3.3-V LVTTL
PS2_DAT AE7 inout 3.3-V LVTTL
PS2_DAT2 AE9 inout 3.3-V LVTTL



SW
Name Location Direction Standard
SW[0] AB12 input 3.3-V LVTTL
SW[1] AC12 input 3.3-V LVTTL
SW[2] AF9 input 3.3-V LVTTL
SW[3] AF10 input 3.3-V LVTTL
SW[4] AD11 input 3.3-V LVTTL
SW[5] AD12 input 3.3-V LVTTL
SW[6] AE11 input 3.3-V LVTTL
SW[7] AC9 input 3.3-V LVTTL
SW[8] AD10 input 3.3-V LVTTL
SW[9] AE12 input 3.3-V LVTTL



Video-In
Name Location Direction Standard
TD_CLK27 H15 input 3.3-V LVTTL
TD_DATA[0] D2 input 3.3-V LVTTL
TD_DATA[1] B1 input 3.3-V LVTTL
TD_DATA[2] E2 input 3.3-V LVTTL
TD_DATA[3] B2 input 3.3-V LVTTL
TD_DATA[4] D1 input 3.3-V LVTTL
TD_DATA[5] E1 input 3.3-V LVTTL
TD_DATA[6] C2 input 3.3-V LVTTL
TD_DATA[7] B3 input 3.3-V LVTTL
TD_HS A5 input 3.3-V LVTTL
TD_RESET_N F6 output 3.3-V LVTTL
TD_VS A3 input 3.3-V LVTTL



VGA
Name Location Direction Standard
VGA_BLANK_N F10 output 3.3-V LVTTL
VGA_B[0] B13 output 3.3-V LVTTL
VGA_B[1] G13 output 3.3-V LVTTL
VGA_B[2] H13 output 3.3-V LVTTL
VGA_B[3] F14 output 3.3-V LVTTL
VGA_B[4] H14 output 3.3-V LVTTL
VGA_B[5] F15 output 3.3-V LVTTL
VGA_B[6] G15 output 3.3-V LVTTL
VGA_B[7] J14 output 3.3-V LVTTL
VGA_CLK A11 output 3.3-V LVTTL
VGA_G[0] J9 output 3.3-V LVTTL
VGA_G[1] J10 output 3.3-V LVTTL
VGA_G[2] H12 output 3.3-V LVTTL
VGA_G[3] G10 output 3.3-V LVTTL
VGA_G[4] G11 output 3.3-V LVTTL
VGA_G[5] G12 output 3.3-V LVTTL
VGA_G[6] F11 output 3.3-V LVTTL
VGA_G[7] E11 output 3.3-V LVTTL
VGA_HS B11 output 3.3-V LVTTL
VGA_R[0] A13 output 3.3-V LVTTL
VGA_R[1] C13 output 3.3-V LVTTL
VGA_R[2] E13 output 3.3-V LVTTL
VGA_R[3] B12 output 3.3-V LVTTL
VGA_R[4] C12 output 3.3-V LVTTL
VGA_R[5] D12 output 3.3-V LVTTL
VGA_R[6] E12 output 3.3-V LVTTL
VGA_R[7] F13 output 3.3-V LVTTL
VGA_SYNC_N C10 output 3.3-V LVTTL
VGA_VS D11 output 3.3-V LVTTL



GPIO_0 connect to GPIO Default
Name Location Direction Standard GPIO Pin Index
GPIO[0] AC18 inout 3.3-V LVTTL 1
GPIO[1] Y17 inout 3.3-V LVTTL 2
GPIO[2] AD17 inout 3.3-V LVTTL 3
GPIO[3] Y18 inout 3.3-V LVTTL 4
GPIO[4] AK16 inout 3.3-V LVTTL 5
GPIO[5] AK18 inout 3.3-V LVTTL 6
GPIO[6] AK19 inout 3.3-V LVTTL 7
GPIO[7] AJ19 inout 3.3-V LVTTL 8
GPIO[8] AJ17 inout 3.3-V LVTTL 9
GPIO[9] AJ16 inout 3.3-V LVTTL 10
GPIO[10] AH18 inout 3.3-V LVTTL 13
GPIO[11] AH17 inout 3.3-V LVTTL 14
GPIO[12] AG16 inout 3.3-V LVTTL 15
GPIO[13] AE16 inout 3.3-V LVTTL 16
GPIO[14] AF16 inout 3.3-V LVTTL 17
GPIO[15] AG17 inout 3.3-V LVTTL 18
GPIO[16] AA18 inout 3.3-V LVTTL 19
GPIO[17] AA19 inout 3.3-V LVTTL 20
GPIO[18] AE17 inout 3.3-V LVTTL 21
GPIO[19] AC20 inout 3.3-V LVTTL 22
GPIO[20] AH19 inout 3.3-V LVTTL 23
GPIO[21] AJ20 inout 3.3-V LVTTL 24
GPIO[22] AH20 inout 3.3-V LVTTL 25
GPIO[23] AK21 inout 3.3-V LVTTL 26
GPIO[24] AD19 inout 3.3-V LVTTL 27
GPIO[25] AD20 inout 3.3-V LVTTL 28
GPIO[26] AE18 inout 3.3-V LVTTL 31
GPIO[27] AE19 inout 3.3-V LVTTL 32
GPIO[28] AF20 inout 3.3-V LVTTL 33
GPIO[29] AF21 inout 3.3-V LVTTL 34
GPIO[30] AF19 inout 3.3-V LVTTL 35
GPIO[31] AG21 inout 3.3-V LVTTL 36
GPIO[32] AF18 inout 3.3-V LVTTL 37
GPIO[33] AG20 inout 3.3-V LVTTL 38
GPIO[34] AG18 inout 3.3-V LVTTL 39
GPIO[35] AJ21 inout 3.3-V LVTTL 40