`timescale 1 ns / 1 ps

module riscv_core_with_axi_master (
	    // clock and reset
		input wire				wClk,
		input wire				nwReset,

		// Write Address
		output wire				wAWValid,
		output wire [31 : 0]	bAWAddr,
		output wire [2 : 0]		bAWProt,
		input wire				wAWReady,

		// Write Data 
		output wire				wWValid,
		output wire [31 : 0]	bWData,
		output wire [3 : 0]		bWStrb,
		input wire				wWReady,

		// Write Response
		output wire				wBReady,
		input wire [1 : 0]		bBResp,
		input wire				wBValid,

		// ReadAddr
		output wire				wARValid,
		output wire [31 : 0]	bARAddr,
		output wire [2 : 0]		bARProt,
		input wire				wARReady,

		//ReadData
		output wire				wRReady,
		input wire				wRValid,
		input wire [31 : 0]		bRData,
		input wire [1 : 0]		bRResp
);

	reg			axi_awvalid;	assign wAWValid = axi_awvalid;
	reg [31:0] 	axi_awaddr;		assign bAWAddr = axi_awaddr;
								assign bAWProt = 3'b000;

	reg			axi_wvalid;		assign wWValid = axi_wvalid;
	reg [31:0] 	axi_wdata;		assign bWData = axi_wdata;
	reg [3:0]   axi_wstrb;		assign bWStrb = axi_wstrb;

								assign wBReady = 1'b1;

	reg			axi_arvalid;	assign wARValid = axi_arvalid;
	reg [31:0] 	axi_araddr;		assign bARAddr = axi_araddr;
								assign bARProt = 3'b001;

								assign wRReady = 1'b1;

    wire wWrite, wRead, wReadReady, wWriteReady;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;

	wire [4:0]  regno;
    wire [3:0]  regena;
    wire [31:0] regwrdata;
    wire        regwren;
    wire [31:0] regrddata;
    wire [4:0]  regno2;
    wire [3:0]  regena2;
    wire [31:0] regwrdata2;
    wire        regwren2;
    wire [31:0] regrddata2;

	reg [31:0] lastreadaddr;
	reg		   lastread;

	always @(posedge wClk)
	if (~nwReset) begin
		lastreadaddr <= 0;
		lastread <= 0;
	end else begin
		lastreadaddr <= bReadAddr;
		lastread <= wRead;
	end

	assign bReadData = 
            ((lastreadaddr & 32'hffffff00) == 32'hf0000000) ? bRData : (
            ((lastreadaddr & 32'hff000000) == 32'h00000000) ? bReadDataRam : (32'h0)
            );

	assign wReadReady = ((lastreadaddr & 32'hf0000000) == 32'hf0000000) ? bRData : (
						((lastreadaddr & 32'hfff00000) == 32'h00000000) ? lastread : (0)
						);


    wire [29:0] ramaddr;
    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];

    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
    regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
	ram4kB     ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
	riscv_core core(wClk, nwReset, 
                wWrite, bWriteAddr, bWriteData, bWriteMask, wWriteReady, 
                wRead, bReadAddr, bReadData, wReadReady,
                regno, regena, regwrdata, regwren, regrddata,
                regno2, regena2, regwrdata2, regwren2, regrddata2
                );


	//Write Address
	reg [31:0] awaddr;
	reg awvalid;
	always @(posedge wClk)
	if (~nwReset) begin
		awvalid <= 1'b0;
	end else if (wWrite) begin
		awaddr <= bWriteAddr;
		awvalid <= 1'b1;
	end else if (wAWReady) begin
		awvalid <= 1'b0;
	end

	always @(*)
	begin
		axi_awvalid = wWrite ? 1'b1 : awvalid;
		axi_awaddr = wWrite ? bWriteAddr : awaddr;
	end

	/* Write Data */
	reg [31:0] wdata;
	reg [3:0]  wstrb;
	reg		   wvalid;
	always @(wClk)
	begin
		if (~nwReset) begin
			wvalid <= 1'b0;
		end if (wWrite) begin
			wdata <= bWriteData;
			wstrb <= ~bWriteMask;
			wvalid <= 1'b1;
		end if (wWReady) begin
			wvalid <= 1'b0;
		end
	end

	assign wWriteReady = ((wWrite || wvalid) && wWReady) || ((bWriteAddr & 32'hfff00000) == 32'h00000000);

	always @(*)
	begin
		axi_wvalid = wWrite ? 1'b1 : wvalid;
		axi_wdata = wWrite ? bWriteData : wdata;
		axi_wstrb = wWrite ? ~bWriteMask : wstrb;
	end

	//Read Address
	reg [31:0] araddr;
	reg arvalid;
	always @(posedge wClk)
	if (~nwReset) begin
		arvalid <= 1'b0;
	end else if (wRead) begin
		araddr <= bReadAddr;
		arvalid <= 1'b1;
	end else if (wARReady) begin
		arvalid <= 1'b0;
	end

	always @(*)
	begin
		axi_arvalid = wRead ? 1'b1 : arvalid;
		axi_araddr = wRead ? bReadAddr : araddr;
	end

endmodule