module axi1to2
	#(
		parameter integer M00_ADDR_MASK =	32'hfffff000,
		parameter integer M00_ADDR_START =	32'h00000000,
		parameter integer M01_ADDR_MASK =	32'hfffff000,
		parameter integer M01_ADDR_START =	32'h00001000
	)
	(
		input wire  axi_aclk,
		input wire  axi_aresetn,

		input wire [31 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output reg  s00_axi_awready,
		input wire [31 : 0] s00_axi_wdata,
		input wire [3 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output reg  s00_axi_wready,
		output reg [1 : 0] s00_axi_bresp,
		output reg  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [31 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output reg  s00_axi_arready,
		output reg [31 : 0] s00_axi_rdata,
		output reg [1 : 0] s00_axi_rresp,
		output reg  s00_axi_rvalid,
		input wire  s00_axi_rready,

		output wire [31 : 0] m00_axi_awaddr,
		output wire [2 : 0] m00_axi_awprot,
		output wire  m00_axi_awvalid,
		input wire  m00_axi_awready,
		output wire [31 : 0] m00_axi_wdata,
		output wire [3 : 0] m00_axi_wstrb,
		output wire  m00_axi_wvalid,
		input wire  m00_axi_wready,
		input wire [1 : 0] m00_axi_bresp,
		input wire  m00_axi_bvalid,
		output wire  m00_axi_bready,
		output wire [31 : 0] m00_axi_araddr,
		output wire [2 : 0] m00_axi_arprot,
		output wire  m00_axi_arvalid,
		input wire  m00_axi_arready,
		input wire [31 : 0] m00_axi_rdata,
		input wire [1 : 0] m00_axi_rresp,
		input wire  m00_axi_rvalid,
		output wire  m00_axi_rready,

		output wire [31 : 0] m01_axi_awaddr,
		output wire [2 : 0] m01_axi_awprot,
		output wire  m01_axi_awvalid,
		input wire  m01_axi_awready,
		output wire [31 : 0] m01_axi_wdata,
		output wire [3 : 0] m01_axi_wstrb,
		output wire  m01_axi_wvalid,
		input wire  m01_axi_wready,
		input wire [1 : 0] m01_axi_bresp,
		input wire  m01_axi_bvalid,
		output wire  m01_axi_bready,
		output wire [31 : 0] m01_axi_araddr,
		output wire [2 : 0] m01_axi_arprot,
		output wire  m01_axi_arvalid,
		input wire  m01_axi_arready,
		input wire [31 : 0] m01_axi_rdata,
		input wire [1 : 0] m01_axi_rresp,
		input wire  m01_axi_rvalid,
		output wire  m01_axi_rready
	);	

	reg [31:0] axi_araddr;
	reg		   axi_arvalid;

	always @(posedge axi_aclk)
	if (~axi_aresetn) begin
		axi_araddr <= 0;
		axi_arvalid <= 0;
	end else if (s00_axi_arvalid) begin
		axi_araddr <= s00_axi_araddr;
		axi_arvalid <= 1'b1;
	end else if (s00_axi_rready) begin
		axi_arvalid <= 1'b0;
	end

	wire is_M00_w = ((s00_axi_awaddr & M00_ADDR_MASK) == M00_ADDR_START);
	wire is_M01_w = ((s00_axi_awaddr & M01_ADDR_MASK) == M01_ADDR_START);
	wire is_M00_r = ((s00_axi_araddr & M00_ADDR_MASK) == M00_ADDR_START);
	wire is_M01_r = ((s00_axi_araddr & M01_ADDR_MASK) == M01_ADDR_START);
	wire is_M00_r_r = axi_arvalid && ((axi_araddr & M00_ADDR_MASK) == M00_ADDR_START);
	wire is_M01_r_r = axi_arvalid && ((axi_araddr & M01_ADDR_MASK) == M01_ADDR_START);

	assign m00_axi_awaddr = s00_axi_awaddr;
	assign m00_axi_awprot = s00_axi_awprot;
	assign m00_axi_awvalid = s00_axi_awvalid && is_M00_w;
	assign m00_axi_wdata = s00_axi_wdata;
	assign m00_axi_wstrb = s00_axi_wstrb;
	assign m00_axi_wvalid = s00_axi_wvalid && is_M00_w;
	assign m00_axi_bready = s00_axi_bready;
	assign m00_axi_araddr = s00_axi_araddr;
	assign m00_axi_arprot = s00_axi_arprot;
	assign m00_axi_arvalid = s00_axi_arvalid && is_M00_r;
	assign m00_axi_rready = s00_axi_rready && is_M00_r;

	assign m01_axi_awaddr = s00_axi_awaddr;
	assign m01_axi_awprot = s00_axi_awprot;
	assign m01_axi_awvalid = s00_axi_awvalid && is_M01_w;
	assign m01_axi_wdata = s00_axi_wdata;
	assign m01_axi_wstrb = s00_axi_wstrb;
	assign m01_axi_wvalid = s00_axi_wvalid && is_M01_w;
	assign m01_axi_bready = s00_axi_bready;
	assign m01_axi_araddr = s00_axi_araddr;
	assign m01_axi_arprot = s00_axi_arprot;
	assign m01_axi_arvalid = s00_axi_arvalid && is_M01_r;
	assign m01_axi_rready = s00_axi_rready && is_M01_r;

	always @(*)
	if (is_M00_w)
		s00_axi_awready = m00_axi_awready;
	else if (is_M01_w)
		s00_axi_awready = m01_axi_awready;
	else
		s00_axi_awready = 1;

	always @(*)
	if (is_M00_w)
		s00_axi_wready = m00_axi_wready;
	else if (is_M01_w)
		s00_axi_wready = m01_axi_wready;
	else
		s00_axi_wready = 1;

	always @(*)
	if (is_M00_w)
		s00_axi_bresp = m00_axi_bresp;
	else if (is_M01_w)
		s00_axi_bresp = m01_axi_bresp;
	else
		s00_axi_bresp = 0;

	always @(*)
	if (is_M00_w)
		s00_axi_bvalid = m00_axi_bvalid;
	else if (is_M01_w)
		s00_axi_bvalid = m01_axi_bvalid;
	else
		s00_axi_bvalid = 1;

	always @(*)
	if (is_M00_r_r)
		s00_axi_arready = m00_axi_arready;
	else if (is_M01_r_r)
		s00_axi_arready = m01_axi_arready;
	else
		s00_axi_arready = 1;

	always @(*)
	if (is_M00_r_r)
		s00_axi_rdata = m00_axi_rdata;
	else if (is_M01_r_r)
		s00_axi_rdata = m01_axi_rdata;
	else
		s00_axi_rdata = 32'hefbeadde;

	always @(*)
	if (is_M00_r_r)
		s00_axi_rresp = m00_axi_rresp;
	else if (is_M01_r_r)
		s00_axi_rresp = m01_axi_rresp;
	else
		s00_axi_rresp = 0;

	always @(*)
	if (is_M00_r_r)
		s00_axi_rvalid = m00_axi_rvalid;
	else if (is_M01_r_r)
		s00_axi_rvalid = m01_axi_rvalid;
	else
		s00_axi_rvalid = 1;

endmodule