#----------------------------------------------------------- # Vivado v2021.1 (64-bit) # SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021 # IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 # Start of session at: Tue Sep 14 06:26:20 2021 # Process ID: 46244 # Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1 # Command line: vivado.exe -log risc_axi_v5_top_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source risc_axi_v5_top_wrapper.tcl # Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/risc_axi_v5_top_wrapper.vds # Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1\vivado.jou #----------------------------------------------------------- source risc_axi_v5_top_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.1/data/ip'. INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'm00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'm00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'm00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm00_axi'. INFO: [IP_Flow 19-4728] Bus Interface 'm00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm00_axi_aresetn'. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's00_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's00_axi'. INFO: [IP_Flow 19-4728] Bus Interface 's00_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's00_axi_aresetn'. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0'. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'; Can't find the specified path. If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it. WARNING: [IP_Flow 19-2207] Repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0' already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'. Command: synth_design -top risc_axi_v5_top_wrapper -part xc7z020clg400-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Device 21-403] Loading part xc7z020clg400-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 37324 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.766 ; gain = 0.000 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_wrapper' [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hdl/risc_axi_v5_top_wrapper.v:12] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:291] INFO: [Synth 8-638] synthesizing module 'risc_axi_v5_top_axi_uartlite_0_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/synth/risc_axi_v5_top_axi_uartlite_0_0.vhd:86] Parameter C_FAMILY bound to: zynq - type: string Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 50000000 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_BAUDRATE bound to: 115200 - type: integer Parameter C_DATA_BITS bound to: 8 - type: integer Parameter C_USE_PARITY bound to: 0 - type: integer Parameter C_ODD_PARITY bound to: 0 - type: integer INFO: [Synth 8-3491] module 'axi_uartlite' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2128' bound to instance 'U0' of component 'axi_uartlite' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/synth/risc_axi_v5_top_axi_uartlite_0_0.vhd:162] INFO: [Synth 8-638] synthesizing module 'axi_uartlite' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2190] INFO: [Synth 8-638] synthesizing module 'uartlite_core' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1650] INFO: [Synth 8-638] synthesizing module 'baudrate' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1453] INFO: [Synth 8-256] done synthesizing module 'baudrate' (1#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1453] INFO: [Synth 8-638] synthesizing module 'uartlite_rx' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:927] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'srl_fifo_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000] INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697] INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143] INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (3#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143] INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397] INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (4#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397] INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (5#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697] INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f' (6#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000] INFO: [Synth 8-256] done synthesizing module 'uartlite_rx' (7#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:927] INFO: [Synth 8-638] synthesizing module 'uartlite_tx' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408] INFO: [Synth 8-256] done synthesizing module 'uartlite_tx' (8#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408] INFO: [Synth 8-256] done synthesizing module 'uartlite_core' (9#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1650] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'slave_attachment' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-638] synthesizing module 'address_decoder' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-638] synthesizing module 'pselect_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'pselect_f' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder' (11#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (12#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (13#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-256] done synthesizing module 'axi_uartlite' (14#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2190] INFO: [Synth 8-256] done synthesizing module 'risc_axi_v5_top_axi_uartlite_0_0' (15#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/synth/risc_axi_v5_top_axi_uartlite_0_0.vhd:86] WARNING: [Synth 8-7071] port 'interrupt' of module 'risc_axi_v5_top_axi_uartlite_0_0' is unconnected for instance 'axi_uartlite_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:374] WARNING: [Synth 8-7023] instance 'axi_uartlite_0' of module 'risc_axi_v5_top_axi_uartlite_0_0' has 22 connections declared, but only 21 given [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:374] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_led_key_0_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/synth/risc_axi_v5_top_led_key_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'led_key' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/led_key/led_key.v:4] INFO: [Synth 8-6155] done synthesizing module 'led_key' (16#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/led_key/led_key.v:4] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_led_key_0_0' (17#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_led_key_0_0/synth/risc_axi_v5_top_led_key_0_0.v:58] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_5' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/synth/risc_axi_v5_top_riscv_core_with_axi_0_5.v:58] INFO: [Synth 8-6157] synthesizing module 'riscv_core_with_axi_master' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:4] INFO: [Synth 8-6157] synthesizing module 'regfile' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/regfile.v:2] INFO: [Synth 8-6155] done synthesizing module 'regfile' (18#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/regfile.v:2] INFO: [Synth 8-638] synthesizing module 'ram4KB' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/synth/ram4KB.vhd:70] Parameter C_FAMILY bound to: zynq - type: string Parameter C_XDEVICEFAMILY bound to: zynq - type: string Parameter C_ELABORATION_DIR bound to: ./ - type: string Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_MEM_TYPE bound to: 0 - type: integer Parameter C_BYTE_SIZE bound to: 8 - type: integer Parameter C_ALGORITHM bound to: 1 - type: integer Parameter C_PRIM_TYPE bound to: 1 - type: integer Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer Parameter C_INIT_FILE_NAME bound to: ram4KB.mif - type: string Parameter C_INIT_FILE bound to: ram4KB.mem - type: string Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer Parameter C_DEFAULT_DATA bound to: 0 - type: string Parameter C_HAS_RSTA bound to: 0 - type: integer Parameter C_RST_PRIORITY_A bound to: CE - type: string Parameter C_RSTRAM_A bound to: 0 - type: integer Parameter C_INITA_VAL bound to: 0 - type: string Parameter C_HAS_ENA bound to: 1 - type: integer Parameter C_HAS_REGCEA bound to: 0 - type: integer Parameter C_USE_BYTE_WEA bound to: 1 - type: integer Parameter C_WEA_WIDTH bound to: 4 - type: integer Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer Parameter C_READ_WIDTH_A bound to: 32 - type: integer Parameter C_WRITE_DEPTH_A bound to: 1024 - type: integer Parameter C_READ_DEPTH_A bound to: 1024 - type: integer Parameter C_ADDRA_WIDTH bound to: 10 - type: integer Parameter C_HAS_RSTB bound to: 0 - type: integer Parameter C_RST_PRIORITY_B bound to: CE - type: string Parameter C_RSTRAM_B bound to: 0 - type: integer Parameter C_INITB_VAL bound to: 0 - type: string Parameter C_HAS_ENB bound to: 0 - type: integer Parameter C_HAS_REGCEB bound to: 0 - type: integer Parameter C_USE_BYTE_WEB bound to: 1 - type: integer Parameter C_WEB_WIDTH bound to: 4 - type: integer Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer Parameter C_READ_WIDTH_B bound to: 32 - type: integer Parameter C_WRITE_DEPTH_B bound to: 1024 - type: integer Parameter C_READ_DEPTH_B bound to: 1024 - type: integer Parameter C_ADDRB_WIDTH bound to: 10 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_USE_SOFTECC bound to: 0 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_EN_ECC_PIPE bound to: 0 - type: integer Parameter C_READ_LATENCY_A bound to: 1 - type: integer Parameter C_READ_LATENCY_B bound to: 1 - type: integer Parameter C_HAS_INJECTERR bound to: 0 - type: integer Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string Parameter C_COMMON_CLK bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer Parameter C_USE_URAM bound to: 0 - type: integer Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer Parameter C_COUNT_36K_BRAM bound to: 1 - type: string Parameter C_COUNT_18K_BRAM bound to: 0 - type: string Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.96495 mW - type: string INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/synth/ram4KB.vhd:236] INFO: [Synth 8-256] done synthesizing module 'ram4KB' (27#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/ip/ram4KB/synth/ram4KB.vhd:70] WARNING: [Synth 8-689] width (30) of port connection 'addra' does not match port width (10) of module 'ram4KB' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:100] INFO: [Synth 8-6157] synthesizing module 'riscv_core_v5' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:58] INFO: [Synth 8-6157] synthesizing module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/mul32.v:34] INFO: [Synth 8-6155] done synthesizing module 'mul32' (28#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/mul32.v:34] WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:192] INFO: [Synth 8-6157] synthesizing module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/div32.v:34] INFO: [Synth 8-6155] done synthesizing module 'div32' (29#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/div32.v:34] WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:271] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:379] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:448] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:457] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:446] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:487] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:566] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:661] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:783] INFO: [Synth 8-226] default block is never used [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:917] INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:780] WARNING: [Synth 8-567] referenced signal 'wReadReady' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:769] WARNING: [Synth 8-567] referenced signal 'wReadReady' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:1049] WARNING: [Synth 8-567] referenced signal 'lastRead' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:1049] WARNING: [Synth 8-567] referenced signal 'lastReadAddr' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:1049] INFO: [Synth 8-6155] done synthesizing module 'riscv_core_v5' (30#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v:58] WARNING: [Synth 8-567] referenced signal 'writeaxi' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:141] WARNING: [Synth 8-567] referenced signal 'writeaxi' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:166] WARNING: [Synth 8-567] referenced signal 'readaxi' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:187] INFO: [Synth 8-6155] done synthesizing module 'riscv_core_with_axi_master' (31#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:4] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_5' (32#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_riscv_core_with_axi_0_5/synth/risc_axi_v5_top_riscv_core_with_axi_0_5.v:58] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_axi_periph_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:515] INFO: [Synth 8-6157] synthesizing module 'm00_couplers_imp_DIBHKD' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:12] INFO: [Synth 8-6155] done synthesizing module 'm00_couplers_imp_DIBHKD' (33#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:12] INFO: [Synth 8-6157] synthesizing module 'm01_couplers_imp_15DQFTV' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:144] INFO: [Synth 8-6155] done synthesizing module 'm01_couplers_imp_15DQFTV' (34#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:144] INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_4FUU9H' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:983] INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_4FUU9H' (35#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:983] INFO: [Synth 8-6157] synthesizing module 'risc_axi_v5_top_xbar_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/synth/risc_axi_v5_top_xbar_0.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_axi_crossbar' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4884] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_crossbar_sasd' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:1240] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_addr_decoder' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:794] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_carry_and' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_carry_and' (36#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' (37#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' (37#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_addr_decoder' (38#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:794] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_decerr_slave' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3501] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_decerr_slave' (39#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3501] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_addr_arbiter_sasd' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:65] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_addr_arbiter_sasd' (40#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:65] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_splitter' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_splitter' (41#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_25_splitter__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_splitter__parameterized0' (41#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' (42#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' (42#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' (42#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_24_axic_register_slice' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8f68/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_24_axic_register_slice' (43#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8f68/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized2' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized2' (43#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_crossbar_sasd' (44#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:1240] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_25_axi_crossbar' (45#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:4884] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_xbar_0' (46#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_xbar_0/synth/risc_axi_v5_top_xbar_0.v:59] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_riscv_core_with_axi_0_axi_periph_0' (47#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:515] INFO: [Synth 8-638] synthesizing module 'risc_axi_v5_top_rst_wClk_50M_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/synth/risc_axi_v5_top_rst_wClk_50M_0.vhd:74] Parameter C_FAMILY bound to: zynq - type: string Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer Parameter C_EXT_RESET_HIGH bound to: 1'b0 Parameter C_AUX_RESET_HIGH bound to: 1'b0 Parameter C_NUM_BUS_RST bound to: 1 - type: integer Parameter C_NUM_PERP_RST bound to: 1 - type: integer Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer INFO: [Synth 8-3491] module 'proc_sys_reset' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/synth/risc_axi_v5_top_rst_wClk_50M_0.vhd:129] INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481] INFO: [Synth 8-638] synthesizing module 'lpf' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816] INFO: [Synth 8-3491] module 'SRL16' declared at 'C:/Xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:100945' bound to instance 'POR_SRL_I' of component 'SRL16' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868] INFO: [Synth 8-6157] synthesizing module 'SRL16' [C:/Xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:100945] INFO: [Synth 8-6155] done synthesizing module 'SRL16' (48#1) [C:/Xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:100945] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized0' (48#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-256] done synthesizing module 'lpf' (49#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816] INFO: [Synth 8-638] synthesizing module 'sequence_psr' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301] INFO: [Synth 8-638] synthesizing module 'upcnt_n' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125] INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (50#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125] INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (51#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301] INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (52#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323] INFO: [Synth 8-256] done synthesizing module 'risc_axi_v5_top_rst_wClk_50M_0' (53#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/synth/risc_axi_v5_top_rst_wClk_50M_0.vhd:74] WARNING: [Synth 8-7071] port 'mb_reset' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:506] WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:506] WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:506] WARNING: [Synth 8-7071] port 'interconnect_aresetn' of module 'risc_axi_v5_top_rst_wClk_50M_0' is unconnected for instance 'rst_wClk_50M' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:506] WARNING: [Synth 8-7023] instance 'rst_wClk_50M' of module 'risc_axi_v5_top_rst_wClk_50M_0' has 10 connections declared, but only 6 given [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:506] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top' (54#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/synth/risc_axi_v5_top.v:291] INFO: [Synth 8-6155] done synthesizing module 'risc_axi_v5_top_wrapper' (55#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hdl/risc_axi_v5_top_wrapper.v:12] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1301.613 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0_board.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0_board.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/risc_axi_v5_top_rst_wClk_50M_0.xdc] for cell 'risc_axi_v5_top_i/rst_wClk_50M/U0' Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_board.xdc] for cell 'risc_axi_v5_top_i/axi_uartlite_0/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_board.xdc] for cell 'risc_axi_v5_top_i/axi_uartlite_0/U0' Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0.xdc] for cell 'risc_axi_v5_top_i/axi_uartlite_0/U0' Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0.xdc] for cell 'risc_axi_v5_top_i/axi_uartlite_0/U0' Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc] Finished Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/constrs_1/new/zynq.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/risc_axi_v5_top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1301.613 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 19 instances were transformed. FDR => FDRE: 18 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1301.613 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/rst_wClk_50M/U0. (constraint file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc, line 36). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/axi_uartlite_0/U0. (constraint file D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/dont_touch.xdc, line 42). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0/inst/ram. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/rst_wClk_50M. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/led_key_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/axi_uartlite_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for risc_axi_v5_top_i/riscv_core_with_axi_0. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'riscv_core_v5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- sm_idle | 0010 | 00 sm_read | 1000 | 01 sm_write | 0100 | 10 sm_resp | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0000 | 0001 iSTATE1 | 0001 | 0010 iSTATE0 | 0010 | 0011 iSTATE | 0011 | 0100 iSTATE7 | 0100 | 0101 iSTATE6 | 0101 | 0110 iSTATE4 | 0110 | 0111 iSTATE5 | 0111 | 1000 iSTATE3 | 1000 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'riscv_core_v5' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 64 Bit Adders := 1 2 Input 64 Bit Adders := 1 2 Input 32 Bit Adders := 9 3 Input 32 Bit Adders := 1 2 Input 6 Bit Adders := 2 2 Input 5 Bit Adders := 1 3 Input 5 Bit Adders := 2 2 Input 3 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 2 2 Input 1 Bit XORs := 1 +---Registers : 64 Bit Registers := 4 36 Bit Registers := 2 32 Bit Registers := 19 16 Bit Registers := 2 6 Bit Registers := 2 5 Bit Registers := 6 4 Bit Registers := 3 3 Bit Registers := 6 2 Bit Registers := 7 1 Bit Registers := 82 +---RAMs : 1024 Bit (32 X 32 bit) RAMs := 2 +---Muxes : 2 Input 64 Bit Muxes := 5 2 Input 36 Bit Muxes := 2 2 Input 32 Bit Muxes := 44 10 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 12 3 Input 32 Bit Muxes := 4 8 Input 32 Bit Muxes := 3 6 Input 32 Bit Muxes := 1 2 Input 30 Bit Muxes := 1 2 Input 24 Bit Muxes := 4 3 Input 24 Bit Muxes := 2 4 Input 24 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 4 Input 8 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 9 8 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 6 Input 5 Bit Muxes := 1 3 Input 5 Bit Muxes := 2 4 Input 4 Bit Muxes := 2 2 Input 4 Bit Muxes := 19 7 Input 4 Bit Muxes := 1 8 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 3 9 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 4 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 4 8 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 182 8 Input 1 Bit Muxes := 2 7 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 1 10 Input 1 Bit Muxes := 1 9 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[31] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[31]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[31] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[31] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[30] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[30]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[30] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[30] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[29] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[29]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[29] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[29] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[28] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[28]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[28] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[28] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[27] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[27]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[27] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[27] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[26] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[26]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[26] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[26] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[25] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[25]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[25] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[25] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[24] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[24]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[24] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[24] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[23] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[23]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[23] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[23] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[22] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[22]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[22] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[22] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[21] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[21]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[21] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[21] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[20] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[20]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[20] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[20] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[19] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[19]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[19] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[19] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[18] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[18]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[18] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[18] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[17] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[17]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[17] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[17] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[16] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[16]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[16] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[16] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[15] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[15]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[15] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[15] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[14] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[14]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[14] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[14] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[13] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[13]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[13] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[13] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[12] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[12]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[12] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[12] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[11] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[11]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[11] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[11] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[10] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[10]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[10] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[10] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[9] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[9]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[9] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[9] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[8] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[8]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[8] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[8] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[7] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[7]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[7] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[7] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[6] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[6]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[6] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[6] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[5] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[5]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[5] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[5] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[4] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[4]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[4] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[4] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[3] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[3]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[3] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[3] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[2] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[2]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[2] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[2] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[1] with 1st driver pin 'risc_axi_v5_top_i/riscv_core_with_axi_0/inst/m00_axi_awaddr0_inferred/axi_awaddr[1]' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin m00_axi_awaddr[1] with 2nd driver pin 'GND' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] CRITICAL WARNING: [Synth 8-6858] multi-driven net m00_axi_awaddr[1] is connected to at least one constant driver which has been preserved, other driver is ignored [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v:144] --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +----------------------------------------+---------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------+---------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/regs/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/regs2/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +----------------------------------------+---------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +----------------------------------------+---------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------+---------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/regs/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |risc_axi_v5_top_i/riscv_core_with_axi_0 | inst/regs2/regs_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +----------------------------------------+---------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance risc_axi_v5_top_i/riscv_core_with_axi_0/inst/regs/regs_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance risc_axi_v5_top_i/riscv_core_with_axi_0/inst/regs2/regs_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-------------+--------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-------------+--------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |axi_uartlite | UARTLITE_CORE_I/UARTLITE_RX_I/data_shift_reg[15] | 16 | 1 | YES | NO | YES | 1 | 0 | |axi_uartlite | UARTLITE_CORE_I/UARTLITE_TX_I/data_shift_reg[15] | 15 | 1 | YES | NO | YES | 1 | 0 | +-------------+--------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Dynamic Shift Register Report: +------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+ |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | +------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+ |dsrl | INFERRED_GEN.data_reg[15] | 8 | 8 | 8 | 0 | 0 | 0 | 0 | +------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |CARRY4 | 174| |3 |LUT1 | 145| |4 |LUT2 | 246| |5 |LUT3 | 317| |6 |LUT4 | 245| |7 |LUT5 | 512| |8 |LUT6 | 1482| |9 |RAMB18E1 | 2| |10 |RAMB36E1 | 1| |11 |SRL16 | 1| |12 |SRL16E | 18| |13 |FDR | 8| |14 |FDRE | 806| |15 |FDSE | 53| |16 |IBUF | 3| |17 |OBUF | 5| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1301.613 ; gain = 166.848 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 93 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:46 . Memory (MB): peak = 1301.613 ; gain = 166.848 Synthesis Optimization Complete : Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 1301.613 ; gain = 166.848 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1301.613 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 186 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1301.613 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 9 instances were transformed. FDR => FDRE: 8 instances SRL16 => SRL16E: 1 instance Synth Design complete, checksum: 2970f702 INFO: [Common 17-83] Releasing license: Synthesis 193 Infos, 23 Warnings, 93 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 1301.613 ; gain = 166.848 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/synth_1/risc_axi_v5_top_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file risc_axi_v5_top_wrapper_utilization_synth.rpt -pb risc_axi_v5_top_wrapper_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Sep 14 06:27:24 2021...