Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date         : Mon Sep 13 21:27:02 2021
| Host         : DESKTOP-I91JIJO running 64-bit major release  (build 9200)
| Command      : report_drc -file risc_axi_v5_top_wrapper_drc_opted.rpt -pb risc_axi_v5_top_wrapper_drc_opted.pb -rpx risc_axi_v5_top_wrapper_drc_opted.rpx
| Design       : risc_axi_v5_top_wrapper
| Device       : xc7z020clg400-2
| Speed File   : -2
| Design State : Synthesized
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 1
+--------+----------+--------------------+------------+
| Rule   | Severity | Description        | Violations |
+--------+----------+--------------------+------------+
| ZPS7-1 | Warning  | PS7 block required | 1          |
+--------+----------+--------------------+------------+

2. REPORT DETAILS
-----------------
ZPS7-1#1 Warning
PS7 block required  
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>