# compile vhdl design source files
vhdl xil_defaultlib  \
"../../../../riscv_axi_v5.ip_user_files/bd/risc_axi_v5_top/ip/risc_axi_v5_top_rst_wClk_50M_0/sim/risc_axi_v5_top_rst_wClk_50M_0.vhd" \

# Do not sort compile order
nosort