diff --git a/bsp/essemi/es8p508x/SConscript b/bsp/essemi/es8p508x/SConscript index df4aa532bead4509e75228f6d271fba8b11d1b32..11d722608a44e2e6ea508de14d4618c41740ca16 100644 --- a/bsp/essemi/es8p508x/SConscript +++ b/bsp/essemi/es8p508x/SConscript @@ -1,8 +1,9 @@ # RT-Thread SConscript bridge import os +from building import * objs = [] -cwd = GetCurrentDir() +cwd = GetCurrentDir() list = os.listdir(cwd) for d in list: diff --git a/bsp/imx6ul/SConstruct b/bsp/imx6ul/SConstruct index 9483ea927d0fd610de84b9db00da263c9492e7f0..8c9e4ee3476083cbd61c3b353405bb5eae7e38f3 100644 --- a/bsp/imx6ul/SConstruct +++ b/bsp/imx6ul/SConstruct @@ -20,6 +20,7 @@ env = Environment(tools = ['mingw'], AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] Export('RTT_ROOT') Export('rtconfig') diff --git a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.py b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.py index 44de4dc1dff582dfa99b679259cce07726a5a4e7..1c90a8bdaae1e9f81d6270caa90bfebe90bd26af 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.py +++ b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.py @@ -53,6 +53,9 @@ if PLATFORM == 'gcc': CPATH = '' LPATH = '' + AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + AFLAGS += ' -D__STARTUP_CLEAR_BSS' + if BUILD == 'debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' @@ -60,7 +63,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2 -Os' - POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' # module setting CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' diff --git a/bsp/imxrt/imxrt1064-nxp-evk/README.md b/bsp/imxrt/imxrt1064-nxp-evk/README.md index 434f13c651b39b3ef4fe690ce6b5a1464db2c42e..37a5e3d1dd03ab6984fdd002cc120a8c33f345b9 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/README.md +++ b/bsp/imxrt/imxrt1064-nxp-evk/README.md @@ -71,7 +71,7 @@ ### 快速上手 -本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，暂不支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，以及GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 #### 硬件连接 @@ -115,4 +115,4 @@ msh > 维护人: -- [王强](https://github.com/xfwangqiang), 邮箱：<164877907@qq.com> \ No newline at end of file +- [王强](https://github.com/xfwangqiang, https://gitee.com/xfwangqiang), 邮箱：<164877907@qq.com> \ No newline at end of file diff --git a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py index 2acb77e3edc5f26142348dd9a806ca692c42bc15..eeef72b0c6fb657d0357d7aa659d84542f356724 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py +++ b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py @@ -53,6 +53,9 @@ if PLATFORM == 'gcc': CPATH = '' LPATH = '' + AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + AFLAGS += ' -D__STARTUP_CLEAR_BSS' + if BUILD == 'debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' diff --git a/bsp/nrf5x/libraries/drivers/SConscript b/bsp/nrf5x/libraries/drivers/SConscript index 6bbdffce071f3296905d254ffe8dd095eca6c295..b446b7c3b4345749c4ba572fb4cd85d5a68810e4 100644 --- a/bsp/nrf5x/libraries/drivers/SConscript +++ b/bsp/nrf5x/libraries/drivers/SConscript @@ -19,8 +19,12 @@ if GetDepend(['BSP_USING_QSPI_FLASH']): if GetDepend(['BSP_USING_SPI']): src += ['drv_spi.c'] + if GetDepend(['BSP_USING_GPIO']): src += ['drv_gpio.c'] + +if GetDepend(['BSP_USING_PWM']): + src += ['drv_pwm.c'] path = [cwd] diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.c b/bsp/nrf5x/libraries/drivers/drv_gpio.c index 001839b2b4faa2ff85e3cc6aab0d6918e13b2efd..3084fbc0439efab58a3c6a438c4ccf7c2bbedc2e 100644 --- a/bsp/nrf5x/libraries/drivers/drv_gpio.c +++ b/bsp/nrf5x/libraries/drivers/drv_gpio.c @@ -46,22 +46,6 @@ static const struct pin_index pins[] = __NRF5X_PIN(29, 0, 29), __NRF5X_PIN(30, 0, 30), __NRF5X_PIN(31, 0, 31), - __NRF5X_PIN(32, 1, 0 ), - __NRF5X_PIN(33, 1, 1 ), - __NRF5X_PIN(34, 1, 2 ), - __NRF5X_PIN(35, 1, 3 ), - __NRF5X_PIN(36, 1, 4 ), - __NRF5X_PIN(37, 1, 5 ), - __NRF5X_PIN(38, 1, 6 ), - __NRF5X_PIN(39, 1, 7 ), - __NRF5X_PIN(40, 1, 8 ), - __NRF5X_PIN(41, 1, 9 ), - __NRF5X_PIN(42, 1, 10), - __NRF5X_PIN(43, 1, 11), - __NRF5X_PIN(44, 1, 12), - __NRF5X_PIN(45, 1, 13), - __NRF5X_PIN(46, 1, 14), - __NRF5X_PIN(47, 1, 15), }; /* EVENTS_IN[n](n=0..7) and EVENTS_PORT */ diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.h b/bsp/nrf5x/libraries/drivers/drv_gpio.h index 28eca1a810f81dd0fc8a12b85168b0c8c5769eb1..bb04697ab53ec20061ae7a287e53983ce9cb1c37 100644 --- a/bsp/nrf5x/libraries/drivers/drv_gpio.h +++ b/bsp/nrf5x/libraries/drivers/drv_gpio.h @@ -13,7 +13,6 @@ #include #include -#include #include #include diff --git a/bsp/nrf5x/libraries/drivers/drv_pwm.c b/bsp/nrf5x/libraries/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..4d7c036ce58e344ffd7e159a744c8f4e7ab67782 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_pwm.c @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 supperthomas first version + * + */ + + +#include +#include "rtdevice.h" +#include "rtservice.h" + +#ifdef RT_USING_PWM + +#include + +struct mcu_pwm +{ + struct rt_device_pwm pwm_device; + + nrfx_pwm_t *pwm_handle; + nrf_pwm_values_individual_t m_demo1_seq_values; + nrf_pwm_sequence_t m_demo1_seq; + + rt_uint8_t channel; + char *name; + rt_uint64_t pwm_src_clk; + uint8_t channel_0_pin; + uint8_t channel_1_pin; + uint8_t channel_2_pin; + uint8_t channel_3_pin; +}; + +enum +{ +#ifdef BSP_USING_PWM0 + PWM0_INDEX, +#endif +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +}; +#ifdef BSP_USING_PWM0 +static nrfx_pwm_t m_pwm0 = NRFX_PWM_INSTANCE(0); +#define PWM0_CONFIG \ + { \ + .pwm_handle = &m_pwm0, \ + .name = "pwm0", \ + .pwm_src_clk = 1000000, \ + } +#endif + +#ifdef BSP_USING_PWM1 +static nrfx_pwm_t m_pwm1 = NRFX_PWM_INSTANCE(1); +#define PWM1_CONFIG \ + { \ + .pwm_handle = &m_pwm1, \ + .name = "pwm1", \ + .pwm_src_clk = 1000000, \ + } +#endif + +#ifdef BSP_USING_PWM2 +static nrfx_pwm_t m_pwm2 = NRFX_PWM_INSTANCE(2); +#define PWM2_CONFIG \ + { \ + .pwm_handle = &m_pwm2, \ + .name = "pwm2", \ + .pwm_src_clk = 1000000, \ + } +#endif + +#ifdef BSP_USING_PWM3 +static nrfx_pwm_t m_pwm3 = NRFX_PWM_INSTANCE(3); +#define PWM3_CONFIG \ + { \ + .pwm_handle = &m_pwm3, \ + .name = "pwm3", \ + .pwm_src_clk = 1000000, \ + } +#endif + +static struct mcu_pwm mcu_pwm_obj[] = +{ +#ifdef BSP_USING_PWM0 + PWM0_CONFIG, +#endif +#ifdef BSP_USING_PWM1 + PWM1_CONFIG, +#endif + +#ifdef BSP_USING_PWM2 + PWM2_CONFIG, +#endif + +#ifdef BSP_USING_PWM3 + PWM3_CONFIG, +#endif +}; + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); +static struct rt_pwm_ops drv_ops = +{ + drv_pwm_control +}; + +static rt_err_t drv_pwm_enable(struct mcu_pwm *p_mcu, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + if (!enable) + { + nrfx_pwm_stop(p_mcu->pwm_handle, true); + } + else + { + (void)nrfx_pwm_simple_playback(p_mcu->pwm_handle, &p_mcu->m_demo1_seq, 1, NRFX_PWM_FLAG_LOOP); + } + + return RT_EOK; +} + +uint8_t mcu_get_channel_number(uint8_t channel) +{ + if (channel & 0x01) + { + return 0; + } + else if (channel & 0x02) + { + return 1; + } + else if (channel & 0x04) + { + return 2; + } + else if (channel & 0x08) + { + return 3; + } + return 0; +} + +static rt_err_t drv_pwm_get(struct mcu_pwm *pwm_handle, struct rt_pwm_configuration *configuration) +{ + rt_uint8_t channel_number = mcu_get_channel_number(configuration->channel); + uint8_t tick_pscond; + + tick_pscond = pwm_handle->pwm_src_clk / 1000000UL; + configuration->period = pwm_handle->pwm_handle->p_registers->COUNTERTOP * 1000UL / tick_pscond; + configuration->pulse = pwm_handle->pwm_handle->p_registers->SEQ[channel_number].PTR / tick_pscond; + + return RT_EOK; +} + +static void nrfx_set_prioid(nrfx_pwm_t *pwm_handle, uint32_t perioid) +{ + pwm_handle->p_registers->COUNTERTOP = perioid; +} + +static rt_err_t drv_pwm_set(struct mcu_pwm *p_mcu, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + uint8_t tick_pscond; + tick_pscond = p_mcu->pwm_src_clk / 1000000UL; + + p_mcu->pwm_handle->p_registers->COUNTERTOP = (unsigned long long)configuration->period * tick_pscond; + if (configuration->channel & 0x01) + { + p_mcu->m_demo1_seq_values.channel_0 = configuration->pulse; + } + + if (configuration->channel & 0x02) + { + p_mcu->m_demo1_seq_values.channel_1 = configuration->pulse; + } + + if (configuration->channel & 0x04) + { + p_mcu->m_demo1_seq_values.channel_2 = configuration->pulse; + } + + if (configuration->channel & 0x08) + { + p_mcu->m_demo1_seq_values.channel_3 = configuration->pulse; + } + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + void *pwm_handle = (void *)device->parent.user_data; + nrfx_pwm_t *p_handle = (nrfx_pwm_t *)pwm_handle; + struct mcu_pwm *p_mcu = rt_container_of(p_handle, struct mcu_pwm, pwm_handle); + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(p_mcu, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(p_mcu, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(p_mcu, configuration); + case PWM_CMD_GET: + return drv_pwm_get(p_mcu, configuration); + default: + return RT_EINVAL; + } +} + +static rt_err_t mcu_hw_pwm_init(struct mcu_pwm *device) +{ +#define NRFX_PWM_PIN_INVERTED 0x80 +#define _PRIO_APP_LOWEST 7 + nrfx_pwm_config_t config0 = + { + .irq_priority = _PRIO_APP_LOWEST, + .base_clock = NRF_PWM_CLK_1MHz, //default value + .count_mode = NRF_PWM_MODE_UP, + .top_value = 5000, //default vaule + .load_mode = NRF_PWM_LOAD_INDIVIDUAL, + .step_mode = NRF_PWM_STEP_AUTO + }; + rt_err_t result = RT_EOK; + if (device->pwm_src_clk == 1000000) + { + config0.base_clock = NRF_PWM_CLK_1MHz; + } + else if (device->pwm_src_clk == 2000000) + { + config0.base_clock = NRF_PWM_CLK_2MHz; + } + else if (device->pwm_src_clk == 8000000) + { + config0.base_clock = NRF_PWM_CLK_8MHz; + } + else + { + config0.base_clock = NRF_PWM_CLK_1MHz; + } + + if (device->channel & 0x01) + { + config0.output_pins[0] = device->channel_0_pin | NRFX_PWM_PIN_INVERTED; + } + + if (device->channel & 0x02) + { + config0.output_pins[1] = device->channel_1_pin | NRFX_PWM_PIN_INVERTED; + } + + if (device->channel & 0x04) + { + config0.output_pins[2] = device->channel_2_pin | NRFX_PWM_PIN_INVERTED; + } + + if (device->channel & 0x08) + { + config0.output_pins[3] = device->channel_3_pin | NRFX_PWM_PIN_INVERTED; + } + device->m_demo1_seq.values.p_individual = &device->m_demo1_seq_values; + device->m_demo1_seq.length = NRF_PWM_VALUES_LENGTH(device->m_demo1_seq_values), + nrfx_pwm_init(device->pwm_handle, &config0, NULL, NULL); + return result; +} + +static void pwm_get_channel(void) +{ +#ifdef BSP_USING_PWM0_CH0 + mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 0; + mcu_pwm_obj[PWM0_INDEX].channel_0_pin = BSP_USING_PWM0_CH0; +#endif +#ifdef BSP_USING_PWM0_CH1 + mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 1; + mcu_pwm_obj[PWM0_INDEX].channel_1_pin = BSP_USING_PWM0_CH1; +#endif +#ifdef BSP_USING_PWM0_CH2 + mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 2; + mcu_pwm_obj[PWM0_INDEX].channel_2_pin = BSP_USING_PWM0_CH2; +#endif +#ifdef BSP_USING_PWM0_CH3 + mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 3; + mcu_pwm_obj[PWM0_INDEX].channel_3_pin = BSP_USING_PWM0_CH3; +#endif +#ifdef BSP_USING_PWM1_CH0 + mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 0; + mcu_pwm_obj[PWM1_INDEX].channel_0_pin = BSP_USING_PWM1_CH0; +#endif +#ifdef BSP_USING_PWM1_CH1 + mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 1; + mcu_pwm_obj[PWM1_INDEX].channel_1_pin = BSP_USING_PWM1_CH1; +#endif +#ifdef BSP_USING_PWM1_CH2 + mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 2; + mcu_pwm_obj[PWM1_INDEX].channel_2_pin = BSP_USING_PWM1_CH2; +#endif +#ifdef BSP_USING_PWM1_CH3 + mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 3; + mcu_pwm_obj[PWM1_INDEX].channel_3_pin = BSP_USING_PWM1_CH3; +#endif +#ifdef BSP_USING_PWM2_CH0 + mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 0; + mcu_pwm_obj[PWM2_INDEX].channel_0_pin = BSP_USING_PWM2_CH0; +#endif +#ifdef BSP_USING_PWM2_CH1 + mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 1; + mcu_pwm_obj[PWM2_INDEX].channel_1_pin = BSP_USING_PWM2_CH1; +#endif +#ifdef BSP_USING_PWM2_CH2 + mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 2; + mcu_pwm_obj[PWM2_INDEX].channel_2_pin = BSP_USING_PWM2_CH2; +#endif +#ifdef BSP_USING_PWM2_CH3 + mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 3; + mcu_pwm_obj[PWM2_INDEX].channel_3_pin = BSP_USING_PWM2_CH3; +#endif +#ifdef BSP_USING_PWM3_CH0 + mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 0; + mcu_pwm_obj[PWM3_INDEX].channel_0_pin = BSP_USING_PWM3_CH0; +#endif +#ifdef BSP_USING_PWM3_CH1 + mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 1; + mcu_pwm_obj[PWM3_INDEX].channel_1_pin = BSP_USING_PWM3_CH1; +#endif +#ifdef BSP_USING_PWM3_CH2 + mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 2; + mcu_pwm_obj[PWM3_INDEX].channel_2_pin = BSP_USING_PWM3_CH2; +#endif +#ifdef BSP_USING_PWM3_CH3 + mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 3; + mcu_pwm_obj[PWM3_INDEX].channel_3_pin = BSP_USING_PWM3_CH3; +#endif +} + +static int mcu_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + pwm_get_channel(); + for (i = 0; i < sizeof(mcu_pwm_obj) / sizeof(mcu_pwm_obj[0]); i++) + { + /* pwm init */ + if (mcu_hw_pwm_init(&mcu_pwm_obj[i]) != RT_EOK) + { + rt_kprintf("\r\n %s init failed", mcu_pwm_obj[i].name); + result = -RT_ERROR; + goto __exit; + } + else + { + rt_kprintf("\r\n %s init success", mcu_pwm_obj[i].name); + + /* register pwm device */ + if (rt_device_pwm_register(&mcu_pwm_obj[i].pwm_device, mcu_pwm_obj[i].name, &drv_ops, &mcu_pwm_obj[i].pwm_handle) == RT_EOK) + { + rt_kprintf("\r\n %s register success", mcu_pwm_obj[i].name); + } + else + { + rt_kprintf("\r\n %s register failed", mcu_pwm_obj[i].name); + result = -RT_ERROR; + } + } + } +__exit: + return result; +} +INIT_DEVICE_EXPORT(mcu_pwm_init); + + + +/* test example */ +#define PWM_DEV_NAME "pwm0" /* PWM name*/ +#define PWM_DEV_CHANNEL 15 /* PWM channel */ + +struct rt_device_pwm *pwm_dev; + +static int pwm_led_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse, dir; + + period = 50000; /* 50ms*/ + dir = 1; + pulse = 0; + + + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + + while (1) + { + rt_thread_mdelay(50); + if (dir) + { + pulse += 500; + } + else + { + pulse -= 500; + } + if (pulse >= period) + { + dir = 0; + } + if (0 == pulse) + { + dir = 1; + } + + + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + } +} +MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +#endif \ No newline at end of file diff --git a/bsp/nrf5x/nrf52832/.config b/bsp/nrf5x/nrf52832/.config index 385179fda93d3c72bae97c95318d3709f9c61eba..0638293bd54582aea735de385a37302d27d480c6 100644 --- a/bsp/nrf5x/nrf52832/.config +++ b/bsp/nrf5x/nrf52832/.config @@ -74,7 +74,9 @@ CONFIG_RT_VER_NUM=0x40003 # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y -# CONFIG_RT_USING_USER_MAIN is not set +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -112,7 +114,7 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set @@ -120,6 +122,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -192,12 +195,15 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -224,6 +230,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -236,9 +243,10 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -257,6 +265,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set # # security packages @@ -265,6 +274,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -299,6 +309,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set # # system packages @@ -309,6 +321,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -321,6 +334,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set # # peripheral libraries and drivers @@ -338,6 +354,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +CONFIG_PKG_USING_NRFX=y +CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" +CONFIG_PKG_USING_NRFX_V210=y +# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set +CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set @@ -355,13 +378,19 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set # CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_NORDIC_SDK is not set -# CONFIG_PKG_USING_NORDIC_SDK_V100 is not set -# CONFIG_PKG_USING_NORDIC_SDK_LATEST_VERSION is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set # # miscellaneous packages @@ -398,17 +427,39 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set # # Hardware Drivers Config # CONFIG_SOC_NRF52832=y +CONFIG_SOC_NORDIC=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_JLINK_TO_USART is not set +# CONFIG_BSP_USING_QSPI_FLASH is not set # # On-chip Peripheral Drivers # +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_SOFTDEVICE is not set CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_PIN=8 +CONFIG_BSP_UART0_TX_PIN=6 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set + +# +# On-chip flash config +# +CONFIG_MCU_FLASH_START_ADDRESS=0x00000000 +CONFIG_MCU_FLASH_SIZE_KB=1024 +CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 +CONFIG_MCU_SRAM_SIZE_KB=256 +CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 diff --git a/bsp/nrf5x/nrf52832/SConstruct b/bsp/nrf5x/nrf52832/SConstruct index 20d41c40aecae145168c5e333b42b915be3361b5..2ac1ce6674022e47bea090dc83914a90f23765e0 100644 --- a/bsp/nrf5x/nrf52832/SConstruct +++ b/bsp/nrf5x/nrf52832/SConstruct @@ -50,5 +50,8 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) +# include cmsis +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript'))) + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/nrf5x/nrf52832/applications/application.c b/bsp/nrf5x/nrf52832/applications/application.c index 1135d82e16ce7d6c719feaeffe60099421eded18..3e29eeeac3b469da964fa46b055b820ee076e350 100644 --- a/bsp/nrf5x/nrf52832/applications/application.c +++ b/bsp/nrf5x/nrf52832/applications/application.c @@ -1,48 +1,32 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2015-03-01 Yangfs the first version - * 2015-03-27 Bernard code cleanup. - */ - -/** - * @addtogroup NRF52832 + * 2020-04-29 supperthomas first version + * */ -/*@{*/ #include +#include +#define DK_BOARD_LED_1 17 +#define DK_BOARD_LED_2 18 -#ifdef RT_USING_FINSH -#include -#include -#endif - -void rt_init_thread_entry(void* parameter) +int main(void) { - extern rt_err_t ble_init(void); - - ble_init(); + int count = 1; + rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(DK_BOARD_LED_1, PIN_HIGH); + rt_thread_mdelay(500); + + rt_pin_write(DK_BOARD_LED_1, PIN_LOW); + rt_thread_mdelay(500); + } + return RT_EOK; } -int rt_application_init(void) -{ - rt_thread_t tid; - - tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, - RT_THREAD_PRIORITY_MAX / 3, 20); - if (tid != RT_NULL) - rt_thread_startup(tid); - - return 0; -} - - -/*@}*/ diff --git a/bsp/nrf5x/nrf52832/applications/ble_nus_app.c b/bsp/nrf5x/nrf52832/applications/ble_nus_app.c deleted file mode 100644 index f4a51493ed22ea8d34e6155a80a0e4b7c537fcea..0000000000000000000000000000000000000000 --- a/bsp/nrf5x/nrf52832/applications/ble_nus_app.c +++ /dev/null @@ -1,670 +0,0 @@ -#include "nordic_common.h" -#include "nrf.h" -#include "ble_hci.h" -#include "ble_advdata.h" -#include "ble_advertising.h" -#include "ble_conn_params.h" -#include "softdevice_handler.h" -#include "nrf_ble_gatt.h" -#include "app_timer.h" -#include "ble_nus.h" -#include "app_util_platform.h" - -#include - -typedef rt_size_t (*BLE_NOTIFY_T)(rt_uint8_t *buf, rt_uint16_t size); - -#define STACK_EVT_MQ_NUM 10 - -#define FAST_ADV() \ - do { \ - uint32_t err_code; \ - err_code = ble_advertising_start(BLE_ADV_MODE_FAST); \ - APP_ERROR_CHECK(err_code); \ - } while(0) - -typedef enum -{ - STACK_EV_DISCON = 1, - STACK_EV_DISPATCH = 2, - STACK_EV_KEY = 4, -} STACK_EV_E; - -typedef struct -{ - rt_list_t node; - void* evt; -} evt_list_t; - -typedef enum -{ - STACK_STATE_IDLE = 0, - STACK_STATE_ADV = 1, - STACK_STATE_CON = 2, - STACK_STATE_DISC = 3 -} STACK_STATE_E; - -STACK_STATE_E stack_state = STACK_STATE_IDLE; - -rt_event_t stack_event; -rt_sem_t sd_evt_sem; -rt_mq_t stack_evt_mq; -rt_uint8_t *evt_sample; - -BLE_NOTIFY_T rx_notify = RT_NULL; - -// Low frequency clock source to be used by the SoftDevice -#define NRF_CLOCK_LFCLKSRC {.source = NRF_CLOCK_LF_SRC_XTAL, \ - .rc_ctiv = 0, \ - .rc_temp_ctiv = 0, \ - .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM} - - -#define CONN_CFG_TAG 1 /**< A tag that refers to the BLE stack configuration we set with @ref sd_ble_cfg_set. Default tag is @ref BLE_CONN_CFG_TAG_DEFAULT. */ - -#define APP_FEATURE_NOT_SUPPORTED BLE_GATT_STATUS_ATTERR_APP_BEGIN + 2 /**< Reply when unsupported features are requested. */ - -#define DEVICE_NAME "Nordic_UART" /**< Name of device. Will be included in the advertising data. */ -#define NUS_SERVICE_UUID_TYPE BLE_UUID_TYPE_VENDOR_BEGIN /**< UUID type for the Nordic UART Service (vendor specific). */ - -#define APP_ADV_INTERVAL 64 /**< The advertising interval (in units of 0.625 ms. This value corresponds to 40 ms). */ -#define APP_ADV_TIMEOUT_IN_SECONDS 30 /**< The advertising timeout (in units of seconds). */ - -#define MIN_CONN_INTERVAL MSEC_TO_UNITS(20, UNIT_1_25_MS) /**< Minimum acceptable connection interval (20 ms), Connection interval uses 1.25 ms units. */ -#define MAX_CONN_INTERVAL MSEC_TO_UNITS(75, UNIT_1_25_MS) /**< Maximum acceptable connection interval (75 ms), Connection interval uses 1.25 ms units. */ -#define SLAVE_LATENCY 0 /**< Slave latency. */ -#define CONN_SUP_TIMEOUT MSEC_TO_UNITS(4000, UNIT_10_MS) /**< Connection supervisory timeout (4 seconds), Supervision Timeout uses 10 ms units. */ -#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */ -#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */ -#define MAX_CONN_PARAMS_UPDATE_COUNT 3 /**< Number of attempts before giving up the connection parameter negotiation. */ - -#define DEAD_BEEF 0xDEADBEEF /**< Value used as error code on stack dump, can be used to identify stack location on stack unwind. */ - -#define UART_TX_BUF_SIZE 256 /**< UART TX buffer size. */ -#define UART_RX_BUF_SIZE 256 /**< UART RX buffer size. */ - -static ble_nus_t m_nus; /**< Structure to identify the Nordic UART Service. */ -static uint16_t m_conn_handle = BLE_CONN_HANDLE_INVALID; /**< Handle of the current connection. */ - -static nrf_ble_gatt_t m_gatt; /**< GATT module instance. */ -static ble_uuid_t m_adv_uuids[] = {{BLE_UUID_NUS_SERVICE, NUS_SERVICE_UUID_TYPE}}; /**< Universally unique service identifier. */ -static uint16_t m_ble_nus_max_data_len = BLE_GATT_ATT_MTU_DEFAULT - 3; /**< Maximum length of data (in bytes) that can be transmitted to the peer by the Nordic UART service module. */ - -/**@brief Function for assert macro callback. - * - * @details This function will be called in case of an assert in the SoftDevice. - * - * @warning This handler is an example only and does not fit a final product. You need to analyse - * how your product is supposed to react in case of Assert. - * @warning On assert from the SoftDevice, the system can only recover on reset. - * - * @param[in] line_num Line number of the failing ASSERT call. - * @param[in] p_file_name File name of the failing ASSERT call. - */ -void assert_nrf_callback(uint16_t line_num, const uint8_t * p_file_name) -{ - app_error_handler(DEAD_BEEF, line_num, p_file_name); -} - - -/**@brief Function for the GAP initialization. - * - * @details This function will set up all the necessary GAP (Generic Access Profile) parameters of - * the device. It also sets the permissions and appearance. - */ -static void gap_params_init(void) -{ - uint32_t err_code; - ble_gap_conn_params_t gap_conn_params; - ble_gap_conn_sec_mode_t sec_mode; - - BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); - - err_code = sd_ble_gap_device_name_set(&sec_mode, - (const uint8_t *) DEVICE_NAME, - strlen(DEVICE_NAME)); - APP_ERROR_CHECK(err_code); - - memset(&gap_conn_params, 0, sizeof(gap_conn_params)); - - gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL; - gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL; - gap_conn_params.slave_latency = SLAVE_LATENCY; - gap_conn_params.conn_sup_timeout = CONN_SUP_TIMEOUT; - - err_code = sd_ble_gap_ppcp_set(&gap_conn_params); - APP_ERROR_CHECK(err_code); -} - - -/**@brief Function for handling the data from the Nordic UART Service. - * - * @details This function will process the data received from the Nordic UART BLE Service and send - * it to the UART module. - * - * @param[in] p_nus Nordic UART Service structure. - * @param[in] p_data Data to be send to UART module. - * @param[in] length Length of the data. - */ -/**@snippet [Handling the data received over BLE] */ -static void nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length) -{ - rt_kprintf("Received data from BLE NUS. Writing data on UART.\r\n"); - - for (uint32_t i = 0; i < length; i++) - { - rt_kprintf("%02x ", p_data[i]); - } - - // ble_send(p_data, length); - - if (rx_notify != RT_NULL) - { - rx_notify(p_data, length); - } -} -/**@snippet [Handling the data received over BLE] */ - - -/**@brief Function for initializing services that will be used by the application. - */ -static void services_init(void) -{ - uint32_t err_code; - ble_nus_init_t nus_init; - - memset(&nus_init, 0, sizeof(nus_init)); - - nus_init.data_handler = nus_data_handler; - - err_code = ble_nus_init(&m_nus, &nus_init); - APP_ERROR_CHECK(err_code); -} - - -/**@brief Function for handling an event from the Connection Parameters Module. - * - * @details This function will be called for all events in the Connection Parameters Module - * which are passed to the application. - * - * @note All this function does is to disconnect. This could have been done by simply setting - * the disconnect_on_fail config parameter, but instead we use the event handler - * mechanism to demonstrate its use. - * - * @param[in] p_evt Event received from the Connection Parameters Module. - */ -static void on_conn_params_evt(ble_conn_params_evt_t * p_evt) -{ - uint32_t err_code; - - if (p_evt->evt_type == BLE_CONN_PARAMS_EVT_FAILED) - { - err_code = sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_CONN_INTERVAL_UNACCEPTABLE); - APP_ERROR_CHECK(err_code); - } -} - - -/**@brief Function for handling errors from the Connection Parameters module. - * - * @param[in] nrf_error Error code containing information about what went wrong. - */ -static void conn_params_error_handler(uint32_t nrf_error) -{ - APP_ERROR_HANDLER(nrf_error); -} - - -/**@brief Function for initializing the Connection Parameters module. - */ -static void conn_params_init(void) -{ - uint32_t err_code; - ble_conn_params_init_t cp_init; - - memset(&cp_init, 0, sizeof(cp_init)); - - cp_init.p_conn_params = NULL; - cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY; - cp_init.next_conn_params_update_delay = NEXT_CONN_PARAMS_UPDATE_DELAY; - cp_init.max_conn_params_update_count = MAX_CONN_PARAMS_UPDATE_COUNT; - cp_init.start_on_notify_cccd_handle = BLE_GATT_HANDLE_INVALID; - cp_init.disconnect_on_fail = false; - cp_init.evt_handler = on_conn_params_evt; - cp_init.error_handler = conn_params_error_handler; - - err_code = ble_conn_params_init(&cp_init); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling advertising events. - * - * @details This function will be called for advertising events which are passed to the application. - * - * @param[in] ble_adv_evt Advertising event. - */ -static void on_adv_evt(ble_adv_evt_t ble_adv_evt) -{ - // uint32_t err_code; - - switch (ble_adv_evt) - { - case BLE_ADV_EVT_FAST: - // err_code = bsp_indication_set(BSP_INDICATE_ADVERTISING); - // APP_ERROR_CHECK(err_code); - stack_state = STACK_STATE_ADV; - rt_kprintf("ble fast advert\n"); - break; - case BLE_ADV_EVT_IDLE: - // sleep_mode_enter(); - stack_state = STACK_STATE_IDLE; - rt_kprintf("advert idle\n"); - break; - default: - break; - } -} - - -/**@brief Function for the application's SoftDevice event handler. - * - * @param[in] p_ble_evt SoftDevice event. - */ -static void on_ble_evt(ble_evt_t * p_ble_evt) -{ - uint32_t err_code; - - switch (p_ble_evt->header.evt_id) - { - case BLE_GAP_EVT_CONNECTED: - // err_code = bsp_indication_set(BSP_INDICATE_CONNECTED); - // APP_ERROR_CHECK(err_code); - m_conn_handle = p_ble_evt->evt.gap_evt.conn_handle; - stack_state = STACK_STATE_CON; - rt_kprintf("Connected\r\n"); - break; // BLE_GAP_EVT_CONNECTED - - case BLE_GAP_EVT_DISCONNECTED: - // err_code = bsp_indication_set(BSP_INDICATE_IDLE); - // APP_ERROR_CHECK(err_code); - m_conn_handle = BLE_CONN_HANDLE_INVALID; - stack_state = STACK_STATE_DISC; - rt_kprintf("Disconnected\r\n"); - break; // BLE_GAP_EVT_DISCONNECTED - - case BLE_GAP_EVT_SEC_PARAMS_REQUEST: - // Pairing not supported - err_code = sd_ble_gap_sec_params_reply(m_conn_handle, BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, NULL, NULL); - APP_ERROR_CHECK(err_code); - break; // BLE_GAP_EVT_SEC_PARAMS_REQUEST - - case BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST: - { - ble_gap_data_length_params_t dl_params; - - // Clearing the struct will effectivly set members to @ref BLE_GAP_DATA_LENGTH_AUTO - memset(&dl_params, 0, sizeof(ble_gap_data_length_params_t)); - err_code = sd_ble_gap_data_length_update(p_ble_evt->evt.gap_evt.conn_handle, &dl_params, NULL); - APP_ERROR_CHECK(err_code); - } break; - - case BLE_GATTS_EVT_SYS_ATTR_MISSING: - // No system attributes have been stored. - err_code = sd_ble_gatts_sys_attr_set(m_conn_handle, NULL, 0, 0); - APP_ERROR_CHECK(err_code); - break; // BLE_GATTS_EVT_SYS_ATTR_MISSING - - case BLE_GATTC_EVT_TIMEOUT: - // Disconnect on GATT Client timeout event. - err_code = sd_ble_gap_disconnect(p_ble_evt->evt.gattc_evt.conn_handle, - BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); - APP_ERROR_CHECK(err_code); - break; // BLE_GATTC_EVT_TIMEOUT - - case BLE_GATTS_EVT_TIMEOUT: - // Disconnect on GATT Server timeout event. - err_code = sd_ble_gap_disconnect(p_ble_evt->evt.gatts_evt.conn_handle, - BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); - APP_ERROR_CHECK(err_code); - break; // BLE_GATTS_EVT_TIMEOUT - - case BLE_EVT_USER_MEM_REQUEST: - err_code = sd_ble_user_mem_reply(p_ble_evt->evt.gattc_evt.conn_handle, NULL); - APP_ERROR_CHECK(err_code); - break; // BLE_EVT_USER_MEM_REQUEST - - case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST: - { - ble_gatts_evt_rw_authorize_request_t req; - ble_gatts_rw_authorize_reply_params_t auth_reply; - - req = p_ble_evt->evt.gatts_evt.params.authorize_request; - - if (req.type != BLE_GATTS_AUTHORIZE_TYPE_INVALID) - { - if ((req.request.write.op == BLE_GATTS_OP_PREP_WRITE_REQ) || - (req.request.write.op == BLE_GATTS_OP_EXEC_WRITE_REQ_NOW) || - (req.request.write.op == BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL)) - { - if (req.type == BLE_GATTS_AUTHORIZE_TYPE_WRITE) - { - auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE; - } - else - { - auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_READ; - } - auth_reply.params.write.gatt_status = APP_FEATURE_NOT_SUPPORTED; - err_code = sd_ble_gatts_rw_authorize_reply(p_ble_evt->evt.gatts_evt.conn_handle, - &auth_reply); - APP_ERROR_CHECK(err_code); - } - } - } break; // BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST - - default: - // No implementation needed. - break; - } -} - - -/**@brief Function for dispatching a SoftDevice event to all modules with a SoftDevice - * event handler. - * - * @details This function is called from the SoftDevice event interrupt handler after a - * SoftDevice event has been received. - * - * @param[in] p_ble_evt SoftDevice event. - */ -static void ble_evt_dispatch(ble_evt_t * p_ble_evt) -{ - if (rt_mq_send(stack_evt_mq, p_ble_evt, p_ble_evt->header.evt_len) != RT_EOK) - { - rt_kprintf("dispatch malloc failure\n"); - } - else - { - rt_event_send(stack_event, STACK_EV_DISPATCH); - } -} - -static rt_err_t evt_dispatch_worker(void) -{ - ble_evt_t * p_ble_evt = (ble_evt_t *)evt_sample; - rt_err_t err; - - err = rt_mq_recv(stack_evt_mq, (void*)evt_sample, BLE_STACK_EVT_MSG_BUF_SIZE, RT_WAITING_NO); - - if (RT_EOK == err) - { - ble_conn_params_on_ble_evt(p_ble_evt); - nrf_ble_gatt_on_ble_evt(&m_gatt, p_ble_evt); - ble_nus_on_ble_evt(&m_nus, p_ble_evt); - on_ble_evt(p_ble_evt); - ble_advertising_on_ble_evt(p_ble_evt); - // bsp_btn_ble_on_ble_evt(p_ble_evt); - - rt_kprintf("ble evt dispatch\n"); - } - - return err; -} - -static uint32_t _softdevice_evt_schedule(void) -{ - rt_sem_release(sd_evt_sem); - - return NRF_SUCCESS; -} - -/**@brief Function for the SoftDevice initialization. - * - * @details This function initializes the SoftDevice and the BLE event interrupt. - */ -static void ble_stack_init(void) -{ - uint32_t err_code; - - nrf_clock_lf_cfg_t clock_lf_cfg = NRF_CLOCK_LFCLKSRC; - - // Initialize SoftDevice. - SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, _softdevice_evt_schedule); - - // Fetch the start address of the application RAM. - uint32_t ram_start = 0; - err_code = softdevice_app_ram_start_get(&ram_start); - APP_ERROR_CHECK(err_code); - - // Overwrite some of the default configurations for the BLE stack. - ble_cfg_t ble_cfg; - - // Configure the maximum number of connections. - memset(&ble_cfg, 0, sizeof(ble_cfg)); - ble_cfg.gap_cfg.role_count_cfg.periph_role_count = BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT; - ble_cfg.gap_cfg.role_count_cfg.central_role_count = 0; - ble_cfg.gap_cfg.role_count_cfg.central_sec_count = 0; - err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_cfg, ram_start); - APP_ERROR_CHECK(err_code); - - // Configure the maximum ATT MTU. - memset(&ble_cfg, 0x00, sizeof(ble_cfg)); - ble_cfg.conn_cfg.conn_cfg_tag = CONN_CFG_TAG; - ble_cfg.conn_cfg.params.gatt_conn_cfg.att_mtu = NRF_BLE_GATT_MAX_MTU_SIZE; - err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_cfg, ram_start); - APP_ERROR_CHECK(err_code); - - // Configure the maximum event length. - memset(&ble_cfg, 0x00, sizeof(ble_cfg)); - ble_cfg.conn_cfg.conn_cfg_tag = CONN_CFG_TAG; - ble_cfg.conn_cfg.params.gap_conn_cfg.event_length = 320; - ble_cfg.conn_cfg.params.gap_conn_cfg.conn_count = BLE_GAP_CONN_COUNT_DEFAULT; - err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_cfg, ram_start); - APP_ERROR_CHECK(err_code); - - // Enable BLE stack. - err_code = softdevice_enable(&ram_start); - APP_ERROR_CHECK(err_code); - - // Subscribe for BLE events. - err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for handling events from the GATT library. */ -static void gatt_evt_handler(nrf_ble_gatt_t * p_gatt, const nrf_ble_gatt_evt_t * p_evt) -{ - if ((m_conn_handle == p_evt->conn_handle) && (p_evt->evt_id == NRF_BLE_GATT_EVT_ATT_MTU_UPDATED)) - { - m_ble_nus_max_data_len = p_evt->params.att_mtu_effective - OPCODE_LENGTH - HANDLE_LENGTH; - rt_kprintf("Data len is set to 0x%X(%d)\r\n", m_ble_nus_max_data_len, m_ble_nus_max_data_len); - } - rt_kprintf("ATT MTU exchange completed. central 0x%x peripheral 0x%x\r\n", p_gatt->att_mtu_desired_central, p_gatt->att_mtu_desired_periph); -} - -/**@brief Function for initializing the GATT library. */ -static void gatt_init(void) -{ - ret_code_t err_code; - - err_code = nrf_ble_gatt_init(&m_gatt, gatt_evt_handler); - APP_ERROR_CHECK(err_code); - - err_code = nrf_ble_gatt_att_mtu_periph_set(&m_gatt, 64); - APP_ERROR_CHECK(err_code); -} - -/**@brief Function for initializing the Advertising functionality. - */ -static void advertising_init(void) -{ - uint32_t err_code; - ble_advdata_t advdata; - ble_advdata_t scanrsp; - ble_adv_modes_config_t options; - - // Build advertising data struct to pass into @ref ble_advertising_init. - memset(&advdata, 0, sizeof(advdata)); - advdata.name_type = BLE_ADVDATA_FULL_NAME; - advdata.include_appearance = false; - advdata.flags = BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE; - - memset(&scanrsp, 0, sizeof(scanrsp)); - scanrsp.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]); - scanrsp.uuids_complete.p_uuids = m_adv_uuids; - - memset(&options, 0, sizeof(options)); - options.ble_adv_fast_enabled = true; - options.ble_adv_fast_interval = APP_ADV_INTERVAL; - options.ble_adv_fast_timeout = APP_ADV_TIMEOUT_IN_SECONDS; - - err_code = ble_advertising_init(&advdata, &scanrsp, &options, on_adv_evt, NULL); - APP_ERROR_CHECK(err_code); - - ble_advertising_conn_cfg_tag_set(CONN_CFG_TAG); -} - -/**@brief Function for handling app_uart events. - * - * @details This function will receive a single character from the app_uart module and append it to - * a string. The string will be be sent over BLE when the last character received was a - * 'new line' '\n' (hex 0x0A) or if the string has reached the maximum data length. - */ -/**@snippet [Handling the data received over UART] */ -void uart_event_handle(rt_device_t uart) -{ - uint8_t data_array[BLE_NUS_MAX_DATA_LEN]; - rt_size_t size = 0; - uint32_t err_code; - - size = rt_device_read(uart, 0, data_array, BLE_NUS_MAX_DATA_LEN); - - if (size <= 0) - { - return; - } - - do - { - err_code = ble_nus_string_send(&m_nus, data_array, size); - if ( (err_code != NRF_ERROR_INVALID_STATE) && (err_code != NRF_ERROR_BUSY) ) - { - APP_ERROR_CHECK(err_code); - } - } while (err_code == NRF_ERROR_BUSY); -} -/**@snippet [Handling the data received over UART] */ - -/**@brief Function for initializing the UART module. - */ -/**@snippet [UART Initialization] */ -static rt_bool_t _stack_init(void) -{ - uint32_t err_code; - - stack_event = rt_event_create("stackev", RT_IPC_FLAG_FIFO); - sd_evt_sem = rt_sem_create("sdsem", 0, RT_IPC_FLAG_FIFO); - stack_evt_mq = rt_mq_create("stackmq", BLE_STACK_EVT_MSG_BUF_SIZE, STACK_EVT_MQ_NUM, RT_IPC_FLAG_FIFO); - evt_sample = rt_malloc(BLE_STACK_EVT_MSG_BUF_SIZE); - - if (!stack_event || !sd_evt_sem || !stack_evt_mq || !evt_sample) - { - rt_kprintf("uart rx sem create failure\n"); - return RT_FALSE; - } - - // Initialize. - err_code = app_timer_init(); - APP_ERROR_CHECK(err_code); - - ble_stack_init(); - gap_params_init(); - gatt_init(); - services_init(); - advertising_init(); - conn_params_init(); - - return RT_TRUE; -} - -/**@brief Application main function. - */ -static void _stack_thread(void *parameter) -{ - rt_tick_t next_timeout = (rt_tick_t)RT_WAITING_FOREVER; - - FAST_ADV(); - // Enter main loop. - for (;;) - { - rt_uint32_t event = 0; - rt_tick_t dispatch_timeout = RT_WAITING_NO; - - rt_event_recv(stack_event, STACK_EV_DISCON | STACK_EV_DISPATCH | STACK_EV_KEY, - RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, next_timeout, &event); - - if (evt_dispatch_worker() != RT_EOK) - { - dispatch_timeout = (rt_tick_t)RT_WAITING_FOREVER; - } - - if (event & STACK_EV_DISCON) - { - if (BLE_CONN_HANDLE_INVALID != m_conn_handle) - { - sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); - } - } - - if (event & STACK_EV_KEY) - { - if (stack_state != STACK_STATE_CON && stack_state != STACK_STATE_ADV) - { - FAST_ADV(); - } - } - - next_timeout = (rt_tick_t)RT_WAITING_FOREVER; - - if (dispatch_timeout < next_timeout) - { - next_timeout = dispatch_timeout; - } - } -} - -static void _softdevice_thread(void* parameter) -{ - for (;;) - { - rt_sem_take(sd_evt_sem, RT_WAITING_FOREVER); - intern_softdevice_events_execute(); - } -} - -rt_err_t ble_init(void) -{ - rt_thread_t thread; - - _stack_init(); - - thread = rt_thread_create("sdth", _softdevice_thread, RT_NULL, 512, 0, 10); - - if (thread != RT_NULL) - { - rt_thread_startup(thread); - } - else - { - return RT_ERROR; - } - - thread = rt_thread_create("bleth", _stack_thread, RT_NULL, 2048, 1, 10); - - if (thread != RT_NULL) - { - return rt_thread_startup(thread); - } - - return RT_ERROR; -} diff --git a/bsp/nrf5x/nrf52832/applications/sdk_config.h b/bsp/nrf5x/nrf52832/applications/sdk_config.h deleted file mode 100644 index 72abeeed7ca34d014b2a3e936460e9d6b65ae079..0000000000000000000000000000000000000000 --- a/bsp/nrf5x/nrf52832/applications/sdk_config.h +++ /dev/null @@ -1,3991 +0,0 @@ - - -#ifndef SDK_CONFIG_H -#define SDK_CONFIG_H -// <<< Use Configuration Wizard in Context Menu >>>\n -#ifdef USE_APP_CONFIG -#include "app_config.h" -#endif -// nRF_BLE - -//========================================================== -// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module - - -#ifndef BLE_ADVERTISING_ENABLED -#define BLE_ADVERTISING_ENABLED 1 -#endif - -// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands - - -#ifndef BLE_DTM_ENABLED -#define BLE_DTM_ENABLED 0 -#endif - -// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library - - -#ifndef BLE_RACP_ENABLED -#define BLE_RACP_ENABLED 0 -#endif - -// NRF_BLE_GATT_ENABLED - nrf_ble_gatt - GATT module -//========================================================== -#ifndef NRF_BLE_GATT_ENABLED -#define NRF_BLE_GATT_ENABLED 1 -#endif -#if NRF_BLE_GATT_ENABLED -// NRF_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size that is passed to the @ref sd_ble_enable function. -#ifndef NRF_BLE_GATT_MAX_MTU_SIZE -#define NRF_BLE_GATT_MAX_MTU_SIZE 158 -#endif - -#endif //NRF_BLE_GATT_ENABLED -// - -// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) - - -#ifndef NRF_BLE_QWR_ENABLED -#define NRF_BLE_QWR_ENABLED 0 -#endif - -// PEER_MANAGER_ENABLED - peer_manager - Peer Manager - - -#ifndef PEER_MANAGER_ENABLED -#define PEER_MANAGER_ENABLED 0 -#endif - -// -//========================================================== - -// nRF_BLE_Services - -//========================================================== -// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client - - -#ifndef BLE_ANCS_C_ENABLED -#define BLE_ANCS_C_ENABLED 0 -#endif - -// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client - - -#ifndef BLE_ANS_C_ENABLED -#define BLE_ANS_C_ENABLED 0 -#endif - -// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client - - -#ifndef BLE_BAS_C_ENABLED -#define BLE_BAS_C_ENABLED 0 -#endif - -// BLE_BAS_ENABLED - ble_bas - Battery Service - - -#ifndef BLE_BAS_ENABLED -#define BLE_BAS_ENABLED 0 -#endif - -// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service - - -#ifndef BLE_CSCS_ENABLED -#define BLE_CSCS_ENABLED 0 -#endif - -// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client - - -#ifndef BLE_CTS_C_ENABLED -#define BLE_CTS_C_ENABLED 0 -#endif - -// BLE_DIS_ENABLED - ble_dis - Device Information Service - - -#ifndef BLE_DIS_ENABLED -#define BLE_DIS_ENABLED 0 -#endif - -// BLE_GLS_ENABLED - ble_gls - Glucose Service - - -#ifndef BLE_GLS_ENABLED -#define BLE_GLS_ENABLED 0 -#endif - -// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service - - -#ifndef BLE_HIDS_ENABLED -#define BLE_HIDS_ENABLED 0 -#endif - -// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client -//========================================================== -#ifndef BLE_HRS_C_ENABLED -#define BLE_HRS_C_ENABLED 0 -#endif -#if BLE_HRS_C_ENABLED -// BLE_HRS_C_RR_INTERVALS_MAX_CNT - Maximum number of RR_INTERVALS per notification to be decoded -#ifndef BLE_HRS_C_RR_INTERVALS_MAX_CNT -#define BLE_HRS_C_RR_INTERVALS_MAX_CNT 30 -#endif - -#endif //BLE_HRS_C_ENABLED -// - -// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service - - -#ifndef BLE_HRS_ENABLED -#define BLE_HRS_ENABLED 0 -#endif - -// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service - - -#ifndef BLE_HTS_ENABLED -#define BLE_HTS_ENABLED 0 -#endif - -// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client - - -#ifndef BLE_IAS_C_ENABLED -#define BLE_IAS_C_ENABLED 0 -#endif - -// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service - - -#ifndef BLE_IAS_ENABLED -#define BLE_IAS_ENABLED 0 -#endif - -// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client - - -#ifndef BLE_LBS_C_ENABLED -#define BLE_LBS_C_ENABLED 0 -#endif - -// BLE_LBS_ENABLED - ble_lbs - LED Button Service - - -#ifndef BLE_LBS_ENABLED -#define BLE_LBS_ENABLED 0 -#endif - -// BLE_LLS_ENABLED - ble_lls - Link Loss Service - - -#ifndef BLE_LLS_ENABLED -#define BLE_LLS_ENABLED 0 -#endif - -// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service - - -#ifndef BLE_NUS_C_ENABLED -#define BLE_NUS_C_ENABLED 0 -#endif - -// BLE_NUS_ENABLED - ble_nus - Nordic UART Service - - -#ifndef BLE_NUS_ENABLED -#define BLE_NUS_ENABLED 1 -#endif - -// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client - - -#ifndef BLE_RSCS_C_ENABLED -#define BLE_RSCS_C_ENABLED 0 -#endif - -// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service - - -#ifndef BLE_RSCS_ENABLED -#define BLE_RSCS_ENABLED 0 -#endif - -// BLE_TPS_ENABLED - ble_tps - TX Power Service - - -#ifndef BLE_TPS_ENABLED -#define BLE_TPS_ENABLED 0 -#endif - -// -//========================================================== - -// nRF_Drivers - -//========================================================== -// APP_USBD_ENABLED - app_usbd - USB Device library -//========================================================== -#ifndef APP_USBD_ENABLED -#define APP_USBD_ENABLED 0 -#endif -#if APP_USBD_ENABLED -// APP_USBD_VID - Vendor ID <0x0000-0xFFFF> - - -// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ - -#ifndef APP_USBD_VID -#define APP_USBD_VID 0 -#endif - -// APP_USBD_PID - Product ID <0x0000-0xFFFF> - - -// Selected Product ID - -#ifndef APP_USBD_PID -#define APP_USBD_PID 0 -#endif - -// APP_USBD_DEVICE_VER_MAJOR - Device version, major part <0-99> - - -// Device version, will be converted automatically to BCD notation. Use just decimal values. - -#ifndef APP_USBD_DEVICE_VER_MAJOR -#define APP_USBD_DEVICE_VER_MAJOR 1 -#endif - -// APP_USBD_DEVICE_VER_MINOR - Device version, minor part <0-99> - - -// Device version, will be converted automatically to BCD notation. Use just decimal values. - -#ifndef APP_USBD_DEVICE_VER_MINOR -#define APP_USBD_DEVICE_VER_MINOR 0 -#endif - -#endif //APP_USBD_ENABLED -// - -// CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver -//========================================================== -#ifndef CLOCK_ENABLED -#define CLOCK_ENABLED 1 -#endif -#if CLOCK_ENABLED -// CLOCK_CONFIG_XTAL_FREQ - HF XTAL Frequency - -// <0=> Default (64 MHz) - -#ifndef CLOCK_CONFIG_XTAL_FREQ -#define CLOCK_CONFIG_XTAL_FREQ 0 -#endif - -// CLOCK_CONFIG_LF_SRC - LF Clock Source - -// <0=> RC -// <1=> XTAL -// <2=> Synth - -#ifndef CLOCK_CONFIG_LF_SRC -#define CLOCK_CONFIG_LF_SRC 1 -#endif - -// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef CLOCK_CONFIG_IRQ_PRIORITY -#define CLOCK_CONFIG_IRQ_PRIORITY 7 -#endif - -// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef CLOCK_CONFIG_LOG_ENABLED -#define CLOCK_CONFIG_LOG_ENABLED 0 -#endif -#if CLOCK_CONFIG_LOG_ENABLED -// CLOCK_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef CLOCK_CONFIG_LOG_LEVEL -#define CLOCK_CONFIG_LOG_LEVEL 3 -#endif - -// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef CLOCK_CONFIG_INFO_COLOR -#define CLOCK_CONFIG_INFO_COLOR 0 -#endif - -// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef CLOCK_CONFIG_DEBUG_COLOR -#define CLOCK_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //CLOCK_CONFIG_LOG_ENABLED -// - -#endif //CLOCK_ENABLED -// - -// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver -//========================================================== -#ifndef COMP_ENABLED -#define COMP_ENABLED 0 -#endif -#if COMP_ENABLED -// COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef - -#ifndef COMP_CONFIG_REF -#define COMP_CONFIG_REF 1 -#endif - -// COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential - -#ifndef COMP_CONFIG_MAIN_MODE -#define COMP_CONFIG_MAIN_MODE 0 -#endif - -// COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed - -#ifndef COMP_CONFIG_SPEED_MODE -#define COMP_CONFIG_SPEED_MODE 2 -#endif - -// COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV - -#ifndef COMP_CONFIG_HYST -#define COMP_CONFIG_HYST 0 -#endif - -// COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA - -#ifndef COMP_CONFIG_ISOURCE -#define COMP_CONFIG_ISOURCE 0 -#endif - -// COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef COMP_CONFIG_INPUT -#define COMP_CONFIG_INPUT 0 -#endif - -// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef COMP_CONFIG_IRQ_PRIORITY -#define COMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef COMP_CONFIG_LOG_ENABLED -#define COMP_CONFIG_LOG_ENABLED 0 -#endif -#if COMP_CONFIG_LOG_ENABLED -// COMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef COMP_CONFIG_LOG_LEVEL -#define COMP_CONFIG_LOG_LEVEL 3 -#endif - -// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef COMP_CONFIG_INFO_COLOR -#define COMP_CONFIG_INFO_COLOR 0 -#endif - -// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef COMP_CONFIG_DEBUG_COLOR -#define COMP_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //COMP_CONFIG_LOG_ENABLED -// - -#endif //COMP_ENABLED -// - -// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver -//========================================================== -#ifndef EGU_ENABLED -#define EGU_ENABLED 0 -#endif -#if EGU_ENABLED -// SWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SWI_CONFIG_LOG_ENABLED -#define SWI_CONFIG_LOG_ENABLED 0 -#endif -#if SWI_CONFIG_LOG_ENABLED -// SWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SWI_CONFIG_LOG_LEVEL -#define SWI_CONFIG_LOG_LEVEL 3 -#endif - -// SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SWI_CONFIG_INFO_COLOR -#define SWI_CONFIG_INFO_COLOR 0 -#endif - -// SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SWI_CONFIG_DEBUG_COLOR -#define SWI_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //SWI_CONFIG_LOG_ENABLED -// - -#endif //EGU_ENABLED -// - -// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver -//========================================================== -#ifndef GPIOTE_ENABLED -#define GPIOTE_ENABLED 1 -#endif -#if GPIOTE_ENABLED -// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins -#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 -#endif - -// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef GPIOTE_CONFIG_IRQ_PRIORITY -#define GPIOTE_CONFIG_IRQ_PRIORITY 7 -#endif - -// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef GPIOTE_CONFIG_LOG_ENABLED -#define GPIOTE_CONFIG_LOG_ENABLED 0 -#endif -#if GPIOTE_CONFIG_LOG_ENABLED -// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef GPIOTE_CONFIG_LOG_LEVEL -#define GPIOTE_CONFIG_LOG_LEVEL 3 -#endif - -// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef GPIOTE_CONFIG_INFO_COLOR -#define GPIOTE_CONFIG_INFO_COLOR 0 -#endif - -// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef GPIOTE_CONFIG_DEBUG_COLOR -#define GPIOTE_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //GPIOTE_CONFIG_LOG_ENABLED -// - -#endif //GPIOTE_ENABLED -// - -// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver -//========================================================== -#ifndef I2S_ENABLED -#define I2S_ENABLED 0 -#endif -#if I2S_ENABLED -// I2S_CONFIG_SCK_PIN - SCK pin <0-31> - - -#ifndef I2S_CONFIG_SCK_PIN -#define I2S_CONFIG_SCK_PIN 31 -#endif - -// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> - - -#ifndef I2S_CONFIG_LRCK_PIN -#define I2S_CONFIG_LRCK_PIN 30 -#endif - -// I2S_CONFIG_MCK_PIN - MCK pin -#ifndef I2S_CONFIG_MCK_PIN -#define I2S_CONFIG_MCK_PIN 255 -#endif - -// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> - - -#ifndef I2S_CONFIG_SDOUT_PIN -#define I2S_CONFIG_SDOUT_PIN 29 -#endif - -// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> - - -#ifndef I2S_CONFIG_SDIN_PIN -#define I2S_CONFIG_SDIN_PIN 28 -#endif - -// I2S_CONFIG_MASTER - Mode - -// <0=> Master -// <1=> Slave - -#ifndef I2S_CONFIG_MASTER -#define I2S_CONFIG_MASTER 0 -#endif - -// I2S_CONFIG_FORMAT - Format - -// <0=> I2S -// <1=> Aligned - -#ifndef I2S_CONFIG_FORMAT -#define I2S_CONFIG_FORMAT 0 -#endif - -// I2S_CONFIG_ALIGN - Alignment - -// <0=> Left -// <1=> Right - -#ifndef I2S_CONFIG_ALIGN -#define I2S_CONFIG_ALIGN 0 -#endif - -// I2S_CONFIG_SWIDTH - Sample width (bits) - -// <0=> 8 -// <1=> 16 -// <2=> 24 - -#ifndef I2S_CONFIG_SWIDTH -#define I2S_CONFIG_SWIDTH 1 -#endif - -// I2S_CONFIG_CHANNELS - Channels - -// <0=> Stereo -// <1=> Left -// <2=> Right - -#ifndef I2S_CONFIG_CHANNELS -#define I2S_CONFIG_CHANNELS 1 -#endif - -// I2S_CONFIG_MCK_SETUP - MCK behavior - -// <0=> Disabled -// <2147483648=> 32MHz/2 -// <1342177280=> 32MHz/3 -// <1073741824=> 32MHz/4 -// <805306368=> 32MHz/5 -// <671088640=> 32MHz/6 -// <536870912=> 32MHz/8 -// <402653184=> 32MHz/10 -// <369098752=> 32MHz/11 -// <285212672=> 32MHz/15 -// <268435456=> 32MHz/16 -// <201326592=> 32MHz/21 -// <184549376=> 32MHz/23 -// <142606336=> 32MHz/30 -// <138412032=> 32MHz/31 -// <134217728=> 32MHz/32 -// <100663296=> 32MHz/42 -// <68157440=> 32MHz/63 -// <34340864=> 32MHz/125 - -#ifndef I2S_CONFIG_MCK_SETUP -#define I2S_CONFIG_MCK_SETUP 536870912 -#endif - -// I2S_CONFIG_RATIO - MCK/LRCK ratio - -// <0=> 32x -// <1=> 48x -// <2=> 64x -// <3=> 96x -// <4=> 128x -// <5=> 192x -// <6=> 256x -// <7=> 384x -// <8=> 512x - -#ifndef I2S_CONFIG_RATIO -#define I2S_CONFIG_RATIO 2000 -#endif - -// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef I2S_CONFIG_IRQ_PRIORITY -#define I2S_CONFIG_IRQ_PRIORITY 7 -#endif - -// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef I2S_CONFIG_LOG_ENABLED -#define I2S_CONFIG_LOG_ENABLED 0 -#endif -#if I2S_CONFIG_LOG_ENABLED -// I2S_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef I2S_CONFIG_LOG_LEVEL -#define I2S_CONFIG_LOG_LEVEL 3 -#endif - -// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef I2S_CONFIG_INFO_COLOR -#define I2S_CONFIG_INFO_COLOR 0 -#endif - -// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef I2S_CONFIG_DEBUG_COLOR -#define I2S_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //I2S_CONFIG_LOG_ENABLED -// - -#endif //I2S_ENABLED -// - -// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver -//========================================================== -#ifndef LPCOMP_ENABLED -#define LPCOMP_ENABLED 0 -#endif -#if LPCOMP_ENABLED -// LPCOMP_CONFIG_REFERENCE - Reference voltage - -// <0=> Supply 1/8 -// <1=> Supply 2/8 -// <2=> Supply 3/8 -// <3=> Supply 4/8 -// <4=> Supply 5/8 -// <5=> Supply 6/8 -// <6=> Supply 7/8 -// <8=> Supply 1/16 (nRF52) -// <9=> Supply 3/16 (nRF52) -// <10=> Supply 5/16 (nRF52) -// <11=> Supply 7/16 (nRF52) -// <12=> Supply 9/16 (nRF52) -// <13=> Supply 11/16 (nRF52) -// <14=> Supply 13/16 (nRF52) -// <15=> Supply 15/16 (nRF52) -// <7=> External Ref 0 -// <65543=> External Ref 1 - -#ifndef LPCOMP_CONFIG_REFERENCE -#define LPCOMP_CONFIG_REFERENCE 3 -#endif - -// LPCOMP_CONFIG_DETECTION - Detection - -// <0=> Crossing -// <1=> Up -// <2=> Down - -#ifndef LPCOMP_CONFIG_DETECTION -#define LPCOMP_CONFIG_DETECTION 2 -#endif - -// LPCOMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef LPCOMP_CONFIG_INPUT -#define LPCOMP_CONFIG_INPUT 0 -#endif - -// LPCOMP_CONFIG_HYST - Hysteresis - - -#ifndef LPCOMP_CONFIG_HYST -#define LPCOMP_CONFIG_HYST 0 -#endif - -// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef LPCOMP_CONFIG_IRQ_PRIORITY -#define LPCOMP_CONFIG_IRQ_PRIORITY 7 -#endif - -// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef LPCOMP_CONFIG_LOG_ENABLED -#define LPCOMP_CONFIG_LOG_ENABLED 0 -#endif -#if LPCOMP_CONFIG_LOG_ENABLED -// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef LPCOMP_CONFIG_LOG_LEVEL -#define LPCOMP_CONFIG_LOG_LEVEL 3 -#endif - -// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef LPCOMP_CONFIG_INFO_COLOR -#define LPCOMP_CONFIG_INFO_COLOR 0 -#endif - -// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef LPCOMP_CONFIG_DEBUG_COLOR -#define LPCOMP_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //LPCOMP_CONFIG_LOG_ENABLED -// - -#endif //LPCOMP_ENABLED -// - -// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver -//========================================================== -#ifndef PDM_ENABLED -#define PDM_ENABLED 0 -#endif -#if PDM_ENABLED -// PDM_CONFIG_MODE - Mode - -// <0=> Stereo -// <1=> Mono - -#ifndef PDM_CONFIG_MODE -#define PDM_CONFIG_MODE 1 -#endif - -// PDM_CONFIG_EDGE - Edge - -// <0=> Left falling -// <1=> Left rising - -#ifndef PDM_CONFIG_EDGE -#define PDM_CONFIG_EDGE 0 -#endif - -// PDM_CONFIG_CLOCK_FREQ - Clock frequency - -// <134217728=> 1000k -// <138412032=> 1032k (default) -// <142606336=> 1067k - -#ifndef PDM_CONFIG_CLOCK_FREQ -#define PDM_CONFIG_CLOCK_FREQ 138412032 -#endif - -// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef PDM_CONFIG_IRQ_PRIORITY -#define PDM_CONFIG_IRQ_PRIORITY 7 -#endif - -// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef PDM_CONFIG_LOG_ENABLED -#define PDM_CONFIG_LOG_ENABLED 0 -#endif -#if PDM_CONFIG_LOG_ENABLED -// PDM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef PDM_CONFIG_LOG_LEVEL -#define PDM_CONFIG_LOG_LEVEL 3 -#endif - -// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PDM_CONFIG_INFO_COLOR -#define PDM_CONFIG_INFO_COLOR 0 -#endif - -// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PDM_CONFIG_DEBUG_COLOR -#define PDM_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //PDM_CONFIG_LOG_ENABLED -// - -#endif //PDM_ENABLED -// - -// PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module -//========================================================== -#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 -#endif -#if PERIPHERAL_RESOURCE_SHARING_ENABLED -// COMMON_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef COMMON_CONFIG_LOG_ENABLED -#define COMMON_CONFIG_LOG_ENABLED 0 -#endif -#if COMMON_CONFIG_LOG_ENABLED -// COMMON_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef COMMON_CONFIG_LOG_LEVEL -#define COMMON_CONFIG_LOG_LEVEL 3 -#endif - -// COMMON_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef COMMON_CONFIG_INFO_COLOR -#define COMMON_CONFIG_INFO_COLOR 0 -#endif - -// COMMON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef COMMON_CONFIG_DEBUG_COLOR -#define COMMON_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //COMMON_CONFIG_LOG_ENABLED -// - -#endif //PERIPHERAL_RESOURCE_SHARING_ENABLED -// - -// POWER_ENABLED - nrf_drv_power - POWER peripheral driver -//========================================================== -#ifndef POWER_ENABLED -#define POWER_ENABLED 0 -#endif -#if POWER_ENABLED -// POWER_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef POWER_CONFIG_IRQ_PRIORITY -#define POWER_CONFIG_IRQ_PRIORITY 7 -#endif - -// POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef POWER_CONFIG_DEFAULT_DCDCEN -#define POWER_CONFIG_DEFAULT_DCDCEN 0 -#endif - -// POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef POWER_CONFIG_DEFAULT_DCDCENHV -#define POWER_CONFIG_DEFAULT_DCDCENHV 0 -#endif - -#endif //POWER_ENABLED -// - -// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver -//========================================================== -#ifndef PPI_ENABLED -#define PPI_ENABLED 0 -#endif -#if PPI_ENABLED -// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef PPI_CONFIG_LOG_ENABLED -#define PPI_CONFIG_LOG_ENABLED 0 -#endif -#if PPI_CONFIG_LOG_ENABLED -// PPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef PPI_CONFIG_LOG_LEVEL -#define PPI_CONFIG_LOG_LEVEL 3 -#endif - -// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PPI_CONFIG_INFO_COLOR -#define PPI_CONFIG_INFO_COLOR 0 -#endif - -// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PPI_CONFIG_DEBUG_COLOR -#define PPI_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //PPI_CONFIG_LOG_ENABLED -// - -#endif //PPI_ENABLED -// - -// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver -//========================================================== -#ifndef PWM_ENABLED -#define PWM_ENABLED 1 -#endif -#if PWM_ENABLED -// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN -#define PWM_DEFAULT_CONFIG_OUT0_PIN 2 -#endif - -// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN -#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN -#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> - - -#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN -#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 -#endif - -// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 MHz - -#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK -#define PWM_DEFAULT_CONFIG_BASE_CLOCK 7 -#endif - -// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode - -// <0=> Up -// <1=> Up and Down - -#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE -#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value -#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE -#define PWM_DEFAULT_CONFIG_TOP_VALUE 46 -#endif - -// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode - -// <0=> Common -// <1=> Grouped -// <2=> Individual -// <3=> Waveform - -#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE -#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode - -// <0=> Auto -// <1=> Triggered - -#ifndef PWM_DEFAULT_CONFIG_STEP_MODE -#define PWM_DEFAULT_CONFIG_STEP_MODE 0 -#endif - -// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY -#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// PWM0_ENABLED - Enable PWM0 instance - - -#ifndef PWM0_ENABLED -#define PWM0_ENABLED 1 -#endif - -// PWM1_ENABLED - Enable PWM1 instance - - -#ifndef PWM1_ENABLED -#define PWM1_ENABLED 0 -#endif - -// PWM2_ENABLED - Enable PWM2 instance - - -#ifndef PWM2_ENABLED -#define PWM2_ENABLED 0 -#endif - -// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef PWM_CONFIG_LOG_ENABLED -#define PWM_CONFIG_LOG_ENABLED 0 -#endif -#if PWM_CONFIG_LOG_ENABLED -// PWM_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef PWM_CONFIG_LOG_LEVEL -#define PWM_CONFIG_LOG_LEVEL 3 -#endif - -// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PWM_CONFIG_INFO_COLOR -#define PWM_CONFIG_INFO_COLOR 0 -#endif - -// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef PWM_CONFIG_DEBUG_COLOR -#define PWM_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //PWM_CONFIG_LOG_ENABLED -// - -// PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for PWM. - -// The workaround uses interrupts to wake up the CPU and ensure -// it is active when PWM is about to start a DMA transfer. For -// initial transfer, done when a playback is started via PPI, -// a specific EGU instance is used to generate the interrupt. -// During the playback, the PWM interrupt triggered on SEQEND -// event of a preceding sequence is used to protect the transfer -// done for the next sequence to be played. -//========================================================== -#ifndef PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 -#endif -#if PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -// PWM_NRF52_ANOMALY_109_EGU_INSTANCE - EGU instance used by the nRF52 Anomaly 109 workaround for PWM. - -// <0=> EGU0 -// <1=> EGU1 -// <2=> EGU2 -// <3=> EGU3 -// <4=> EGU4 -// <5=> EGU5 - -#ifndef PWM_NRF52_ANOMALY_109_EGU_INSTANCE -#define PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5 -#endif - -#endif //PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -// - -#endif //PWM_ENABLED -// - -// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver -//========================================================== -#ifndef QDEC_ENABLED -#define QDEC_ENABLED 0 -#endif -#if QDEC_ENABLED -// QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples - -#ifndef QDEC_CONFIG_REPORTPER -#define QDEC_CONFIG_REPORTPER 0 -#endif - -// QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us - -#ifndef QDEC_CONFIG_SAMPLEPER -#define QDEC_CONFIG_SAMPLEPER 7 -#endif - -// QDEC_CONFIG_PIO_A - A pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_A -#define QDEC_CONFIG_PIO_A 31 -#endif - -// QDEC_CONFIG_PIO_B - B pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_B -#define QDEC_CONFIG_PIO_B 31 -#endif - -// QDEC_CONFIG_PIO_LED - LED pin <0-31> - - -#ifndef QDEC_CONFIG_PIO_LED -#define QDEC_CONFIG_PIO_LED 31 -#endif - -// QDEC_CONFIG_LEDPRE - LED pre -#ifndef QDEC_CONFIG_LEDPRE -#define QDEC_CONFIG_LEDPRE 511 -#endif - -// QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high - -#ifndef QDEC_CONFIG_LEDPOL -#define QDEC_CONFIG_LEDPOL 1 -#endif - -// QDEC_CONFIG_DBFEN - Debouncing enable - - -#ifndef QDEC_CONFIG_DBFEN -#define QDEC_CONFIG_DBFEN 0 -#endif - -// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - - -#ifndef QDEC_CONFIG_SAMPLE_INTEN -#define QDEC_CONFIG_SAMPLE_INTEN 0 -#endif - -// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef QDEC_CONFIG_IRQ_PRIORITY -#define QDEC_CONFIG_IRQ_PRIORITY 7 -#endif - -// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef QDEC_CONFIG_LOG_ENABLED -#define QDEC_CONFIG_LOG_ENABLED 0 -#endif -#if QDEC_CONFIG_LOG_ENABLED -// QDEC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef QDEC_CONFIG_LOG_LEVEL -#define QDEC_CONFIG_LOG_LEVEL 3 -#endif - -// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef QDEC_CONFIG_INFO_COLOR -#define QDEC_CONFIG_INFO_COLOR 0 -#endif - -// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef QDEC_CONFIG_DEBUG_COLOR -#define QDEC_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //QDEC_CONFIG_LOG_ENABLED -// - -#endif //QDEC_ENABLED -// - -// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver -//========================================================== -#ifndef RNG_ENABLED -#define RNG_ENABLED 0 -#endif -#if RNG_ENABLED -// RNG_CONFIG_ERROR_CORRECTION - Error correction - - -#ifndef RNG_CONFIG_ERROR_CORRECTION -#define RNG_CONFIG_ERROR_CORRECTION 0 -#endif - -// RNG_CONFIG_POOL_SIZE - Pool size -#ifndef RNG_CONFIG_POOL_SIZE -#define RNG_CONFIG_POOL_SIZE 32 -#endif - -// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef RNG_CONFIG_IRQ_PRIORITY -#define RNG_CONFIG_IRQ_PRIORITY 7 -#endif - -// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef RNG_CONFIG_LOG_ENABLED -#define RNG_CONFIG_LOG_ENABLED 0 -#endif -#if RNG_CONFIG_LOG_ENABLED -// RNG_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef RNG_CONFIG_LOG_LEVEL -#define RNG_CONFIG_LOG_LEVEL 3 -#endif - -// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RNG_CONFIG_INFO_COLOR -#define RNG_CONFIG_INFO_COLOR 0 -#endif - -// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RNG_CONFIG_DEBUG_COLOR -#define RNG_CONFIG_DEBUG_COLOR 0 -#endif - -// RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - Enables logging of random numbers. - - -#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED -#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 -#endif - -#endif //RNG_CONFIG_LOG_ENABLED -// - -#endif //RNG_ENABLED -// - -// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver -//========================================================== -#ifndef RTC_ENABLED -#define RTC_ENABLED 0 -#endif -#if RTC_ENABLED -// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> - - -#ifndef RTC_DEFAULT_CONFIG_FREQUENCY -#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 -#endif - -// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - - -#ifndef RTC_DEFAULT_CONFIG_RELIABLE -#define RTC_DEFAULT_CONFIG_RELIABLE 0 -#endif - -// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY -#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// RTC0_ENABLED - Enable RTC0 instance - - -#ifndef RTC0_ENABLED -#define RTC0_ENABLED 0 -#endif - -// RTC1_ENABLED - Enable RTC1 instance - - -#ifndef RTC1_ENABLED -#define RTC1_ENABLED 0 -#endif - -// RTC2_ENABLED - Enable RTC2 instance - - -#ifndef RTC2_ENABLED -#define RTC2_ENABLED 0 -#endif - -// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt -#ifndef NRF_MAXIMUM_LATENCY_US -#define NRF_MAXIMUM_LATENCY_US 2000 -#endif - -// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef RTC_CONFIG_LOG_ENABLED -#define RTC_CONFIG_LOG_ENABLED 0 -#endif -#if RTC_CONFIG_LOG_ENABLED -// RTC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef RTC_CONFIG_LOG_LEVEL -#define RTC_CONFIG_LOG_LEVEL 3 -#endif - -// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RTC_CONFIG_INFO_COLOR -#define RTC_CONFIG_INFO_COLOR 0 -#endif - -// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef RTC_CONFIG_DEBUG_COLOR -#define RTC_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //RTC_CONFIG_LOG_ENABLED -// - -#endif //RTC_ENABLED -// - -// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver -//========================================================== -#ifndef SAADC_ENABLED -#define SAADC_ENABLED 1 -#endif -#if SAADC_ENABLED -// SAADC_CONFIG_RESOLUTION - Resolution - -// <0=> 8 bit -// <1=> 10 bit -// <2=> 12 bit -// <3=> 14 bit - -#ifndef SAADC_CONFIG_RESOLUTION -#define SAADC_CONFIG_RESOLUTION 2 -#endif - -// SAADC_CONFIG_OVERSAMPLE - Sample period - -// <0=> Disabled -// <1=> 2x -// <2=> 4x -// <3=> 8x -// <4=> 16x -// <5=> 32x -// <6=> 64x -// <7=> 128x -// <8=> 256x - -#ifndef SAADC_CONFIG_OVERSAMPLE -#define SAADC_CONFIG_OVERSAMPLE 0 -#endif - -// SAADC_CONFIG_LP_MODE - Enabling low power mode - - -#ifndef SAADC_CONFIG_LP_MODE -#define SAADC_CONFIG_LP_MODE 0 -#endif - -// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SAADC_CONFIG_IRQ_PRIORITY -#define SAADC_CONFIG_IRQ_PRIORITY 7 -#endif - -// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SAADC_CONFIG_LOG_ENABLED -#define SAADC_CONFIG_LOG_ENABLED 0 -#endif -#if SAADC_CONFIG_LOG_ENABLED -// SAADC_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SAADC_CONFIG_LOG_LEVEL -#define SAADC_CONFIG_LOG_LEVEL 3 -#endif - -// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SAADC_CONFIG_INFO_COLOR -#define SAADC_CONFIG_INFO_COLOR 0 -#endif - -// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SAADC_CONFIG_DEBUG_COLOR -#define SAADC_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //SAADC_CONFIG_LOG_ENABLED -// - -#endif //SAADC_ENABLED -// - -// SPIS_ENABLED - nrf_drv_spis - SPI Slave driver -//========================================================== -#ifndef SPIS_ENABLED -#define SPIS_ENABLED 0 -#endif -#if SPIS_ENABLED -// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// SPIS_DEFAULT_MODE - Mode - -// <0=> MODE_0 -// <1=> MODE_1 -// <2=> MODE_2 -// <3=> MODE_3 - -#ifndef SPIS_DEFAULT_MODE -#define SPIS_DEFAULT_MODE 0 -#endif - -// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order - -// <0=> MSB first -// <1=> LSB first - -#ifndef SPIS_DEFAULT_BIT_ORDER -#define SPIS_DEFAULT_BIT_ORDER 0 -#endif - -// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> - - -#ifndef SPIS_DEFAULT_DEF -#define SPIS_DEFAULT_DEF 255 -#endif - -// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> - - -#ifndef SPIS_DEFAULT_ORC -#define SPIS_DEFAULT_ORC 255 -#endif - -// SPIS0_ENABLED - Enable SPIS0 instance - - -#ifndef SPIS0_ENABLED -#define SPIS0_ENABLED 0 -#endif - -// SPIS1_ENABLED - Enable SPIS1 instance - - -#ifndef SPIS1_ENABLED -#define SPIS1_ENABLED 0 -#endif - -// SPIS2_ENABLED - Enable SPIS2 instance - - -#ifndef SPIS2_ENABLED -#define SPIS2_ENABLED 0 -#endif - -// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SPIS_CONFIG_LOG_ENABLED -#define SPIS_CONFIG_LOG_ENABLED 0 -#endif -#if SPIS_CONFIG_LOG_ENABLED -// SPIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SPIS_CONFIG_LOG_LEVEL -#define SPIS_CONFIG_LOG_LEVEL 3 -#endif - -// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPIS_CONFIG_INFO_COLOR -#define SPIS_CONFIG_INFO_COLOR 0 -#endif - -// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPIS_CONFIG_DEBUG_COLOR -#define SPIS_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //SPIS_CONFIG_LOG_ENABLED -// - -// SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for SPIS. - - -// The workaround uses a GPIOTE channel to generate interrupts -// on falling edges detected on the CSN line. This will make -// the CPU active for the moment when SPIS starts DMA transfers, -// and this way the transfers will be protected. -// This workaround uses GPIOTE driver, so this driver must be -// enabled as well. - -#ifndef SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 -#endif - -#endif //SPIS_ENABLED -// - -// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver -//========================================================== -#ifndef SPI_ENABLED -#define SPI_ENABLED 0 -#endif -#if SPI_ENABLED -// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY -#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// SPI0_ENABLED - Enable SPI0 instance -//========================================================== -#ifndef SPI0_ENABLED -#define SPI0_ENABLED 0 -#endif -#if SPI0_ENABLED -// SPI0_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI0_USE_EASY_DMA -#define SPI0_USE_EASY_DMA 1 -#endif - -// SPI0_DEFAULT_FREQUENCY - SPI frequency - -// <33554432=> 125 kHz -// <67108864=> 250 kHz -// <134217728=> 500 kHz -// <268435456=> 1 MHz -// <536870912=> 2 MHz -// <1073741824=> 4 MHz -// <2147483648=> 8 MHz - -#ifndef SPI0_DEFAULT_FREQUENCY -#define SPI0_DEFAULT_FREQUENCY 1073741824 -#endif - -#endif //SPI0_ENABLED -// - -// SPI1_ENABLED - Enable SPI1 instance -//========================================================== -#ifndef SPI1_ENABLED -#define SPI1_ENABLED 0 -#endif -#if SPI1_ENABLED -// SPI1_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI1_USE_EASY_DMA -#define SPI1_USE_EASY_DMA 1 -#endif - -// SPI1_DEFAULT_FREQUENCY - SPI frequency - -// <33554432=> 125 kHz -// <67108864=> 250 kHz -// <134217728=> 500 kHz -// <268435456=> 1 MHz -// <536870912=> 2 MHz -// <1073741824=> 4 MHz -// <2147483648=> 8 MHz - -#ifndef SPI1_DEFAULT_FREQUENCY -#define SPI1_DEFAULT_FREQUENCY 1073741824 -#endif - -#endif //SPI1_ENABLED -// - -// SPI2_ENABLED - Enable SPI2 instance -//========================================================== -#ifndef SPI2_ENABLED -#define SPI2_ENABLED 0 -#endif -#if SPI2_ENABLED -// SPI2_USE_EASY_DMA - Use EasyDMA - - -#ifndef SPI2_USE_EASY_DMA -#define SPI2_USE_EASY_DMA 1 -#endif - -// SPI2_DEFAULT_FREQUENCY - Use EasyDMA - - -#ifndef SPI2_DEFAULT_FREQUENCY -#define SPI2_DEFAULT_FREQUENCY 1 -#endif - -#endif //SPI2_ENABLED -// - -// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef SPI_CONFIG_LOG_ENABLED -#define SPI_CONFIG_LOG_ENABLED 0 -#endif -#if SPI_CONFIG_LOG_ENABLED -// SPI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef SPI_CONFIG_LOG_LEVEL -#define SPI_CONFIG_LOG_LEVEL 3 -#endif - -// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPI_CONFIG_INFO_COLOR -#define SPI_CONFIG_INFO_COLOR 0 -#endif - -// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef SPI_CONFIG_DEBUG_COLOR -#define SPI_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //SPI_CONFIG_LOG_ENABLED -// - -// SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 anomaly 109 workaround for SPIM. - - -// The workaround uses interrupts to wake up the CPU by catching -// a start event of zero-length transmission to start the clock. This -// ensures that the DMA transfer will be executed without issues and -// that the proper transfer will be started. See more in the Errata -// document or Anomaly 109 Addendum located at -// https://infocenter.nordicsemi.com/ - -#ifndef SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 -#endif - -#endif //SPI_ENABLED -// - -// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver -//========================================================== -#ifndef TIMER_ENABLED -#define TIMER_ENABLED 0 -#endif -#if TIMER_ENABLED -// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz - -#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY -#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 -#endif - -// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter - -#ifndef TIMER_DEFAULT_CONFIG_MODE -#define TIMER_DEFAULT_CONFIG_MODE 0 -#endif - -// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit - -#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 -#endif - -// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY -#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// TIMER0_ENABLED - Enable TIMER0 instance - - -#ifndef TIMER0_ENABLED -#define TIMER0_ENABLED 0 -#endif - -// TIMER1_ENABLED - Enable TIMER1 instance - - -#ifndef TIMER1_ENABLED -#define TIMER1_ENABLED 0 -#endif - -// TIMER2_ENABLED - Enable TIMER2 instance - - -#ifndef TIMER2_ENABLED -#define TIMER2_ENABLED 0 -#endif - -// TIMER3_ENABLED - Enable TIMER3 instance - - -#ifndef TIMER3_ENABLED -#define TIMER3_ENABLED 0 -#endif - -// TIMER4_ENABLED - Enable TIMER4 instance - - -#ifndef TIMER4_ENABLED -#define TIMER4_ENABLED 0 -#endif - -// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TIMER_CONFIG_LOG_ENABLED -#define TIMER_CONFIG_LOG_ENABLED 0 -#endif -#if TIMER_CONFIG_LOG_ENABLED -// TIMER_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TIMER_CONFIG_LOG_LEVEL -#define TIMER_CONFIG_LOG_LEVEL 3 -#endif - -// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TIMER_CONFIG_INFO_COLOR -#define TIMER_CONFIG_INFO_COLOR 0 -#endif - -// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TIMER_CONFIG_DEBUG_COLOR -#define TIMER_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //TIMER_CONFIG_LOG_ENABLED -// - -#endif //TIMER_ENABLED -// - -// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver -//========================================================== -#ifndef TWIS_ENABLED -#define TWIS_ENABLED 0 -#endif -#if TWIS_ENABLED -// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 -#ifndef TWIS_DEFAULT_CONFIG_ADDR0 -#define TWIS_DEFAULT_CONFIG_ADDR0 0 -#endif - -// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 -#ifndef TWIS_DEFAULT_CONFIG_ADDR1 -#define TWIS_DEFAULT_CONFIG_ADDR1 0 -#endif - -// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL -#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 -#endif - -// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL -#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 -#endif - -// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// TWIS0_ENABLED - Enable TWIS0 instance - - -#ifndef TWIS0_ENABLED -#define TWIS0_ENABLED 0 -#endif - -// TWIS1_ENABLED - Enable TWIS1 instance - - -#ifndef TWIS1_ENABLED -#define TWIS1_ENABLED 0 -#endif - -// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - - -// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. - -#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -#endif - -// TWIS_NO_SYNC_MODE - Remove support for synchronous mode - - -// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. - -#ifndef TWIS_NO_SYNC_MODE -#define TWIS_NO_SYNC_MODE 0 -#endif - -// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TWIS_CONFIG_LOG_ENABLED -#define TWIS_CONFIG_LOG_ENABLED 0 -#endif -#if TWIS_CONFIG_LOG_ENABLED -// TWIS_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TWIS_CONFIG_LOG_LEVEL -#define TWIS_CONFIG_LOG_LEVEL 3 -#endif - -// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWIS_CONFIG_INFO_COLOR -#define TWIS_CONFIG_INFO_COLOR 0 -#endif - -// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWIS_CONFIG_DEBUG_COLOR -#define TWIS_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //TWIS_CONFIG_LOG_ENABLED -// - -#endif //TWIS_ENABLED -// - -// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver -//========================================================== -#ifndef TWI_ENABLED -#define TWI_ENABLED 0 -#endif -#if TWI_ENABLED -// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef TWI_DEFAULT_CONFIG_FREQUENCY -#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init - - -#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT -#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 -#endif - -// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 -#endif - -// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY -#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// TWI0_ENABLED - Enable TWI0 instance -//========================================================== -#ifndef TWI0_ENABLED -#define TWI0_ENABLED 0 -#endif -#if TWI0_ENABLED -// TWI0_USE_EASY_DMA - Use EasyDMA (if present) - - -#ifndef TWI0_USE_EASY_DMA -#define TWI0_USE_EASY_DMA 0 -#endif - -#endif //TWI0_ENABLED -// - -// TWI1_ENABLED - Enable TWI1 instance -//========================================================== -#ifndef TWI1_ENABLED -#define TWI1_ENABLED 0 -#endif -#if TWI1_ENABLED -// TWI1_USE_EASY_DMA - Use EasyDMA (if present) - - -#ifndef TWI1_USE_EASY_DMA -#define TWI1_USE_EASY_DMA 0 -#endif - -#endif //TWI1_ENABLED -// - -// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef TWI_CONFIG_LOG_ENABLED -#define TWI_CONFIG_LOG_ENABLED 0 -#endif -#if TWI_CONFIG_LOG_ENABLED -// TWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef TWI_CONFIG_LOG_LEVEL -#define TWI_CONFIG_LOG_LEVEL 3 -#endif - -// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWI_CONFIG_INFO_COLOR -#define TWI_CONFIG_INFO_COLOR 0 -#endif - -// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef TWI_CONFIG_DEBUG_COLOR -#define TWI_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //TWI_CONFIG_LOG_ENABLED -// - -// TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 anomaly 109 workaround for TWIM. - - -// The workaround uses interrupts to wake up the CPU by catching -// the start event of zero-frequency transmission, clear the -// peripheral, set desired frequency, start the peripheral, and -// the proper transmission. See more in the Errata document or -// Anomaly 109 Addendum located at https://infocenter.nordicsemi.com/ - -#ifndef TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED -#define TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0 -#endif - -#endif //TWI_ENABLED -// - -// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver -//========================================================== -#ifndef UART_ENABLED -#define UART_ENABLED 1 -#endif -#if UART_ENABLED -// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef UART_DEFAULT_CONFIG_HWFC -#define UART_DEFAULT_CONFIG_HWFC 0 -#endif - -// UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef UART_DEFAULT_CONFIG_PARITY -#define UART_DEFAULT_CONFIG_PARITY 0 -#endif - -// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud - -#ifndef UART_DEFAULT_CONFIG_BAUDRATE -#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 -#endif - -// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY -#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 -#endif - -// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA - - -#ifndef UART_EASY_DMA_SUPPORT -#define UART_EASY_DMA_SUPPORT 0 -#endif - -// UART_LEGACY_SUPPORT - Driver supporting Legacy mode - - -#ifndef UART_LEGACY_SUPPORT -#define UART_LEGACY_SUPPORT 1 -#endif - -// UART0_ENABLED - Enable UART0 instance -//========================================================== -#ifndef UART0_ENABLED -#define UART0_ENABLED 1 -#endif -#if UART0_ENABLED -// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA - - -#ifndef UART0_CONFIG_USE_EASY_DMA -#define UART0_CONFIG_USE_EASY_DMA 0 -#endif - -#endif //UART0_ENABLED -// - -// UART_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef UART_CONFIG_LOG_ENABLED -#define UART_CONFIG_LOG_ENABLED 0 -#endif -#if UART_CONFIG_LOG_ENABLED -// UART_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef UART_CONFIG_LOG_LEVEL -#define UART_CONFIG_LOG_LEVEL 3 -#endif - -// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef UART_CONFIG_INFO_COLOR -#define UART_CONFIG_INFO_COLOR 0 -#endif - -// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef UART_CONFIG_DEBUG_COLOR -#define UART_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //UART_CONFIG_LOG_ENABLED -// - -#endif //UART_ENABLED -// - -// USBD_ENABLED - nrf_drv_usbd - USB driver -//========================================================== -#ifndef USBD_ENABLED -#define USBD_ENABLED 0 -#endif -#if USBD_ENABLED -// USBD_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef USBD_CONFIG_IRQ_PRIORITY -#define USBD_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRF_DRV_USBD_DMASCHEDULER_MODE - USBD SMA scheduler working scheme - -// <0=> Prioritized access -// <1=> Round Robin - -#ifndef NRF_DRV_USBD_DMASCHEDULER_MODE -#define NRF_DRV_USBD_DMASCHEDULER_MODE 0 -#endif - -// NRF_USBD_DRV_LOG_ENABLED - Enable logging - - -#ifndef NRF_USBD_DRV_LOG_ENABLED -#define NRF_USBD_DRV_LOG_ENABLED 0 -#endif - -#endif //USBD_ENABLED -// - -// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver -//========================================================== -#ifndef WDT_ENABLED -#define WDT_ENABLED 0 -#endif -#if WDT_ENABLED -// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT - -#ifndef WDT_CONFIG_BEHAVIOUR -#define WDT_CONFIG_BEHAVIOUR 1 -#endif - -// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> - - -#ifndef WDT_CONFIG_RELOAD_VALUE -#define WDT_CONFIG_RELOAD_VALUE 2000 -#endif - -// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef WDT_CONFIG_IRQ_PRIORITY -#define WDT_CONFIG_IRQ_PRIORITY 7 -#endif - -// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef WDT_CONFIG_LOG_ENABLED -#define WDT_CONFIG_LOG_ENABLED 0 -#endif -#if WDT_CONFIG_LOG_ENABLED -// WDT_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef WDT_CONFIG_LOG_LEVEL -#define WDT_CONFIG_LOG_LEVEL 3 -#endif - -// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef WDT_CONFIG_INFO_COLOR -#define WDT_CONFIG_INFO_COLOR 0 -#endif - -// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef WDT_CONFIG_DEBUG_COLOR -#define WDT_CONFIG_DEBUG_COLOR 0 -#endif - -#endif //WDT_CONFIG_LOG_ENABLED -// - -#endif //WDT_ENABLED -// - -// -//========================================================== - -// nRF_Libraries - -//========================================================== -// APP_FIFO_ENABLED - app_fifo - Software FIFO implementation - - -#ifndef APP_FIFO_ENABLED -#define APP_FIFO_ENABLED 1 -#endif - -// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher - - -#ifndef APP_GPIOTE_ENABLED -#define APP_GPIOTE_ENABLED 0 -#endif - -// APP_PWM_ENABLED - app_pwm - PWM functionality - - -#ifndef APP_PWM_ENABLED -#define APP_PWM_ENABLED 0 -#endif - -// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler -//========================================================== -#ifndef APP_SCHEDULER_ENABLED -#define APP_SCHEDULER_ENABLED 1 -#endif -#if APP_SCHEDULER_ENABLED -// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature - - -#ifndef APP_SCHEDULER_WITH_PAUSE -#define APP_SCHEDULER_WITH_PAUSE 0 -#endif - -// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling - - -#ifndef APP_SCHEDULER_WITH_PROFILER -#define APP_SCHEDULER_WITH_PROFILER 0 -#endif - -#endif //APP_SCHEDULER_ENABLED -// - -// APP_TIMER_ENABLED - app_timer - Application timer functionality -//========================================================== -#ifndef APP_TIMER_ENABLED -#define APP_TIMER_ENABLED 1 -#endif -#if APP_TIMER_ENABLED -// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. - -// <0=> 32768 Hz -// <1=> 16384 Hz -// <3=> 8192 Hz -// <7=> 4096 Hz -// <15=> 2048 Hz -// <31=> 1024 Hz - -#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY -#define APP_TIMER_CONFIG_RTC_FREQUENCY 0 -#endif - -// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority - - -// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice -// <0=> 0 (highest) -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY -#define APP_TIMER_CONFIG_IRQ_PRIORITY 7 -#endif - -// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. -// Size of the queue depends on how many timers are used -// in the system, how often timers are started and overall -// system latency. If queue size is too small app_timer calls -// will fail. - -#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE -#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 -#endif - -// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler - - -#ifndef APP_TIMER_CONFIG_USE_SCHEDULER -#define APP_TIMER_CONFIG_USE_SCHEDULER 0 -#endif - -// APP_TIMER_WITH_PROFILER - Enable app_timer profiling - - -#ifndef APP_TIMER_WITH_PROFILER -#define APP_TIMER_WITH_PROFILER 0 -#endif - -// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on - - -// If option is enabled RTC is kept running even if there is no active timers. -// This option can be used when app_timer is used for timestamping. - -#ifndef APP_TIMER_KEEPS_RTC_ACTIVE -#define APP_TIMER_KEEPS_RTC_ACTIVE 0 -#endif - -// APP_TIMER_CONFIG_SWI_NUMBER - Configure SWI instance used. - -// <0=> 0 -// <1=> 1 - -#ifndef APP_TIMER_CONFIG_SWI_NUMBER -#define APP_TIMER_CONFIG_SWI_NUMBER 0 -#endif - -#endif //APP_TIMER_ENABLED -// - -// APP_TWI_ENABLED - app_twi - TWI transaction manager - - -#ifndef APP_TWI_ENABLED -#define APP_TWI_ENABLED 0 -#endif - -// APP_UART_ENABLED - app_uart - UART driver -//========================================================== -#ifndef APP_UART_ENABLED -#define APP_UART_ENABLED 1 -#endif -#if APP_UART_ENABLED -// APP_UART_DRIVER_INSTANCE - UART instance used - -// <0=> 0 - -#ifndef APP_UART_DRIVER_INSTANCE -#define APP_UART_DRIVER_INSTANCE 0 -#endif - -#endif //APP_UART_ENABLED -// - -// APP_USBD_CLASS_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class - - -#ifndef APP_USBD_CLASS_AUDIO_ENABLED -#define APP_USBD_CLASS_AUDIO_ENABLED 0 -#endif - -// APP_USBD_CLASS_HID_ENABLED - app_usbd_hid - USB HID class - - -#ifndef APP_USBD_CLASS_HID_ENABLED -#define APP_USBD_CLASS_HID_ENABLED 0 -#endif - -// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic - - -#ifndef APP_USBD_HID_GENERIC_ENABLED -#define APP_USBD_HID_GENERIC_ENABLED 0 -#endif - -// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard - - -#ifndef APP_USBD_HID_KBD_ENABLED -#define APP_USBD_HID_KBD_ENABLED 0 -#endif - -// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse - - -#ifndef APP_USBD_HID_MOUSE_ENABLED -#define APP_USBD_HID_MOUSE_ENABLED 0 -#endif - -// BUTTON_ENABLED - app_button - buttons handling module - - -#ifndef BUTTON_ENABLED -#define BUTTON_ENABLED 1 -#endif - -// CRC16_ENABLED - crc16 - CRC16 calculation routines - - -#ifndef CRC16_ENABLED -#define CRC16_ENABLED 0 -#endif - -// CRC32_ENABLED - crc32 - CRC32 calculation routines - - -#ifndef CRC32_ENABLED -#define CRC32_ENABLED 0 -#endif - -// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library - - -#ifndef ECC_ENABLED -#define ECC_ENABLED 0 -#endif - -// FDS_ENABLED - fds - Flash data storage module -//========================================================== -#ifndef FDS_ENABLED -#define FDS_ENABLED 0 -#endif -#if FDS_ENABLED -// FDS_OP_QUEUE_SIZE - Size of the internal queue. -#ifndef FDS_OP_QUEUE_SIZE -#define FDS_OP_QUEUE_SIZE 4 -#endif - -// FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. -#ifndef FDS_CHUNK_QUEUE_SIZE -#define FDS_CHUNK_QUEUE_SIZE 8 -#endif - -// FDS_MAX_USERS - Maximum number of callbacks that can be registered. -#ifndef FDS_MAX_USERS -#define FDS_MAX_USERS 8 -#endif - -// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. -// One of the virtual pages is reserved by the system for garbage collection. -// Therefore, the minimum is two virtual pages: one page to store data and -// one page to be used by the system for garbage collection. The total amount -// of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES -// @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. - -#ifndef FDS_VIRTUAL_PAGES -#define FDS_VIRTUAL_PAGES 3 -#endif - -// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual page of flash memory, expressed in number of 4-byte words. - - -// By default, a virtual page is the same size as a physical page. -// The size of a virtual page must be a multiple of the size of a physical page. -// <1024=> 1024 -// <2048=> 2048 - -#ifndef FDS_VIRTUAL_PAGE_SIZE -#define FDS_VIRTUAL_PAGE_SIZE 1024 -#endif - -#endif //FDS_ENABLED -// - -// FSTORAGE_ENABLED - fstorage - Flash storage module -//========================================================== -#ifndef FSTORAGE_ENABLED -#define FSTORAGE_ENABLED 1 -#endif -#if FSTORAGE_ENABLED -// FS_QUEUE_SIZE - Configures the size of the internal queue. -// Increase this if there are many users, or if it is likely that many -// operation will be queued at once without waiting for the previous operations -// to complete. In general, increase the queue size if you frequently receive -// @ref FS_ERR_QUEUE_FULL errors when calling @ref fs_store or @ref fs_erase. - -#ifndef FS_QUEUE_SIZE -#define FS_QUEUE_SIZE 4 -#endif - -// FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. -// Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT -// error often. The SoftDevice may fail to schedule flash access due to high BLE activity. - -#ifndef FS_OP_MAX_RETRIES -#define FS_OP_MAX_RETRIES 3 -#endif - -// FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. -// Tweaking this value can increase the chances of the SoftDevice being -// able to fit flash operations in between radio activity. This value is bound by the -// maximum number of words which the SoftDevice can write to flash in a single call to -// @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs. - -#ifndef FS_MAX_WRITE_SIZE_WORDS -#define FS_MAX_WRITE_SIZE_WORDS 1024 -#endif - -#endif //FSTORAGE_ENABLED -// - -// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release - - -#ifndef HARDFAULT_HANDLER_ENABLED -#define HARDFAULT_HANDLER_ENABLED 0 -#endif - -// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI -//========================================================== -#ifndef HCI_MEM_POOL_ENABLED -#define HCI_MEM_POOL_ENABLED 0 -#endif -#if HCI_MEM_POOL_ENABLED -// HCI_TX_BUF_SIZE - TX buffer size in bytes. -#ifndef HCI_TX_BUF_SIZE -#define HCI_TX_BUF_SIZE 600 -#endif - -// HCI_RX_BUF_SIZE - RX buffer size in bytes. -#ifndef HCI_RX_BUF_SIZE -#define HCI_RX_BUF_SIZE 600 -#endif - -// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. -#ifndef HCI_RX_BUF_QUEUE_SIZE -#define HCI_RX_BUF_QUEUE_SIZE 4 -#endif - -#endif //HCI_MEM_POOL_ENABLED -// - -// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI -//========================================================== -#ifndef HCI_SLIP_ENABLED -#define HCI_SLIP_ENABLED 0 -#endif -#if HCI_SLIP_ENABLED -// HCI_UART_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud - -#ifndef HCI_UART_BAUDRATE -#define HCI_UART_BAUDRATE 30801920 -#endif - -// HCI_UART_FLOW_CONTROL - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef HCI_UART_FLOW_CONTROL -#define HCI_UART_FLOW_CONTROL 0 -#endif - -// HCI_UART_RX_PIN - UART RX pin -#ifndef HCI_UART_RX_PIN -#define HCI_UART_RX_PIN 8 -#endif - -// HCI_UART_TX_PIN - UART TX pin -#ifndef HCI_UART_TX_PIN -#define HCI_UART_TX_PIN 6 -#endif - -// HCI_UART_RTS_PIN - UART RTS pin -#ifndef HCI_UART_RTS_PIN -#define HCI_UART_RTS_PIN 5 -#endif - -// HCI_UART_CTS_PIN - UART CTS pin -#ifndef HCI_UART_CTS_PIN -#define HCI_UART_CTS_PIN 7 -#endif - -#endif //HCI_SLIP_ENABLED -// - -// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport -//========================================================== -#ifndef HCI_TRANSPORT_ENABLED -#define HCI_TRANSPORT_ENABLED 0 -#endif -#if HCI_TRANSPORT_ENABLED -// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. -#ifndef HCI_MAX_PACKET_SIZE_IN_BITS -#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 -#endif - -#endif //HCI_TRANSPORT_ENABLED -// - -// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module - - -#ifndef LED_SOFTBLINK_ENABLED -#define LED_SOFTBLINK_ENABLED 0 -#endif - -// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module - - -#ifndef LOW_POWER_PWM_ENABLED -#define LOW_POWER_PWM_ENABLED 0 -#endif - -// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator -//========================================================== -#ifndef MEM_MANAGER_ENABLED -#define MEM_MANAGER_ENABLED 0 -#endif -#if MEM_MANAGER_ENABLED -// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> - - -#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT -#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 -#endif - -// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. -// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE -#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 -#endif - -// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> - - -#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT -#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. -// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 -#endif - -// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> - - -#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT -#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. -// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE -#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 -#endif - -// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> - - -#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT -#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. -// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE -#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 -#endif - -// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> - - -#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT -#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. -// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 -#endif - -// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> - - -#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT -#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. -// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE -#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 -#endif - -// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> - - -#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT -#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 -#endif - -// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. -// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. - -#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 -#endif - -// MEM_MANAGER_ENABLE_LOGS - Enable debug trace in the module. - - -#ifndef MEM_MANAGER_ENABLE_LOGS -#define MEM_MANAGER_ENABLE_LOGS 0 -#endif - -// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. - - -#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK -#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 -#endif - -#endif //MEM_MANAGER_ENABLED -// - -// NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module -//========================================================== -#ifndef NRF_CSENSE_ENABLED -#define NRF_CSENSE_ENABLED 0 -#endif -#if NRF_CSENSE_ENABLED -// NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. -#ifndef NRF_CSENSE_PAD_HYSTERESIS -#define NRF_CSENSE_PAD_HYSTERESIS 15 -#endif - -// NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. -#ifndef NRF_CSENSE_PAD_DEVIATION -#define NRF_CSENSE_PAD_DEVIATION 70 -#endif - -// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. -#ifndef NRF_CSENSE_MIN_PAD_VALUE -#define NRF_CSENSE_MIN_PAD_VALUE 20 -#endif - -// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. -#ifndef NRF_CSENSE_MAX_PADS_NUMBER -#define NRF_CSENSE_MAX_PADS_NUMBER 20 -#endif - -// NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. -#ifndef NRF_CSENSE_MAX_VALUE -#define NRF_CSENSE_MAX_VALUE 1000 -#endif - -// NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. -// This is used when capacitive sensor does not use COMP. - -#ifndef NRF_CSENSE_OUTPUT_PIN -#define NRF_CSENSE_OUTPUT_PIN 26 -#endif - -#endif //NRF_CSENSE_ENABLED -// - -// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module -//========================================================== -#ifndef NRF_DRV_CSENSE_ENABLED -#define NRF_DRV_CSENSE_ENABLED 0 -#endif -#if NRF_DRV_CSENSE_ENABLED -// USE_COMP - Use the comparator to implement the capacitive sensor driver. - -// Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation. -//========================================================== -#ifndef USE_COMP -#define USE_COMP 0 -#endif -#if USE_COMP -// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). -#ifndef TIMER0_FOR_CSENSE -#define TIMER0_FOR_CSENSE 1 -#endif - -// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). -#ifndef TIMER1_FOR_CSENSE -#define TIMER1_FOR_CSENSE 2 -#endif - -// MEASUREMENT_PERIOD - Single measurement period. -// Time of a single measurement can be calculated as -// T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). -// I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad. - -#ifndef MEASUREMENT_PERIOD -#define MEASUREMENT_PERIOD 20 -#endif - -#endif //USE_COMP -// - -#endif //NRF_DRV_CSENSE_ENABLED -// - -// NRF_QUEUE_ENABLED - nrf_queue - Queue module - - -#ifndef NRF_QUEUE_ENABLED -#define NRF_QUEUE_ENABLED 0 -#endif - -// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. - - -#ifndef NRF_STRERROR_ENABLED -#define NRF_STRERROR_ENABLED 1 -#endif - -// RETARGET_ENABLED - retarget - Retargeting stdio functions - - -#ifndef RETARGET_ENABLED -#define RETARGET_ENABLED 1 -#endif - -// SLIP_ENABLED - slip - SLIP encoding and decoding - - -#ifndef SLIP_ENABLED -#define SLIP_ENABLED 0 -#endif - -// app_usbd_cdc_acm - USB CDC ACM class - -//========================================================== -// APP_USBD_CLASS_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library - - -#ifndef APP_USBD_CLASS_CDC_ACM_ENABLED -#define APP_USBD_CLASS_CDC_ACM_ENABLED 0 -#endif - -// APP_USBD_CDC_ACM_LOG_ENABLED - Enables logging in the module. - - -#ifndef APP_USBD_CDC_ACM_LOG_ENABLED -#define APP_USBD_CDC_ACM_LOG_ENABLED 0 -#endif - -// -//========================================================== - -// app_usbd_msc - USB MSC class - -//========================================================== -// APP_USBD_CLASS_MSC_ENABLED - Enabling USBD MSC Class library - - -#ifndef APP_USBD_CLASS_MSC_ENABLED -#define APP_USBD_CLASS_MSC_ENABLED 0 -#endif - -// APP_USBD_MSC_CLASS_LOG_ENABLED - Enables logging in the module. - - -#ifndef APP_USBD_MSC_CLASS_LOG_ENABLED -#define APP_USBD_MSC_CLASS_LOG_ENABLED 0 -#endif - -// -//========================================================== - -// -//========================================================== - -// nRF_Log - -//========================================================== -// NRF_LOG_ENABLED - nrf_log - Logging -//========================================================== -#ifndef NRF_LOG_ENABLED -#define NRF_LOG_ENABLED 0 -#endif -#if NRF_LOG_ENABLED -// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string -//========================================================== -#ifndef NRF_LOG_USES_COLORS -#define NRF_LOG_USES_COLORS 0 -#endif -#if NRF_LOG_USES_COLORS -// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_COLOR_DEFAULT -#define NRF_LOG_COLOR_DEFAULT 0 -#endif - -// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_ERROR_COLOR -#define NRF_LOG_ERROR_COLOR 0 -#endif - -// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRF_LOG_WARNING_COLOR -#define NRF_LOG_WARNING_COLOR 0 -#endif - -#endif //NRF_LOG_USES_COLORS -// - -// NRF_LOG_DEFAULT_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRF_LOG_DEFAULT_LEVEL -#define NRF_LOG_DEFAULT_LEVEL 3 -#endif - -// NRF_LOG_DEFERRED - Enable deffered logger. - -// Log data is buffered and can be processed in idle. -//========================================================== -#ifndef NRF_LOG_DEFERRED -#define NRF_LOG_DEFERRED 0 -#endif -#if NRF_LOG_DEFERRED -// NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. -// Must be power of 2 - -#ifndef NRF_LOG_DEFERRED_BUFSIZE -#define NRF_LOG_DEFERRED_BUFSIZE 256 -#endif - -#endif //NRF_LOG_DEFERRED -// - -// NRF_LOG_USES_TIMESTAMP - Enable timestamping - - -// Function for getting the timestamp is provided by the user - -#ifndef NRF_LOG_USES_TIMESTAMP -#define NRF_LOG_USES_TIMESTAMP 0 -#endif - -#endif //NRF_LOG_ENABLED -// - -// nrf_log_backend - Logging sink - -//========================================================== -// NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string -// Logger backend RAM usage is determined by this value. - -#ifndef NRF_LOG_BACKEND_MAX_STRING_LENGTH -#define NRF_LOG_BACKEND_MAX_STRING_LENGTH 256 -#endif - -// NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp -// If higher resolution timestamp source is used it might be needed to increase that - -#ifndef NRF_LOG_TIMESTAMP_DIGITS -#define NRF_LOG_TIMESTAMP_DIGITS 8 -#endif - -// NRF_LOG_BACKEND_SERIAL_USES_UART - If enabled data is printed over UART -//========================================================== -#ifndef NRF_LOG_BACKEND_SERIAL_USES_UART -#define NRF_LOG_BACKEND_SERIAL_USES_UART 0 -#endif -#if NRF_LOG_BACKEND_SERIAL_USES_UART -// NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <10289152=> 38400 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 57600 baud - -#ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE -#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30801920 -#endif - -// NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin -#ifndef NRF_LOG_BACKEND_SERIAL_UART_TX_PIN -#define NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 4 -#endif - -// NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin -#ifndef NRF_LOG_BACKEND_SERIAL_UART_RX_PIN -#define NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 3 -#endif - -// NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin -#ifndef NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN -#define NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 5 -#endif - -// NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin -#ifndef NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN -#define NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 7 -#endif - -// NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL -#define NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 0 -#endif - -// NRF_LOG_BACKEND_UART_INSTANCE - UART instance used - -// <0=> 0 - -#ifndef NRF_LOG_BACKEND_UART_INSTANCE -#define NRF_LOG_BACKEND_UART_INSTANCE 0 -#endif - -#endif //NRF_LOG_BACKEND_SERIAL_USES_UART -// - -// NRF_LOG_BACKEND_SERIAL_USES_RTT - If enabled data is printed using RTT -//========================================================== -#ifndef NRF_LOG_BACKEND_SERIAL_USES_RTT -#define NRF_LOG_BACKEND_SERIAL_USES_RTT 0 -#endif -#if NRF_LOG_BACKEND_SERIAL_USES_RTT -// NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size. -// Should be equal or bigger than \ref NRF_LOG_BACKEND_MAX_STRING_LENGTH. -// This value is used in Segger RTT configuration to set the buffer size -// if it is bigger than default RTT buffer size. - -#ifndef NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE -#define NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE 512 -#endif - -#endif //NRF_LOG_BACKEND_SERIAL_USES_RTT -// - -// -//========================================================== - -// -//========================================================== - -// nRF_Segger_RTT - -//========================================================== -// segger_rtt - SEGGER RTT - -//========================================================== -// SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. -// Note that either @ref NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE -// or this value is actually used. It depends on which one is bigger. - -#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP -#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 64 -#endif - -// SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer. -#ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS -#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2 -#endif - -// SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer. -#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN -#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 -#endif - -// SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer. -#ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS -#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2 -#endif - -// SEGGER_RTT_CONFIG_DEFAULT_MODE - RTT behavior if the buffer is full. - - -// The following modes are supported: -// - SKIP - Do not block, output nothing. -// - TRIM - Do not block, output as much as fits. -// - BLOCK - Wait until there is space in the buffer. -// <0=> SKIP -// <1=> TRIM -// <2=> BLOCK_IF_FIFO_FULL - -#ifndef SEGGER_RTT_CONFIG_DEFAULT_MODE -#define SEGGER_RTT_CONFIG_DEFAULT_MODE 0 -#endif - -// -//========================================================== - -// -//========================================================== - -// <<< end of configuration section >>> -#endif //SDK_CONFIG_H - diff --git a/bsp/nrf5x/nrf52832/applications/startup.c b/bsp/nrf5x/nrf52832/applications/startup.c deleted file mode 100644 index a48524814cb4c2e9082ceceb82dd773c7ed8315d..0000000000000000000000000000000000000000 --- a/bsp/nrf5x/nrf52832/applications/startup.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2015-03-01 Yangfs the first version - * 2015-03-27 Bernard code cleanup. - */ - -#include -#include - -#include "board.h" - -/** - * @addtogroup NRF52832 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define NRF_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define NRF_SRAM_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define NRF_SRAM_BEGIN (&__bss_end) -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)NRF_SRAM_BEGIN, (void*)CHIP_SRAM_END); -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_init(); -#endif - - /* init application */ - rt_application_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - // rt_hw_interrupt_disable(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/nrf5x/nrf52832/board/Kconfig b/bsp/nrf5x/nrf52832/board/Kconfig index 40823ab976dba16484776fd6078b61a0f64ad59b..5241d56318a9a8bdb299a84c414fb7f0a5b6a0d3 100644 --- a/bsp/nrf5x/nrf52832/board/Kconfig +++ b/bsp/nrf5x/nrf52832/board/Kconfig @@ -2,21 +2,293 @@ menu "Hardware Drivers Config" config SOC_NRF52832 bool + config SOC_NRF52832 select RT_USING_COMPONENTS_INIT - # select RT_USING_USER_MAIN + select RT_USING_USER_MAIN + default y + +config SOC_NORDIC + bool + config SOC_NORDIC default y -menu "Onboard Peripheral Drivers" +menu "Onboard Peripheral Drivers" + config BSP_USING_JLINK_TO_USART + bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)" + select BSP_USING_UART + select BSP_USING_UART0 + default y endmenu menu "On-chip Peripheral Drivers" - + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + menuconfig BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default n + if BSP_USING_PWM + config NRFX_PWM_ENABLED + int + default 1 + config BSP_USING_PWM0 + bool "Enable PWM0 bus" + default y + if BSP_USING_PWM0 + config NRFX_PWM0_ENABLED + int + default 1 + config BSP_USING_PWM0_CH0 + int "PWM0 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM0_CH1 + int "PWM0 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM0_CH2 + int "PWM0 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM0_CH3 + int "PWM0 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM1 + bool "Enable PWM1 bus" + default n + if BSP_USING_PWM1 + config NRFX_PWM1_ENABLED + int + default 1 + config BSP_USING_PWM1_CH0 + int "PWM1 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM1_CH1 + int "PWM1 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM1_CH2 + int "PWM1 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM1_CH3 + int "PWM1 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM2 + bool "Enable PWM2 bus" + default n + if BSP_USING_PWM2 + config NRFX_PWM2_ENABLED + int + default 1 + config BSP_USING_PWM2_CH0 + int "PWM2 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM2_CH1 + int "PWM2 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM2_CH2 + int "PWM2 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM2_CH3 + int "PWM2 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM3 + bool "Enable PWM3 bus" + default n + if BSP_USING_PWM3 + config NRFX_PWM3_ENABLED + int + default 1 + config BSP_USING_PWM3_CH0 + int "PWM3 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM3_CH1 + int "PWM3 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM3_CH2 + int "PWM3 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM3_CH3 + int "PWM3 channel 3 pin number set" + range 0 47 + default 16 + endif + endif + menuconfig BSP_USING_SOFTDEVICE + bool "Enable NRF SOFTDEVICE" + select PKG_USING_NRF5X_SDK + select NRFX_CLOCK_ENABLED + default n +if BSP_USING_SOFTDEVICE + config NRFX_CLOCK_ENABLED + int + default 1 + config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY + int + default 7 + config NRFX_RTC_ENABLED + int + default 1 + config NRFX_RTC1_ENABLED + int + default 1 + config NRF_CLOCK_ENABLED + int + default 1 + config NRF_SDH_BLE_ENABLED + int + default 1 + config NRF_SDH_ENABLED + int + default 1 + config NRF_SDH_SOC_ENABLED + int + default 1 +endif menuconfig BSP_USING_UART bool "Enable UART" default y select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_PIN + int "uart0 rx pin number" + range 0 31 + default 8 + config BSP_UART0_TX_PIN + int "uart0 tx pin number" + range 0 31 + default 6 + endif + config BSP_USING_UART1 + bool "Enable UART1" + default n + endif + + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_PIN + default y + + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 bus" + default y + if BSP_USING_SPI0 + config BSP_SPI0_SCK_PIN + int "SPI0 sck pin number set" + range 0 47 + default 28 + config BSP_SPI0_MOSI_PIN + int "SPI0 mosi pin number set" + range 0 47 + default 29 + config BSP_SPI0_MISO_PIN + int "SPI0 miso pin number set" + range 0 47 + default 30 + config BSP_SPI0_SS_PIN + int "SPI0 ss pin number set" + range 0 47 + default 31 + endif + + config BSP_USING_SPI1 + bool "Enable SPI1 bus" + default n + if BSP_USING_SPI1 + config BSP_SPI1_SCK_PIN + int "SPI0 sck pin number set" + range 0 47 + default 28 + config BSP_SPI1_MOSI_PIN + int "SPI0 mosi pin number set" + range 0 47 + default 29 + config BSP_SPI1_MISO_PIN + int "SPI0 miso pin number set" + range 0 47 + default 30 + config BSP_SPI1_SS_PIN + int "SPI0 ss pin number set" + range 0 47 + default 31 + endif + + config BSP_USING_SPI2 + bool "Enable SPI2 bus" + default n + if BSP_USING_SPI2 + config BSP_SPI2_SCK_PIN + int "SPI0 sck pin number set" + range 0 47 + default 28 + config BSP_SPI2_MOSI_PIN + int "SPI0 mosi pin number set" + range 0 47 + default 29 + config BSP_SPI2_MISO_PIN + int "SPI0 miso pin number set" + range 0 47 + default 30 + config BSP_SPI2_SS_PIN + int "SPI0 ss pin number set" + range 0 47 + default 31 + endif + + endif + config BSP_USING_ON_CHIP_FLASH + select PKG_USING_FAL + bool "Enable on-chip FLASH" + default n + + menu "On-chip flash config" + + config MCU_FLASH_START_ADDRESS + hex "MCU FLASH START ADDRESS" + default 0x00000000 + + config MCU_FLASH_SIZE_KB + int "MCU FLASH SIZE, MAX size 1024 KB" + range 1 1024 + default 1024 + + config MCU_SRAM_START_ADDRESS + hex "MCU RAM START ADDRESS" + default 0x20000000 + + config MCU_SRAM_SIZE_KB + int "MCU RAM SIZE, MAX size 256 KB" + range 1 256 + default 256 + + config MCU_FLASH_PAGE_SIZE + hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000" + range 0x1000 0x1000 + default 0x1000 + endmenu endmenu endmenu diff --git a/bsp/nrf5x/nrf52832/board/SConscript b/bsp/nrf5x/nrf52832/board/SConscript index abe43c5729bf5ebe6ec6f407730dc5d6ab71d3de..27bcddd310ef877eddb64c102a1223cd64e316ab 100644 --- a/bsp/nrf5x/nrf52832/board/SConscript +++ b/bsp/nrf5x/nrf52832/board/SConscript @@ -5,6 +5,7 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] +define = ['USE_APP_CONFIG'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define) Return('group') diff --git a/bsp/nrf5x/nrf52832/board/app_config.h b/bsp/nrf5x/nrf52832/board/app_config.h new file mode 100644 index 0000000000000000000000000000000000000000..7909dd55b40302110c38ebf2427d3b36bb83b07a --- /dev/null +++ b/bsp/nrf5x/nrf52832/board/app_config.h @@ -0,0 +1,4 @@ +#ifndef APP_CONFIG_H +#define APP_CONFIG_H + +#endif //APP_CONFIG_H diff --git a/bsp/nrf5x/nrf52832/board/board.c b/bsp/nrf5x/nrf52832/board/board.c index 7ff8bfd9c4ed378f16c5fc5c4e9b5f8dc4d77592..d1e55f4c49c92106fadbe9742cae86ea86af4aca 100644 --- a/bsp/nrf5x/nrf52832/board/board.c +++ b/bsp/nrf5x/nrf52832/board/board.c @@ -1,220 +1,110 @@ -#include "board.h" -#include "drv_uart.h" -#include "app_util_platform.h" -#include "nrf_drv_common.h" -#include "nrf_systick.h" -#include "nrf_rtc.h" -#include "nrf_drv_clock.h" -#include "softdevice_handler.h" -#include "nrf_drv_uart.h" -#include "nrf_gpio.h" - +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-29 supperthomas first version + * + */ #include #include +#include -#define TICK_RATE_HZ RT_TICK_PER_SECOND -#define SYSTICK_CLOCK_HZ ( 32768UL ) - -#define NRF_RTC_REG NRF_RTC1 - /* IRQn used by the selected RTC */ -#define NRF_RTC_IRQn RTC1_IRQn - /* Constants required to manipulate the NVIC. */ -#define NRF_RTC_PRESCALER ( (uint32_t) (ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) ) - /* Maximum RTC ticks */ -#define NRF_RTC_MAXTICKS ((1U<<24)-1U) - -static volatile uint32_t m_tick_overflow_count = 0; -#define NRF_RTC_BITWIDTH 24 -#define OSTick_Handler RTC1_IRQHandler -#define EXPECTED_IDLE_TIME_BEFORE_SLEEP 2 - -void SysTick_Configuration(void) -{ - nrf_drv_clock_lfclk_request(NULL); - - /* Configure SysTick to interrupt at the requested rate. */ - nrf_rtc_prescaler_set(NRF_RTC_REG, NRF_RTC_PRESCALER); - nrf_rtc_int_enable (NRF_RTC_REG, RTC_INTENSET_TICK_Msk); - nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_CLEAR); - nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_START); - nrf_rtc_event_enable(NRF_RTC_REG, RTC_EVTEN_OVRFLW_Msk); - - NVIC_SetPriority(NRF_RTC_IRQn, 0xF); - NVIC_EnableIRQ(NRF_RTC_IRQn); -} +#include "board.h" +#include "drv_uart.h" +#ifdef BSP_USING_SOFTDEVICE +#include +#include +#include "app_error.h" +#include "nrf_drv_clock.h" +const nrfx_rtc_t rtc = NRFX_RTC_INSTANCE(1); /**< Declaring an instance of nrf_drv_rtc for RTC0. */ -static rt_tick_t _tick_distance(void) +static void rtc_handler(nrfx_rtc_int_type_t int_type) { - nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0); + if (int_type == NRFX_RTC_INT_TICK) + { + rt_interrupt_enter(); - uint32_t systick_counter = nrf_rtc_counter_get(NRF_RTC_REG); - nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK); + rt_tick_increase(); - /* check for overflow in TICK counter */ - if(nrf_rtc_event_pending(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW)) - { - nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW); - m_tick_overflow_count++; + rt_interrupt_leave(); } - - return ((m_tick_overflow_count << NRF_RTC_BITWIDTH) + systick_counter) - rt_tick_get(); } - -void OSTick_Handler( void ) +#else +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) { - uint32_t diff; - - /* enter interrupt */ + /* enter interrupt */ rt_interrupt_enter(); - diff = _tick_distance(); - while((diff--) > 0) - { - if (rt_thread_self() != RT_NULL) - { - rt_tick_increase(); - } - } + rt_tick_increase(); + /* leave interrupt */ rt_interrupt_leave(); } - -static void _wakeup_tick_adjust(void) -{ - uint32_t diff; - uint32_t level; - - level = rt_hw_interrupt_disable(); - - diff = _tick_distance(); - - rt_tick_set(rt_tick_get() + diff); - - if (rt_thread_self() != RT_NULL) - { - struct rt_thread *thread; - - /* check time slice */ - thread = rt_thread_self(); - - if (thread->remaining_tick <= diff) - { - /* change to initialized tick */ - thread->remaining_tick = thread->init_tick; - - /* yield */ - rt_thread_yield(); - } - else - { - thread->remaining_tick -= diff; - } - - /* check timer */ - rt_timer_check(); - } - - rt_hw_interrupt_enable(level); -} - -static void _sleep_ongo( uint32_t sleep_tick ) +#endif +void SysTick_Configuration(void) { - uint32_t enterTime; - uint32_t entry_tick; - - /* Make sure the SysTick reload value does not overflow the counter. */ - if ( sleep_tick > NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP ) - { - sleep_tick = NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP; - } - - rt_enter_critical(); - - enterTime = nrf_rtc_counter_get(NRF_RTC_REG); - - { - uint32_t wakeupTime = (enterTime + sleep_tick) & NRF_RTC_MAXTICKS; - - /* Stop tick events */ - nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_TICK_MASK); - - /* Configure CTC interrupt */ - nrf_rtc_cc_set(NRF_RTC_REG, 0, wakeupTime); - nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0); - nrf_rtc_int_enable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK); +#ifdef BSP_USING_SOFTDEVICE + nrf_drv_clock_init(); + nrf_drv_clock_lfclk_request(NULL); - entry_tick = rt_tick_get(); + uint32_t err_code; +#define TICK_RATE_HZ RT_TICK_PER_SECOND +#define SYSTICK_CLOCK_HZ ( 32768UL ) - __DSB(); +#define NRF_RTC_REG NRF_RTC1 + /* IRQn used by the selected RTC */ +#define NRF_RTC_IRQn RTC1_IRQn + /* Constants required to manipulate the NVIC. */ +#define NRF_RTC_PRESCALER ( (uint32_t) (NRFX_ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) ) + nrfx_rtc_config_t config = NRFX_RTC_DEFAULT_CONFIG; + config.prescaler = NRF_RTC_PRESCALER; + + err_code = nrfx_rtc_init(&rtc, &config, rtc_handler); + // APP_ERROR_CHECK(err_code); + nrfx_rtc_tick_enable(&rtc, true); +#define COMPARE_COUNTERTIME (3UL) /**< Get Compare event COMPARE_TIME seconds after the counter starts from 0. */ + //Set compare channel to trigger interrupt after COMPARE_COUNTERTIME seconds + err_code = nrfx_rtc_cc_set(&rtc, 0, COMPARE_COUNTERTIME * 8, true); + // APP_ERROR_CHECK(err_code); + + //Power on RTC instance + nrfx_rtc_enable(&rtc); +#else + /* Set interrupt priority */ + NVIC_SetPriority(SysTick_IRQn, 0xf); - if ( sleep_tick > 0 ) - { -#ifdef SOFTDEVICE_PRESENT - if (softdevice_handler_is_enabled()) - { - uint32_t err_code = sd_app_evt_wait(); - APP_ERROR_CHECK(err_code); - } - else + /* Configure SysTick to interrupt at the requested rate. */ + nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND); + nrf_systick_val_clear(); + nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE + | NRF_SYSTICK_CSR_ENABLE); #endif - { - /* No SD - we would just block interrupts globally. - * BASEPRI cannot be used for that because it would prevent WFE from wake up. - */ - do{ - __WFE(); - } while (0 == (NVIC->ISPR[0] | NVIC->ISPR[1])); - } - } - - nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK); - nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0); - - _wakeup_tick_adjust(); - - /* Correct the system ticks */ - { - - nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK); - nrf_rtc_int_enable (NRF_RTC_REG, NRF_RTC_INT_TICK_MASK); - /* It is important that we clear pending here so that our corrections are latest and in sync with tick_interrupt handler */ - NVIC_ClearPendingIRQ(NRF_RTC_IRQn); - } - - // rt_kprintf("entry tick:%u, expected:%u, current tick:%u\n", entry_tick, sleep_tick, rt_tick_get()); - } - - rt_exit_critical(); } -void rt_hw_system_powersave(void) -{ - uint32_t sleep_tick; - - sleep_tick = rt_timer_next_timeout_tick() - rt_tick_get(); - - if ( sleep_tick >= EXPECTED_IDLE_TIME_BEFORE_SLEEP) - { - // rt_kprintf("sleep entry:%u\n", rt_tick_get()); - _sleep_ongo( sleep_tick ); - } -} - void rt_hw_board_init(void) { + rt_hw_interrupt_enable(0); // sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE); /* Activate deep sleep mode */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - nrf_drv_clock_init(); - // nrf_drv_clock_hfclk_request(0); - SysTick_Configuration(); - rt_thread_idle_sethook(rt_hw_system_powersave); +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_SERIAL rt_hw_uart_init(); +#endif #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); @@ -223,5 +113,20 @@ void rt_hw_board_init(void) #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif + +#ifdef BSP_USING_SOFTDEVICE + extern uint32_t Image$$RW_IRAM1$$Base; + uint32_t const *const m_ram_start = &Image$$RW_IRAM1$$Base; + if ((uint32_t)m_ram_start == 0x20000000) + { + rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start); + while (1); + } + else + { + rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start); + } +#endif + } diff --git a/bsp/nrf5x/nrf52832/board/board.h b/bsp/nrf5x/nrf52832/board/board.h index f9d291792a72002b1d74a9b736971e71b568a634..f80896078074199fdac2d85c2d23d3631d053b19 100644 --- a/bsp/nrf5x/nrf52832/board/board.h +++ b/bsp/nrf5x/nrf52832/board/board.h @@ -2,10 +2,26 @@ #define _BOARD_H_ #include - +#include #include "nrf.h" -#define CHIP_SRAM_END (0x20000000 + 64*1024) +#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024 +#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE)) +#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024 +#define MCU_SRAM_END_ADDRESS (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END (0x20000000 + 64*1024) void rt_hw_board_init(void); diff --git a/bsp/nrf5x/nrf52832/board/linker_scripts/link.sct b/bsp/nrf5x/nrf52832/board/linker_scripts/link.sct index 0200e96087ef805bed85a9a25f71ede3630d08d2..a2f8ebd922a9198f5d05cf4d1a45d8ec460f2594 100644 --- a/bsp/nrf5x/nrf52832/board/linker_scripts/link.sct +++ b/bsp/nrf5x/nrf52832/board/linker_scripts/link.sct @@ -2,13 +2,13 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x0001F000 0x00061000 { ; load region size_region - ER_IROM1 0x0001F000 0x00061000 { ; load address = execution address +LR_IROM1 0x00000000 0x100000 { ; load region size_region + ER_IROM1 0x00000000 0x100000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x200025F8 0x0000DA08 { ; RW data + RW_IRAM1 0x20000000 0x40000 { ; RW data .ANY (+RW +ZI) } } diff --git a/bsp/nrf5x/nrf52832/board/nrfx_config.h b/bsp/nrf5x/nrf52832/board/nrfx_config.h new file mode 100644 index 0000000000000000000000000000000000000000..b006b6bcd5e528259502801ff846dc6d915ad69b --- /dev/null +++ b/bsp/nrf5x/nrf52832/board/nrfx_config.h @@ -0,0 +1,47 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +// TODO - temporary redirection +#include + +#endif // NRFX_CONFIG_H__ diff --git a/bsp/nrf5x/nrf52832/board/nrfx_glue.h b/bsp/nrf5x/nrf52832/board/nrfx_glue.h new file mode 100644 index 0000000000000000000000000000000000000000..28025dafaece4ae2e94153a1714f7528f12261d9 --- /dev/null +++ b/bsp/nrf5x/nrf52832/board/nrfx_glue.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif +#include +#include "nrf.h" +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +#include + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to be set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) NVIC_SetPriority(irq_number, priority) + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) NVIC_EnableIRQ(irq_number) + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) + +/** @brief Macro for entering into a critical section. */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** @brief Macro for exiting from a critical section. */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#define NRFX_DELAY_US(us_time) + +//------------------------------------------------------------------------------ + +/** @brief Atomic 32-bit unsigned type. */ +#define nrfx_atomic_t + +/** + * @brief Macro for storing a value to an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) + +/** + * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the OR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) + +/** + * @brief Macro for running a bitwise AND operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the AND operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) + +/** + * @brief Macro for running a bitwise XOR operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the XOR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) + +/** + * @brief Macro for running an addition operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the ADD operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) + +/** + * @brief Macro for running a subtraction operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_GROUPS_USED 0 + +/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_GROUPS_USED 0 + +/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */ +#define NRFX_EGUS_USED 0 + +/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/bsp/nrf5x/nrf52832/board/nrfx_log.h b/bsp/nrf5x/nrf52832/board/nrfx_log.h new file mode 100644 index 0000000000000000000000000000000000000000..80d8efbdf13099a02c6a1359336167353f7a032f --- /dev/null +++ b/bsp/nrf5x/nrf52832/board/nrfx_log.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/bsp/nrf5x/nrf52832/board/sdk_config.h b/bsp/nrf5x/nrf52832/board/sdk_config.h new file mode 100644 index 0000000000000000000000000000000000000000..172e0ccc2cb18fe53f0242b3db4d891f765ed129 --- /dev/null +++ b/bsp/nrf5x/nrf52832/board/sdk_config.h @@ -0,0 +1,11704 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H +// <<< Use Configuration Wizard in Context Menu >>>\n +#ifdef USE_APP_CONFIG +#include "app_config.h" +#endif +// nRF_BLE + +#include +//========================================================== +// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module + + +#ifndef BLE_ADVERTISING_ENABLED +#define BLE_ADVERTISING_ENABLED 0 +#endif + +// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands + + +#ifndef BLE_DTM_ENABLED +#define BLE_DTM_ENABLED 0 +#endif + +// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library + + +#ifndef BLE_RACP_ENABLED +#define BLE_RACP_ENABLED 0 +#endif + +// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) +//========================================================== +#ifndef NRF_BLE_QWR_ENABLED +#define NRF_BLE_QWR_ENABLED 0 +#endif +// NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. +#ifndef NRF_BLE_QWR_MAX_ATTR +#define NRF_BLE_QWR_MAX_ATTR 0 +#endif + +// + +// PEER_MANAGER_ENABLED - peer_manager - Peer Manager +//========================================================== +#ifndef PEER_MANAGER_ENABLED +#define PEER_MANAGER_ENABLED 0 +#endif +// PM_MAX_REGISTRANTS - Number of event handlers that can be registered. +#ifndef PM_MAX_REGISTRANTS +#define PM_MAX_REGISTRANTS 3 +#endif + +// PM_FLASH_BUFFERS - Number of internal buffers for flash operations. +// Decrease this value to lower RAM usage. + +#ifndef PM_FLASH_BUFFERS +#define PM_FLASH_BUFFERS 4 +#endif + +// PM_CENTRAL_ENABLED - Enable/disable central-specific Peer Manager functionality. + + +// Enable/disable central-specific Peer Manager functionality. + +#ifndef PM_CENTRAL_ENABLED +#define PM_CENTRAL_ENABLED 1 +#endif + +// PM_SERVICE_CHANGED_ENABLED - Enable/disable the service changed management for GATT server in Peer Manager. + + +// If not using a GATT server, or using a server wihout a service changed characteristic, +// disable this to save code space. + +#ifndef PM_SERVICE_CHANGED_ENABLED +#define PM_SERVICE_CHANGED_ENABLED 1 +#endif + +// PM_PEER_RANKS_ENABLED - Enable/disable the peer rank management in Peer Manager. + + +// Set this to false to save code space if not using the peer rank API. + +#ifndef PM_PEER_RANKS_ENABLED +#define PM_PEER_RANKS_ENABLED 1 +#endif + +// PM_LESC_ENABLED - Enable/disable LESC support in Peer Manager. + + +// If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space. + +#ifndef PM_LESC_ENABLED +#define PM_LESC_ENABLED 0 +#endif + +// PM_RA_PROTECTION_ENABLED - Enable/disable protection against repeated pairing attempts in Peer Manager. +//========================================================== +#ifndef PM_RA_PROTECTION_ENABLED +#define PM_RA_PROTECTION_ENABLED 0 +#endif +// PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked. +#ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM +#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8 +#endif + +// PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated. +#ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL +#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000 +#endif + +// PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated. +#ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL +#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000 +#endif + +// PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms). +// The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period. + +#ifndef PM_RA_PROTECTION_REWARD_PERIOD +#define PM_RA_PROTECTION_REWARD_PERIOD 10000 +#endif + +// + +// PM_HANDLER_SEC_DELAY_MS - Delay before starting security. +// This might be necessary for interoperability reasons, especially as peripheral. + +#ifndef PM_HANDLER_SEC_DELAY_MS +#define PM_HANDLER_SEC_DELAY_MS 0 +#endif + +// + +// +//========================================================== + +// nRF_BLE_Services + +//========================================================== +// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client + + +#ifndef BLE_ANCS_C_ENABLED +#define BLE_ANCS_C_ENABLED 0 +#endif + +// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client + + +#ifndef BLE_ANS_C_ENABLED +#define BLE_ANS_C_ENABLED 0 +#endif + +// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client + + +#ifndef BLE_BAS_C_ENABLED +#define BLE_BAS_C_ENABLED 0 +#endif + +// BLE_BAS_ENABLED - ble_bas - Battery Service +//========================================================== +#ifndef BLE_BAS_ENABLED +#define BLE_BAS_ENABLED 0 +#endif +// BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_BAS_CONFIG_LOG_ENABLED +#define BLE_BAS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_BAS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_BAS_CONFIG_LOG_LEVEL +#define BLE_BAS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_BAS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_BAS_CONFIG_INFO_COLOR +#define BLE_BAS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_BAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_BAS_CONFIG_DEBUG_COLOR +#define BLE_BAS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service + + +#ifndef BLE_CSCS_ENABLED +#define BLE_CSCS_ENABLED 0 +#endif + +// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client + + +#ifndef BLE_CTS_C_ENABLED +#define BLE_CTS_C_ENABLED 0 +#endif + +// BLE_DIS_ENABLED - ble_dis - Device Information Service + + +#ifndef BLE_DIS_ENABLED +#define BLE_DIS_ENABLED 0 +#endif + +// BLE_GLS_ENABLED - ble_gls - Glucose Service + + +#ifndef BLE_GLS_ENABLED +#define BLE_GLS_ENABLED 0 +#endif + +// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service + + +#ifndef BLE_HIDS_ENABLED +#define BLE_HIDS_ENABLED 0 +#endif + +// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client + + +#ifndef BLE_HRS_C_ENABLED +#define BLE_HRS_C_ENABLED 0 +#endif + +// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service + + +#ifndef BLE_HRS_ENABLED +#define BLE_HRS_ENABLED 0 +#endif + +// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service + + +#ifndef BLE_HTS_ENABLED +#define BLE_HTS_ENABLED 0 +#endif + +// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client + + +#ifndef BLE_IAS_C_ENABLED +#define BLE_IAS_C_ENABLED 0 +#endif + +// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service +//========================================================== +#ifndef BLE_IAS_ENABLED +#define BLE_IAS_ENABLED 0 +#endif +// BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_IAS_CONFIG_LOG_ENABLED +#define BLE_IAS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_IAS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_IAS_CONFIG_LOG_LEVEL +#define BLE_IAS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_IAS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_IAS_CONFIG_INFO_COLOR +#define BLE_IAS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_IAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_IAS_CONFIG_DEBUG_COLOR +#define BLE_IAS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client + + +#ifndef BLE_LBS_C_ENABLED +#define BLE_LBS_C_ENABLED 0 +#endif + +// BLE_LBS_ENABLED - ble_lbs - LED Button Service + + +#ifndef BLE_LBS_ENABLED +#define BLE_LBS_ENABLED 0 +#endif + +// BLE_LLS_ENABLED - ble_lls - Link Loss Service + + +#ifndef BLE_LLS_ENABLED +#define BLE_LLS_ENABLED 0 +#endif + +// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service + + +#ifndef BLE_NUS_C_ENABLED +#define BLE_NUS_C_ENABLED 0 +#endif + +// BLE_NUS_ENABLED - ble_nus - Nordic UART Service +//========================================================== +#ifndef BLE_NUS_ENABLED +#define BLE_NUS_ENABLED 0 +#endif +// BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_NUS_CONFIG_LOG_ENABLED +#define BLE_NUS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_NUS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_NUS_CONFIG_LOG_LEVEL +#define BLE_NUS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_NUS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_NUS_CONFIG_INFO_COLOR +#define BLE_NUS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_NUS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_NUS_CONFIG_DEBUG_COLOR +#define BLE_NUS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client + + +#ifndef BLE_RSCS_C_ENABLED +#define BLE_RSCS_C_ENABLED 0 +#endif + +// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service + + +#ifndef BLE_RSCS_ENABLED +#define BLE_RSCS_ENABLED 0 +#endif + +// BLE_TPS_ENABLED - ble_tps - TX Power Service + + +#ifndef BLE_TPS_ENABLED +#define BLE_TPS_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Core + +//========================================================== +// NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU +//========================================================== +#ifndef NRF_MPU_LIB_ENABLED +#define NRF_MPU_LIB_ENABLED 0 +#endif +// NRF_MPU_LIB_CLI_CMDS - Enable CLI commands specific to the module. + + +#ifndef NRF_MPU_LIB_CLI_CMDS +#define NRF_MPU_LIB_CLI_CMDS 0 +#endif + +// + +// NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard +//========================================================== +#ifndef NRF_STACK_GUARD_ENABLED +#define NRF_STACK_GUARD_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_SIZE - Size of the stack guard. + +// <5=> 32 bytes +// <6=> 64 bytes +// <7=> 128 bytes +// <8=> 256 bytes +// <9=> 512 bytes +// <10=> 1024 bytes +// <11=> 2048 bytes +// <12=> 4096 bytes + +#ifndef NRF_STACK_GUARD_CONFIG_SIZE +#define NRF_STACK_GUARD_CONFIG_SIZE 7 +#endif + +// + +// +//========================================================== + +// nRF_Crypto + +//========================================================== +// NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library. +//========================================================== +#ifndef NRF_CRYPTO_ENABLED +#define NRF_CRYPTO_ENABLED 1 +#endif +// NRF_CRYPTO_ALLOCATOR - Memory allocator + + +// Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK. +// <0=> Default +// <1=> User macros +// <2=> On stack (alloca) +// <3=> C dynamic memory (malloc) +// <4=> SDK Memory Manager (nrf_malloc) + +#ifndef NRF_CRYPTO_ALLOCATOR +#define NRF_CRYPTO_ALLOCATOR 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend. + +// The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED - CC310_BL SHA-256 hash functionality. + + +// CC310_BL backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED - nrf_cc310_bl buffers to RAM before running hash operation + + +// Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian +// Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU! + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310 bl. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend. + +// The CC310 hardware-accelerated cryptography backend (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED - Enable the AES CBC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED - Enable the AES CTR mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED - Enable the AES ECB mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED - Enable the AES CBC_MAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED - Enable the AES CMAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED - Enable the AES CCM mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED - Enable the AES CCM* mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED - Enable the secp160r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED - Enable the secp160r2 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED - Enable the secp192r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED - Enable the secp384r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED - Enable the secp521r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED - Enable the secp160k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED - Enable the secp192k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED - Enable the secp224k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED - Enable the secp256k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED - Enable the Curve25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED - Enable the Ed25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED - CC310 SHA-256 hash functionality. + + +// CC310 backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED - CC310 SHA-512 hash functionality + + +// CC310 backend implementation for SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED - CC310 HMAC using SHA-256 + + +// CC310 backend implementation for HMAC using hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED - CC310 HMAC using SHA-512 + + +// CC310 backend implementation for HMAC using SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED - Enable RNG support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED - Enable the AES EAX mode using Cifra. + + +#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED - Enable the AES CBC mode mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED - Enable the AES CTR mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED - Enable the AES CFB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED - Enable the AES ECB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED - Enable the AES CBC MAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED - Enable the AES CMAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED - Enable the AES CCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED - Enable the AES GCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED - Enable secp384r1 (NIST 384-bit) curve + + +// Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED - Enable secp521r1 (NIST 521-bit) curve + + +// Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED - Enable secp192k1 (Koblitz 192-bit) curve + + +// Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED - Enable secp224k1 (Koblitz 224-bit) curve + + +// Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED - Enable bp256r1 (Brainpool 256-bit) curve + + +// Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED - Enable bp384r1 (Brainpool 384-bit) curve + + +// Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED - Enable bp512r1 (Brainpool 512-bit) curve + + +// Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED - Enable Curve25519 curve + + +// Enable this setting if you need Curve25519 support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED - Enable mbed TLS SHA-256 hash functionality. + + +// mbed TLS backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED - Enable mbed TLS SHA-512 hash functionality. + + +// mbed TLS backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED - Enable mbed TLS HMAC using SHA-256. + + +// mbed TLS backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED - Enable mbed TLS HMAC using SHA-512. + + +// mbed TLS backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend. + +// The nRF HW backend provide access to RNG peripheral in nRF5x devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED - Enable mbed TLS CTR-DRBG algorithm. + + +// Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding. + +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto. + +// The nRF SW cryptography backend (only used in bootloader context). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED - nRF SW hash backend support for SHA-256 + + +// The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend + +// The Oberon backend +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using Oberon. + + +#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED - Enable secp256r1 curve + + +// Enable this setting if you need secp256r1 curve support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED - Enable Curve25519 ECDH + + +// Enable this setting if you need Curve25519 ECDH support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED - Enable Ed25519 signature scheme + + +// Enable this setting if you need Ed25519 support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED - Oberon SHA-256 hash functionality + + +// Oberon backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED - Oberon SHA-512 hash functionality + + +// Oberon backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED - Oberon HMAC using SHA-256 + + +// Oberon backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED - Oberon HMAC using SHA-512 + + +// Oberon backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend. + +// Enables the nrf_crypto backend for Optiga Trust X devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED - Optiga backend support for RNG + + +// The Optiga backend provide external chip RNG. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED - Optiga backend support for ECC secp256r1 + + +// The Optiga backend provide external chip ECC using secp256r1. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED - Big-endian byte order in raw Curve25519 data + + +// Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0. + +#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED +#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0 +#endif + +// + +// +//========================================================== + +// nRF_DFU + +//========================================================== +// ble_dfu - Device Firmware Update + +//========================================================== +// BLE_DFU_ENABLED - Enable DFU Service. + + +#ifndef BLE_DFU_ENABLED +#define BLE_DFU_ENABLED 0 +#endif + +// NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS - Buttonless DFU supports bonds. + + +#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS +#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Drivers + +//========================================================== +// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer +//========================================================== +#ifndef COMP_ENABLED +#define COMP_ENABLED 0 +#endif +// COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef COMP_CONFIG_REF +#define COMP_CONFIG_REF 1 +#endif + +// COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef COMP_CONFIG_MAIN_MODE +#define COMP_CONFIG_MAIN_MODE 0 +#endif + +// COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef COMP_CONFIG_SPEED_MODE +#define COMP_CONFIG_SPEED_MODE 2 +#endif + +// COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef COMP_CONFIG_HYST +#define COMP_CONFIG_HYST 0 +#endif + +// COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef COMP_CONFIG_ISOURCE +#define COMP_CONFIG_ISOURCE 0 +#endif + +// COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_INPUT +#define COMP_CONFIG_INPUT 0 +#endif + +// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_IRQ_PRIORITY +#define COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer + + +#ifndef EGU_ENABLED +#define EGU_ENABLED 0 +#endif + +// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer +//========================================================== +#ifndef GPIOTE_ENABLED +#define GPIOTE_ENABLED 0 +#endif +// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef GPIOTE_CONFIG_IRQ_PRIORITY +#define GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer +//========================================================== +#ifndef I2S_ENABLED +#define I2S_ENABLED 0 +#endif +// I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef I2S_CONFIG_SCK_PIN +#define I2S_CONFIG_SCK_PIN 31 +#endif + +// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef I2S_CONFIG_LRCK_PIN +#define I2S_CONFIG_LRCK_PIN 30 +#endif + +// I2S_CONFIG_MCK_PIN - MCK pin +#ifndef I2S_CONFIG_MCK_PIN +#define I2S_CONFIG_MCK_PIN 255 +#endif + +// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef I2S_CONFIG_SDOUT_PIN +#define I2S_CONFIG_SDOUT_PIN 29 +#endif + +// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef I2S_CONFIG_SDIN_PIN +#define I2S_CONFIG_SDIN_PIN 28 +#endif + +// I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef I2S_CONFIG_MASTER +#define I2S_CONFIG_MASTER 0 +#endif + +// I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef I2S_CONFIG_FORMAT +#define I2S_CONFIG_FORMAT 0 +#endif + +// I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef I2S_CONFIG_ALIGN +#define I2S_CONFIG_ALIGN 0 +#endif + +// I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef I2S_CONFIG_SWIDTH +#define I2S_CONFIG_SWIDTH 1 +#endif + +// I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef I2S_CONFIG_CHANNELS +#define I2S_CONFIG_CHANNELS 1 +#endif + +// I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef I2S_CONFIG_MCK_SETUP +#define I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef I2S_CONFIG_RATIO +#define I2S_CONFIG_RATIO 2000 +#endif + +// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef I2S_CONFIG_IRQ_PRIORITY +#define I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef I2S_CONFIG_LOG_ENABLED +#define I2S_CONFIG_LOG_ENABLED 0 +#endif +// I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef I2S_CONFIG_LOG_LEVEL +#define I2S_CONFIG_LOG_LEVEL 3 +#endif + +// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_INFO_COLOR +#define I2S_CONFIG_INFO_COLOR 0 +#endif + +// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_DEBUG_COLOR +#define I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer +//========================================================== +#ifndef LPCOMP_ENABLED +#define LPCOMP_ENABLED 0 +#endif +// LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef LPCOMP_CONFIG_REFERENCE +#define LPCOMP_CONFIG_REFERENCE 3 +#endif + +// LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef LPCOMP_CONFIG_DETECTION +#define LPCOMP_CONFIG_DETECTION 2 +#endif + +// LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_INPUT +#define LPCOMP_CONFIG_INPUT 0 +#endif + +// LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef LPCOMP_CONFIG_HYST +#define LPCOMP_CONFIG_HYST 0 +#endif + +// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_IRQ_PRIORITY +#define LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver +//========================================================== +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF 1 +#endif + +// NRFX_COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE 0 +#endif + +// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE 2 +#endif + +// NRFX_COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST 0 +#endif + +// NRFX_COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE 0 +#endif + +// NRFX_COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT 0 +#endif + +// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 1 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver +//========================================================== +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SCK_PIN +#define NRFX_I2S_CONFIG_SCK_PIN 31 +#endif + +// NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef NRFX_I2S_CONFIG_LRCK_PIN +#define NRFX_I2S_CONFIG_LRCK_PIN 30 +#endif + +// NRFX_I2S_CONFIG_MCK_PIN - MCK pin +#ifndef NRFX_I2S_CONFIG_MCK_PIN +#define NRFX_I2S_CONFIG_MCK_PIN 255 +#endif + +// NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SDOUT_PIN +#define NRFX_I2S_CONFIG_SDOUT_PIN 29 +#endif + +// NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SDIN_PIN +#define NRFX_I2S_CONFIG_SDIN_PIN 28 +#endif + +// NRFX_I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef NRFX_I2S_CONFIG_MASTER +#define NRFX_I2S_CONFIG_MASTER 0 +#endif + +// NRFX_I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef NRFX_I2S_CONFIG_FORMAT +#define NRFX_I2S_CONFIG_FORMAT 0 +#endif + +// NRFX_I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef NRFX_I2S_CONFIG_ALIGN +#define NRFX_I2S_CONFIG_ALIGN 0 +#endif + +// NRFX_I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef NRFX_I2S_CONFIG_SWIDTH +#define NRFX_I2S_CONFIG_SWIDTH 1 +#endif + +// NRFX_I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef NRFX_I2S_CONFIG_CHANNELS +#define NRFX_I2S_CONFIG_CHANNELS 1 +#endif + +// NRFX_I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef NRFX_I2S_CONFIG_MCK_SETUP +#define NRFX_I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// NRFX_I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef NRFX_I2S_CONFIG_RATIO +#define NRFX_I2S_CONFIG_RATIO 2000 +#endif + +// NRFX_I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_INFO_COLOR +#define NRFX_I2S_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR +#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver +//========================================================== +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif +// NRFX_LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef NRFX_LPCOMP_CONFIG_REFERENCE +#define NRFX_LPCOMP_CONFIG_REFERENCE 3 +#endif + +// NRFX_LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef NRFX_LPCOMP_CONFIG_DETECTION +#define NRFX_LPCOMP_CONFIG_DETECTION 2 +#endif + +// NRFX_LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_LPCOMP_CONFIG_INPUT +#define NRFX_LPCOMP_CONFIG_INPUT 0 +#endif + +// NRFX_LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef NRFX_LPCOMP_CONFIG_HYST +#define NRFX_LPCOMP_CONFIG_HYST 0 +#endif + +// NRFX_LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR +#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR +#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver +//========================================================== +#ifndef NRFX_NFCT_ENABLED +#define NRFX_NFCT_ENABLED 0 +#endif +// NRFX_NFCT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY +#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED +#define NRFX_NFCT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL +#define NRFX_NFCT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_NFCT_CONFIG_INFO_COLOR +#define NRFX_NFCT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR +#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver +//========================================================== +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef NRFX_PDM_CONFIG_MODE +#define NRFX_PDM_CONFIG_MODE 1 +#endif + +// NRFX_PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef NRFX_PDM_CONFIG_EDGE +#define NRFX_PDM_CONFIG_EDGE 0 +#endif + +// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ +#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 0 +#endif +// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver +//========================================================== +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif +// NRFX_PWM0_ENABLED - Enable PWM0 instance + + +#ifndef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED 0 +#endif + +// NRFX_PWM1_ENABLED - Enable PWM1 instance + + +#ifndef NRFX_PWM1_ENABLED +#define NRFX_PWM1_ENABLED 0 +#endif + +// NRFX_PWM2_ENABLED - Enable PWM2 instance + + +#ifndef NRFX_PWM2_ENABLED +#define NRFX_PWM2_ENABLED 0 +#endif + +// NRFX_PWM3_ENABLED - Enable PWM3 instance + + +#ifndef NRFX_PWM3_ENABLED +#define NRFX_PWM3_ENABLED 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK +#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE +#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE +#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE +#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE +#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER 7 +#endif + +// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED 31 +#endif + +// NRFX_QDEC_CONFIG_LEDPRE - LED pre +#ifndef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE 511 +#endif + +// NRFX_QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL 1 +#endif + +// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver +//========================================================== +#ifndef NRFX_QSPI_ENABLED +#define NRFX_QSPI_ENABLED 1 +#endif +// NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef NRFX_QSPI_CONFIG_SCK_DELAY +#define NRFX_QSPI_CONFIG_SCK_DELAY 1 +#endif + +// NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. +#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET +#define NRFX_QSPI_CONFIG_XIP_OFFSET 0 +#endif + +// NRFX_QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef NRFX_QSPI_CONFIG_READOC +#define NRFX_QSPI_CONFIG_READOC 0 +#endif + +// NRFX_QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef NRFX_QSPI_CONFIG_WRITEOC +#define NRFX_QSPI_CONFIG_WRITEOC 0 +#endif + +// NRFX_QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef NRFX_QSPI_CONFIG_ADDRMODE +#define NRFX_QSPI_CONFIG_ADDRMODE 0 +#endif + +// NRFX_QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef NRFX_QSPI_CONFIG_MODE +#define NRFX_QSPI_CONFIG_MODE 0 +#endif + +// NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef NRFX_QSPI_CONFIG_FREQUENCY +#define NRFX_QSPI_CONFIG_FREQUENCY 15 +#endif + +// NRFX_QSPI_PIN_SCK - SCK pin value. +#ifndef NRFX_QSPI_PIN_SCK +#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_CSN - CSN pin value. +#ifndef NRFX_QSPI_PIN_CSN +#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO0 - IO0 pin value. +#ifndef NRFX_QSPI_PIN_IO0 +#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO1 - IO1 pin value. +#ifndef NRFX_QSPI_PIN_IO1 +#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO2 - IO2 pin value. +#ifndef NRFX_QSPI_PIN_IO2 +#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO3 - IO3 pin value. +#ifndef NRFX_QSPI_PIN_IO3 +#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 0 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 0 +#endif + +// NRFX_RTC2_ENABLED - Enable RTC2 instance + + +#ifndef NRFX_RTC2_ENABLED +#define NRFX_RTC2_ENABLED 0 +#endif + +// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef NRFX_SAADC_CONFIG_RESOLUTION +#define NRFX_SAADC_CONFIG_RESOLUTION 1 +#endif + +// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE +#define NRFX_SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef NRFX_SAADC_CONFIG_LP_MODE +#define NRFX_SAADC_CONFIG_LP_MODE 0 +#endif + +// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 0 +#endif + +// NRFX_SPIM1_ENABLED - Enable SPIM1 instance + + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 0 +#endif + +// NRFX_SPIM2_ENABLED - Enable SPIM2 instance + + +#ifndef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED 0 +#endif + +// NRFX_SPIM3_ENABLED - Enable SPIM3 instance + + +#ifndef NRFX_SPIM3_ENABLED +#define NRFX_SPIM3_ENABLED 0 +#endif + +// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features + + +#ifndef NRFX_SPIM_EXTENDED_ENABLED +#define NRFX_SPIM_EXTENDED_ENABLED 0 +#endif + +// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG 1 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 0 +#endif + +// NRFX_SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 0 +#endif + +// NRFX_SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef NRFX_SPIS2_ENABLED +#define NRFX_SPIS2_ENABLED 0 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF 255 +#endif + +// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC 255 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 1 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 1 +#endif + +// NRFX_SPI1_ENABLED - Enable SPI1 instance + + +#ifndef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 1 +#endif + +// NRFX_SPI2_ENABLED - Enable SPI2 instance + + +#ifndef NRFX_SPI2_ENABLED +#define NRFX_SPI2_ENABLED 1 +#endif + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator +//========================================================== +#ifndef NRFX_SWI_ENABLED +#define NRFX_SWI_ENABLED 0 +#endif +// NRFX_EGU_ENABLED - Enable EGU support + + +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver + + +#ifndef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 0 +#endif + +// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver + + +#ifndef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 0 +#endif + +// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver + + +#ifndef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 0 +#endif + +// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver + + +#ifndef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 0 +#endif + +// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver + + +#ifndef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 0 +#endif + +// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver + + +#ifndef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 0 +#endif + +// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 0 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 0 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 0 +#endif + +// NRFX_TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef NRFX_TIMER3_ENABLED +#define NRFX_TIMER3_ENABLED 0 +#endif + +// NRFX_TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef NRFX_TIMER4_ENABLED +#define NRFX_TIMER4_ENABLED 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 0 +#endif + +// NRFX_TWIM1_ENABLED - Enable TWIM1 instance + + +#ifndef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 0 +#endif + +// NRFX_TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef NRFX_TWIS1_ENABLED +#define NRFX_TWIS1_ENABLED 0 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 0 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 0 +#endif + +// NRFX_TWI1_ENABLED - Enable TWI1 instance + + +#ifndef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 0 +#endif + +// NRFX_UARTE1_ENABLED - Enable UARTE1 instance +#ifndef NRFX_UARTE1_ENABLED +#define NRFX_UARTE1_ENABLED 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <8388608=> 31250 baud +// <10289152=> 38400 baud +// <15007744=> 56000 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 1 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 1 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver +//========================================================== +#ifndef NRFX_USBD_ENABLED +#define NRFX_USBD_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY +#define NRFX_USBD_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_USBD_CONFIG_DMASCHEDULER_MODE - USBD DMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE +#define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0 +#endif + +// NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// NRFX_USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. + +#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP +#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR 1 +#endif + +// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRF_CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer +//========================================================== +#ifndef NRF_CLOCK_ENABLED +#define NRF_CLOCK_ENABLED 0 +#endif +// CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef CLOCK_CONFIG_LF_SRC +#define CLOCK_CONFIG_LF_SRC 1 +#endif + +// CLOCK_CONFIG_LF_CAL_ENABLED - Calibration enable for LF Clock Source + + +#ifndef CLOCK_CONFIG_LF_CAL_ENABLED +#define CLOCK_CONFIG_LF_CAL_ENABLED 0 +#endif + +// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef CLOCK_CONFIG_IRQ_PRIORITY +#define CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer +//========================================================== +#ifndef PDM_ENABLED +#define PDM_ENABLED 0 +#endif +// PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef PDM_CONFIG_MODE +#define PDM_CONFIG_MODE 1 +#endif + +// PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef PDM_CONFIG_EDGE +#define PDM_CONFIG_EDGE 0 +#endif + +// PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef PDM_CONFIG_CLOCK_FREQ +#define PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PDM_CONFIG_IRQ_PRIORITY +#define PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer +//========================================================== +#ifndef POWER_ENABLED +#define POWER_ENABLED 0 +#endif +// POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef POWER_CONFIG_IRQ_PRIORITY +#define POWER_CONFIG_IRQ_PRIORITY 6 +#endif + +// POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCEN +#define POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCENHV +#define POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver - legacy layer + + +#ifndef PPI_ENABLED +#define PPI_ENABLED 0 +#endif + +// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer +//========================================================== +#ifndef PWM_ENABLED +#define PWM_ENABLED 0 +#endif +// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN +#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN +#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN +#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN +#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK +#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE +#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE +#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE +#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef PWM_DEFAULT_CONFIG_STEP_MODE +#define PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// PWM0_ENABLED - Enable PWM0 instance + + +#ifndef PWM0_ENABLED +#define PWM0_ENABLED 0 +#endif + +// PWM1_ENABLED - Enable PWM1 instance + + +#ifndef PWM1_ENABLED +#define PWM1_ENABLED 0 +#endif + +// PWM2_ENABLED - Enable PWM2 instance + + +#ifndef PWM2_ENABLED +#define PWM2_ENABLED 0 +#endif + +// PWM3_ENABLED - Enable PWM3 instance + + +#ifndef PWM3_ENABLED +#define PWM3_ENABLED 0 +#endif + +// + +// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer +//========================================================== +#ifndef QDEC_ENABLED +#define QDEC_ENABLED 0 +#endif +// QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef QDEC_CONFIG_REPORTPER +#define QDEC_CONFIG_REPORTPER 0 +#endif + +// QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef QDEC_CONFIG_SAMPLEPER +#define QDEC_CONFIG_SAMPLEPER 7 +#endif + +// QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_A +#define QDEC_CONFIG_PIO_A 31 +#endif + +// QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_B +#define QDEC_CONFIG_PIO_B 31 +#endif + +// QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_LED +#define QDEC_CONFIG_PIO_LED 31 +#endif + +// QDEC_CONFIG_LEDPRE - LED pre +#ifndef QDEC_CONFIG_LEDPRE +#define QDEC_CONFIG_LEDPRE 511 +#endif + +// QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef QDEC_CONFIG_LEDPOL +#define QDEC_CONFIG_LEDPOL 1 +#endif + +// QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef QDEC_CONFIG_DBFEN +#define QDEC_CONFIG_DBFEN 0 +#endif + +// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef QDEC_CONFIG_SAMPLE_INTEN +#define QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QDEC_CONFIG_IRQ_PRIORITY +#define QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer +//========================================================== +#ifndef QSPI_ENABLED +#define QSPI_ENABLED 0 +#endif +// QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef QSPI_CONFIG_SCK_DELAY +#define QSPI_CONFIG_SCK_DELAY 1 +#endif + +// QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. +#ifndef QSPI_CONFIG_XIP_OFFSET +#define QSPI_CONFIG_XIP_OFFSET 0 +#endif + +// QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef QSPI_CONFIG_READOC +#define QSPI_CONFIG_READOC 0 +#endif + +// QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef QSPI_CONFIG_WRITEOC +#define QSPI_CONFIG_WRITEOC 0 +#endif + +// QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef QSPI_CONFIG_ADDRMODE +#define QSPI_CONFIG_ADDRMODE 0 +#endif + +// QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef QSPI_CONFIG_MODE +#define QSPI_CONFIG_MODE 0 +#endif + +// QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef QSPI_CONFIG_FREQUENCY +#define QSPI_CONFIG_FREQUENCY 15 +#endif + +// QSPI_PIN_SCK - SCK pin value. +#ifndef QSPI_PIN_SCK +#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_CSN - CSN pin value. +#ifndef QSPI_PIN_CSN +#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO0 - IO0 pin value. +#ifndef QSPI_PIN_IO0 +#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO1 - IO1 pin value. +#ifndef QSPI_PIN_IO1 +#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO2 - IO2 pin value. +#ifndef QSPI_PIN_IO2 +#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO3 - IO3 pin value. +#ifndef QSPI_PIN_IO3 +#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QSPI_CONFIG_IRQ_PRIORITY +#define QSPI_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer +//========================================================== +#ifndef RNG_ENABLED +#define RNG_ENABLED 0 +#endif +// RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef RNG_CONFIG_ERROR_CORRECTION +#define RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// RNG_CONFIG_POOL_SIZE - Pool size +#ifndef RNG_CONFIG_POOL_SIZE +#define RNG_CONFIG_POOL_SIZE 64 +#endif + +// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RNG_CONFIG_IRQ_PRIORITY +#define RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer +//========================================================== +#ifndef RTC_ENABLED +#define RTC_ENABLED 0 +#endif +// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef RTC_DEFAULT_CONFIG_FREQUENCY +#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef RTC_DEFAULT_CONFIG_RELIABLE +#define RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// RTC0_ENABLED - Enable RTC0 instance + + +#ifndef RTC0_ENABLED +#define RTC0_ENABLED 0 +#endif + +// RTC1_ENABLED - Enable RTC1 instance + + +#ifndef RTC1_ENABLED +#define RTC1_ENABLED 0 +#endif + +// RTC2_ENABLED - Enable RTC2 instance + + +#ifndef RTC2_ENABLED +#define RTC2_ENABLED 0 +#endif + +// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRF_MAXIMUM_LATENCY_US +#define NRF_MAXIMUM_LATENCY_US 2000 +#endif + +// + +// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer +//========================================================== +#ifndef SAADC_ENABLED +#define SAADC_ENABLED 0 +#endif +// SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef SAADC_CONFIG_RESOLUTION +#define SAADC_CONFIG_RESOLUTION 1 +#endif + +// SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef SAADC_CONFIG_OVERSAMPLE +#define SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef SAADC_CONFIG_LP_MODE +#define SAADC_CONFIG_LP_MODE 0 +#endif + +// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SAADC_CONFIG_IRQ_PRIORITY +#define SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer +//========================================================== +#ifndef SPIS_ENABLED +#define SPIS_ENABLED 0 +#endif +// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// SPIS_DEFAULT_MODE - Mode + +// <0=> MODE_0 +// <1=> MODE_1 +// <2=> MODE_2 +// <3=> MODE_3 + +#ifndef SPIS_DEFAULT_MODE +#define SPIS_DEFAULT_MODE 0 +#endif + +// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order + +// <0=> MSB first +// <1=> LSB first + +#ifndef SPIS_DEFAULT_BIT_ORDER +#define SPIS_DEFAULT_BIT_ORDER 0 +#endif + +// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef SPIS_DEFAULT_DEF +#define SPIS_DEFAULT_DEF 255 +#endif + +// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_ORC 255 +#endif + +// SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef SPIS0_ENABLED +#define SPIS0_ENABLED 0 +#endif + +// SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef SPIS1_ENABLED +#define SPIS1_ENABLED 0 +#endif + +// SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef SPIS2_ENABLED +#define SPIS2_ENABLED 0 +#endif + +// + +// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer +//========================================================== +#ifndef SPI_ENABLED +#define SPI_ENABLED 0 +#endif +// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRF_SPI_DRV_MISO_PULLUP_CFG - MISO PIN pull-up configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG +#define NRF_SPI_DRV_MISO_PULLUP_CFG 1 +#endif + +// SPI0_ENABLED - Enable SPI0 instance +//========================================================== +#ifndef SPI0_ENABLED +#define SPI0_ENABLED 0 +#endif +// SPI0_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI0_USE_EASY_DMA +#define SPI0_USE_EASY_DMA 1 +#endif + +// + +// SPI1_ENABLED - Enable SPI1 instance +//========================================================== +#ifndef SPI1_ENABLED +#define SPI1_ENABLED 0 +#endif +// SPI1_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI1_USE_EASY_DMA +#define SPI1_USE_EASY_DMA 1 +#endif + +// + +// SPI2_ENABLED - Enable SPI2 instance +//========================================================== +#ifndef SPI2_ENABLED +#define SPI2_ENABLED 0 +#endif +// SPI2_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI2_USE_EASY_DMA +#define SPI2_USE_EASY_DMA 1 +#endif + +// + +// + +// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer +//========================================================== +#ifndef TIMER_ENABLED +#define TIMER_ENABLED 0 +#endif +// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY +#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef TIMER_DEFAULT_CONFIG_MODE +#define TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef TIMER0_ENABLED +#define TIMER0_ENABLED 0 +#endif + +// TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef TIMER1_ENABLED +#define TIMER1_ENABLED 0 +#endif + +// TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef TIMER2_ENABLED +#define TIMER2_ENABLED 0 +#endif + +// TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef TIMER3_ENABLED +#define TIMER3_ENABLED 0 +#endif + +// TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef TIMER4_ENABLED +#define TIMER4_ENABLED 0 +#endif + +// + +// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer +//========================================================== +#ifndef TWIS_ENABLED +#define TWIS_ENABLED 0 +#endif +// TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef TWIS0_ENABLED +#define TWIS0_ENABLED 0 +#endif + +// TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef TWIS1_ENABLED +#define TWIS1_ENABLED 0 +#endif + +// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef TWIS_NO_SYNC_MODE +#define TWIS_NO_SYNC_MODE 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef TWIS_DEFAULT_CONFIG_ADDR0 +#define TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef TWIS_DEFAULT_CONFIG_ADDR1 +#define TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL +#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL +#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer +//========================================================== +#ifndef TWI_ENABLED +#define TWI_ENABLED 0 +#endif +// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef TWI_DEFAULT_CONFIG_FREQUENCY +#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init + + +#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT +#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 +#endif + +// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TWI0_ENABLED - Enable TWI0 instance +//========================================================== +#ifndef TWI0_ENABLED +#define TWI0_ENABLED 0 +#endif +// TWI0_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI0_USE_EASY_DMA +#define TWI0_USE_EASY_DMA 0 +#endif + +// + +// TWI1_ENABLED - Enable TWI1 instance +//========================================================== +#ifndef TWI1_ENABLED +#define TWI1_ENABLED 0 +#endif +// TWI1_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI1_USE_EASY_DMA +#define TWI1_USE_EASY_DMA 0 +#endif + +// + +// + +// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer +//========================================================== +#ifndef UART_ENABLED +#define UART_ENABLED 0 +#endif +// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef UART_DEFAULT_CONFIG_HWFC +#define UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef UART_DEFAULT_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef UART_DEFAULT_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA + + +#ifndef UART_EASY_DMA_SUPPORT +#define UART_EASY_DMA_SUPPORT 1 +#endif + +// UART_LEGACY_SUPPORT - Driver supporting Legacy mode + + +#ifndef UART_LEGACY_SUPPORT +#define UART_LEGACY_SUPPORT 1 +#endif + +// UART0_ENABLED - Enable UART0 instance +//========================================================== +#ifndef UART0_ENABLED +#define UART0_ENABLED 0 +#endif +// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA + + +#ifndef UART0_CONFIG_USE_EASY_DMA +#define UART0_CONFIG_USE_EASY_DMA 1 +#endif + +// + +// UART1_ENABLED - Enable UART1 instance +//========================================================== +#ifndef UART1_ENABLED +#define UART1_ENABLED 0 +#endif +// + +// + +// USBD_ENABLED - nrf_drv_usbd - Software Component +//========================================================== +#ifndef USBD_ENABLED +#define USBD_ENABLED 0 +#endif +// USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef USBD_CONFIG_IRQ_PRIORITY +#define USBD_CONFIG_IRQ_PRIORITY 6 +#endif + +// USBD_CONFIG_DMASCHEDULER_MODE - USBD SMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef USBD_CONFIG_DMASCHEDULER_MODE +#define USBD_CONFIG_DMASCHEDULER_MODE 0 +#endif + +// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. +// NOTE: This option does not work on Engineering A chip. + +#ifndef USBD_CONFIG_ISO_IN_ZLP +#define USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// + +// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer +//========================================================== +#ifndef WDT_ENABLED +#define WDT_ENABLED 0 +#endif +// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef WDT_CONFIG_BEHAVIOUR +#define WDT_CONFIG_BEHAVIOUR 1 +#endif + +// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef WDT_CONFIG_RELOAD_VALUE +#define WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef WDT_CONFIG_IRQ_PRIORITY +#define WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// +//========================================================== + +// nRF_Drivers_External + +//========================================================== +// NRF_TWI_SENSOR_ENABLED - nrf_twi_sensor - nRF TWI Sensor module + + +#ifndef NRF_TWI_SENSOR_ENABLED +#define NRF_TWI_SENSOR_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Libraries + +//========================================================== +// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher + + +#ifndef APP_GPIOTE_ENABLED +#define APP_GPIOTE_ENABLED 0 +#endif + +// APP_PWM_ENABLED - app_pwm - PWM functionality + + +#ifndef APP_PWM_ENABLED +#define APP_PWM_ENABLED 0 +#endif + +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 0 +#endif +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +// + +// APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI +//========================================================== +#ifndef APP_SDCARD_ENABLED +#define APP_SDCARD_ENABLED 0 +#endif +// APP_SDCARD_SPI_INSTANCE - SPI instance used + +// <0=> 0 +// <1=> 1 +// <2=> 2 + +#ifndef APP_SDCARD_SPI_INSTANCE +#define APP_SDCARD_SPI_INSTANCE 0 +#endif + +// APP_SDCARD_FREQ_INIT - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_INIT +#define APP_SDCARD_FREQ_INIT 67108864 +#endif + +// APP_SDCARD_FREQ_DATA - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_DATA +#define APP_SDCARD_FREQ_DATA 1073741824 +#endif + +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 0 +#endif +// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. + +// <0=> 32768 Hz +// <1=> 16384 Hz +// <3=> 8192 Hz +// <7=> 4096 Hz +// <15=> 2048 Hz +// <31=> 1024 Hz + +#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY +#define APP_TIMER_CONFIG_RTC_FREQUENCY 1 +#endif + +// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY +#define APP_TIMER_CONFIG_IRQ_PRIORITY 6 +#endif + +// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. +// Size of the queue depends on how many timers are used +// in the system, how often timers are started and overall +// system latency. If queue size is too small app_timer calls +// will fail. + +#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE +#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 +#endif + +// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler + + +#ifndef APP_TIMER_CONFIG_USE_SCHEDULER +#define APP_TIMER_CONFIG_USE_SCHEDULER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +// APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. +// Maximum possible timeout that can be set is reduced by safe window. +// Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS. +// Since RTC is not stopped when processor is halted in debugging session, this value +// must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS +// without corrupting app_timer behavior. + +#ifndef APP_TIMER_SAFE_WINDOW_MS +#define APP_TIMER_SAFE_WINDOW_MS 300000 +#endif + +// App Timer Legacy configuration - Legacy configuration. + +//========================================================== +// APP_TIMER_WITH_PROFILER - Enable app_timer profiling + + +#ifndef APP_TIMER_WITH_PROFILER +#define APP_TIMER_WITH_PROFILER 0 +#endif + +// APP_TIMER_CONFIG_SWI_NUMBER - Configure SWI instance used. + + +#ifndef APP_TIMER_CONFIG_SWI_NUMBER +#define APP_TIMER_CONFIG_SWI_NUMBER 0 +#endif + +// +//========================================================== + +// + +// APP_USBD_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class + + +#ifndef APP_USBD_AUDIO_ENABLED +#define APP_USBD_AUDIO_ENABLED 0 +#endif + +// APP_USBD_ENABLED - app_usbd - USB Device library +//========================================================== +#ifndef APP_USBD_ENABLED +#define APP_USBD_ENABLED 0 +#endif +// APP_USBD_VID - Vendor ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ + +#ifndef APP_USBD_VID +#define APP_USBD_VID 0 +#endif + +// APP_USBD_PID - Product ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Selected Product ID + +#ifndef APP_USBD_PID +#define APP_USBD_PID 0 +#endif + +// APP_USBD_DEVICE_VER_MAJOR - Major device version <0-99> + + +// Major device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MAJOR +#define APP_USBD_DEVICE_VER_MAJOR 1 +#endif + +// APP_USBD_DEVICE_VER_MINOR - Minor device version <0-9> + + +// Minor device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MINOR +#define APP_USBD_DEVICE_VER_MINOR 0 +#endif + +// APP_USBD_DEVICE_VER_SUB - Sub-minor device version <0-9> + + +// Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_SUB +#define APP_USBD_DEVICE_VER_SUB 0 +#endif + +// APP_USBD_CONFIG_SELF_POWERED - Self-powered device, as opposed to bus-powered. + + +#ifndef APP_USBD_CONFIG_SELF_POWERED +#define APP_USBD_CONFIG_SELF_POWERED 1 +#endif + +// APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps. <0-500> + + +#ifndef APP_USBD_CONFIG_MAX_POWER +#define APP_USBD_CONFIG_MAX_POWER 100 +#endif + +// APP_USBD_CONFIG_POWER_EVENTS_PROCESS - Process power events. + + +// Enable processing power events in USB event handler. + +#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS +#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1 +#endif + +// APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue. + +// This is the default configuration when all the events are placed into internal queue. +// Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts. +// Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context. +// Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable. +//========================================================== +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE +#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1 +#endif +// APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue. <16-64> + + +// The size of the queue for the events that would be processed in the main loop. + +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE +#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32 +#endif + +// APP_USBD_CONFIG_SOF_HANDLING_MODE - Change SOF events handling mode. + + +// Normal queue - SOF events are pushed normally into the event queue. +// Compress queue - SOF events are counted and binded with other events or executed when the queue is empty. +// This prevents the queue from filling up with SOF events. +// Interrupt - SOF events are processed in interrupt. +// <0=> Normal queue +// <1=> Compress queue +// <2=> Interrupt + +#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE +#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1 +#endif + +// + +// APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE - Provide a function that generates timestamps for logs based on the current SOF. + + +// The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. +// Use it when initializing the logger. +// SOF processing is always enabled when this configuration parameter is active. +// Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. +// This means that it works even if the logging in this very module is disabled. + +#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE +#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0 +#endif + +// APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor. <31-254> + + +// 31 characters can be stored in the internal USB buffer used for transfers. +// Any value higher than 31 creates an additional buffer just for descriptor strings. + +#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE +#define APP_USBD_CONFIG_DESC_STRING_SIZE 31 +#endif + +// APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED - Enable UTF8 conversion. + + +// Enable UTF8-encoded characters. In normal processing, only ASCII characters are available. + +#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED +#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0 +#endif + +// APP_USBD_STRINGS_LANGIDS - Supported languages identifiers. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of supported languages. +#ifndef APP_USBD_STRINGS_LANGIDS +#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US) +#endif + +// APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_MANUFACTURER +#define APP_USBD_STRING_ID_MANUFACTURER 1 +#endif +// APP_USBD_STRINGS_MANUFACTURER_EXTERN - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN +#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0 +#endif + +// APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of manufacturer names for each defined language. +// Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string. +// Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values. +// Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values. +// Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor. +// Setting string to NULL disables that string. +// The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS. +#ifndef APP_USBD_STRINGS_MANUFACTURER +#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor") +#endif + +// + +// APP_USBD_STRING_ID_PRODUCT - Define product string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_PRODUCT +#define APP_USBD_STRING_ID_PRODUCT 2 +#endif +// APP_USBD_STRINGS_PRODUCT_EXTERN - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN +#define APP_USBD_STRINGS_PRODUCT_EXTERN 0 +#endif + +// APP_USBD_STRINGS_PRODUCT - String descriptor for the product name. + +// Note: This value is not editable in Configuration Wizard. +// List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_PRODUCT +#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product") +#endif + +// + +// APP_USBD_STRING_ID_SERIAL - Define serial number string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_SERIAL +#define APP_USBD_STRING_ID_SERIAL 3 +#endif +// APP_USBD_STRING_SERIAL_EXTERN - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRING_SERIAL_EXTERN +#define APP_USBD_STRING_SERIAL_EXTERN 0 +#endif + +// APP_USBD_STRING_SERIAL - String descriptor for the serial number. + +// Note: This value is not editable in Configuration Wizard. +// Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRING_SERIAL +#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000") +#endif + +// + +// APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_CONFIGURATION +#define APP_USBD_STRING_ID_CONFIGURATION 4 +#endif +// APP_USBD_STRING_CONFIGURATION_EXTERN - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable. + + +#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN +#define APP_USBD_STRING_CONFIGURATION_EXTERN 0 +#endif + +// APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration. + +// Note: This value is not editable in Configuration Wizard. +// Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_CONFIGURATION +#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration") +#endif + +// + +// APP_USBD_STRINGS_USER - Default values for user strings. + +// Note: This value is not editable in Configuration Wizard. +// This value stores all application specific user strings with the default initialization. +// The setup is done by X-macros. +// Expected macro parameters: +// @code +// X(mnemonic, [=str_idx], ...) +// @endcode +// - @c mnemonic: Mnemonic of the string descriptor that would be added to +// @ref app_usbd_string_desc_idx_t enumerator. +// - @c str_idx : String index value, can be set or left empty. +// For example, WinUSB driver requires descriptor to be present on 0xEE index. +// Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...))) +// - @c ... : List of string descriptors for each defined language. +#ifndef APP_USBD_STRINGS_USER +#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1")) +#endif + +// + +// APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class +//========================================================== +#ifndef APP_USBD_HID_ENABLED +#define APP_USBD_HID_ENABLED 0 +#endif +// APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class. <0-255> + + +// 0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification. + +#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE +#define APP_USBD_HID_DEFAULT_IDLE_RATE 0 +#endif + +// APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table. <1-255> + + +// Must be higher than the highest report ID used. + +#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE +#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4 +#endif + +// + +// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic + + +#ifndef APP_USBD_HID_GENERIC_ENABLED +#define APP_USBD_HID_GENERIC_ENABLED 0 +#endif + +// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard + + +#ifndef APP_USBD_HID_KBD_ENABLED +#define APP_USBD_HID_KBD_ENABLED 0 +#endif + +// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse + + +#ifndef APP_USBD_HID_MOUSE_ENABLED +#define APP_USBD_HID_MOUSE_ENABLED 0 +#endif + +// APP_USBD_MSC_ENABLED - app_usbd_msc - USB MSC class + + +#ifndef APP_USBD_MSC_ENABLED +#define APP_USBD_MSC_ENABLED 0 +#endif + +// CRC16_ENABLED - crc16 - CRC16 calculation routines + + +#ifndef CRC16_ENABLED +#define CRC16_ENABLED 0 +#endif + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 0 +#endif + +// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library + + +#ifndef ECC_ENABLED +#define ECC_ENABLED 0 +#endif + +// FDS_ENABLED - fds - Flash data storage module +//========================================================== +#ifndef FDS_ENABLED +#define FDS_ENABLED 0 +#endif +// Pages - Virtual page settings + +// Configure the number of virtual pages to use and their size. +//========================================================== +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// One of the virtual pages is reserved by the system for garbage collection. +// Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection. +// The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. + +#ifndef FDS_VIRTUAL_PAGES +#define FDS_VIRTUAL_PAGES 3 +#endif + +// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual flash page. + + +// Expressed in number of 4-byte words. +// By default, a virtual page is the same size as a physical page. +// The size of a virtual page must be a multiple of the size of a physical page. +// <1024=> 1024 +// <2048=> 2048 + +#ifndef FDS_VIRTUAL_PAGE_SIZE +#define FDS_VIRTUAL_PAGE_SIZE 1024 +#endif + +// FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. +// FDS module stores its data in the last pages of the flash memory. +// By setting this value, you can move flash end address used by the FDS. +// As a result the reserved space can be used by other modules. + +#ifndef FDS_VIRTUAL_PAGES_RESERVED +#define FDS_VIRTUAL_PAGES_RESERVED 0 +#endif + +// +//========================================================== + +// Backend - Backend configuration + +// Configure which nrf_fstorage backend is used by FDS to write to flash. +//========================================================== +// FDS_BACKEND - FDS flash backend. + + +// NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present. +// NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice. +// <1=> NRF_FSTORAGE_NVMC +// <2=> NRF_FSTORAGE_SD + +#ifndef FDS_BACKEND +#define FDS_BACKEND 2 +#endif + +// +//========================================================== + +// Queue - Queue settings + +//========================================================== +// FDS_OP_QUEUE_SIZE - Size of the internal queue. +// Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors. + +#ifndef FDS_OP_QUEUE_SIZE +#define FDS_OP_QUEUE_SIZE 4 +#endif + +// +//========================================================== + +// CRC - CRC functionality + +//========================================================== +// FDS_CRC_CHECK_ON_READ - Enable CRC checks. + +// Save a record's CRC when it is written to flash and check it when the record is opened. +// Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened. +// Additionally, they will not be garbage collected until they are deleted. +//========================================================== +#ifndef FDS_CRC_CHECK_ON_READ +#define FDS_CRC_CHECK_ON_READ 0 +#endif +// FDS_CRC_CHECK_ON_WRITE - Perform a CRC check on newly written records. + + +// Perform a CRC check on newly written records. +// This setting can be used to make sure that the record data was not altered while being written to flash. +// <1=> Enabled +// <0=> Disabled + +#ifndef FDS_CRC_CHECK_ON_WRITE +#define FDS_CRC_CHECK_ON_WRITE 0 +#endif + +// + +// +//========================================================== + +// Users - Number of users + +//========================================================== +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +#ifndef FDS_MAX_USERS +#define FDS_MAX_USERS 4 +#endif + +// +//========================================================== + +// + +// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release + + +#ifndef HARDFAULT_HANDLER_ENABLED +#define HARDFAULT_HANDLER_ENABLED 0 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 0 +#endif +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +// + +// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI +//========================================================== +#ifndef HCI_SLIP_ENABLED +#define HCI_SLIP_ENABLED 0 +#endif +// HCI_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef HCI_UART_BAUDRATE +#define HCI_UART_BAUDRATE 30801920 +#endif + +// HCI_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef HCI_UART_FLOW_CONTROL +#define HCI_UART_FLOW_CONTROL 0 +#endif + +// HCI_UART_RX_PIN - UART RX pin +#ifndef HCI_UART_RX_PIN +#define HCI_UART_RX_PIN 31 +#endif + +// HCI_UART_TX_PIN - UART TX pin +#ifndef HCI_UART_TX_PIN +#define HCI_UART_TX_PIN 31 +#endif + +// HCI_UART_RTS_PIN - UART RTS pin +#ifndef HCI_UART_RTS_PIN +#define HCI_UART_RTS_PIN 31 +#endif + +// HCI_UART_CTS_PIN - UART CTS pin +#ifndef HCI_UART_CTS_PIN +#define HCI_UART_CTS_PIN 31 +#endif + +// + +// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport +//========================================================== +#ifndef HCI_TRANSPORT_ENABLED +#define HCI_TRANSPORT_ENABLED 0 +#endif +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +#ifndef HCI_MAX_PACKET_SIZE_IN_BITS +#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 +#endif + +// + +// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module + + +#ifndef LED_SOFTBLINK_ENABLED +#define LED_SOFTBLINK_ENABLED 0 +#endif + +// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module + + +#ifndef LOW_POWER_PWM_ENABLED +#define LOW_POWER_PWM_ENABLED 0 +#endif + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 0 +#endif +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. +// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. +// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 +#endif + +// MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED +#define MEM_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// MEM_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL +#define MEM_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// MEM_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_INFO_COLOR +#define MEM_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// MEM_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR +#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +// + +// NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module +//========================================================== +#ifndef NRF_BALLOC_ENABLED +#define NRF_BALLOC_ENABLED 1 +#endif +// NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS +#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS +#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED - Enables basic checks in this module. + + +#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED +#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED - Enables double memory free check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED - Enables free memory corruption check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_BALLOC_CLI_CMDS +#define NRF_BALLOC_CLI_CMDS 0 +#endif + +// + +// + +// NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module +//========================================================== +#ifndef NRF_CSENSE_ENABLED +#define NRF_CSENSE_ENABLED 0 +#endif +// NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. +#ifndef NRF_CSENSE_PAD_HYSTERESIS +#define NRF_CSENSE_PAD_HYSTERESIS 15 +#endif + +// NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. +#ifndef NRF_CSENSE_PAD_DEVIATION +#define NRF_CSENSE_PAD_DEVIATION 70 +#endif + +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. +#ifndef NRF_CSENSE_MIN_PAD_VALUE +#define NRF_CSENSE_MIN_PAD_VALUE 20 +#endif + +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +#ifndef NRF_CSENSE_MAX_PADS_NUMBER +#define NRF_CSENSE_MAX_PADS_NUMBER 20 +#endif + +// NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. +#ifndef NRF_CSENSE_MAX_VALUE +#define NRF_CSENSE_MAX_VALUE 1000 +#endif + +// NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. +// This is used when capacitive sensor does not use COMP. + +#ifndef NRF_CSENSE_OUTPUT_PIN +#define NRF_CSENSE_OUTPUT_PIN 26 +#endif + +// + +// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module +//========================================================== +#ifndef NRF_DRV_CSENSE_ENABLED +#define NRF_DRV_CSENSE_ENABLED 0 +#endif +// USE_COMP - Use the comparator to implement the capacitive sensor driver. + +// Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation. +//========================================================== +#ifndef USE_COMP +#define USE_COMP 0 +#endif +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER0_FOR_CSENSE +#define TIMER0_FOR_CSENSE 1 +#endif + +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER1_FOR_CSENSE +#define TIMER1_FOR_CSENSE 2 +#endif + +// MEASUREMENT_PERIOD - Single measurement period. +// Time of a single measurement can be calculated as +// T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). +// I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad. + +#ifndef MEASUREMENT_PERIOD +#define MEASUREMENT_PERIOD 20 +#endif + +// + +// + +// NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library +//========================================================== +#ifndef NRF_FSTORAGE_ENABLED +#define NRF_FSTORAGE_ENABLED 0 +#endif +// nrf_fstorage - Common settings + +// Common settings to all fstorage implementations +//========================================================== +// NRF_FSTORAGE_PARAM_CHECK_DISABLED - Disable user input validation + + +// If selected, use ASSERT to validate user input. +// This effectively removes user input validation in production code. +// Recommended setting: OFF, only enable this setting if size is a major concern. + +#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED +#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0 +#endif + +// +//========================================================== + +// nrf_fstorage_sd - Implementation using the SoftDevice + +// Configuration options for the fstorage implementation using the SoftDevice +//========================================================== +// NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations +// Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM. + +#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE +#define NRF_FSTORAGE_SD_QUEUE_SIZE 4 +#endif + +// NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy +// Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error. +// The SoftDevice might fail to schedule flash access due to high BLE activity. + +#ifndef NRF_FSTORAGE_SD_MAX_RETRIES +#define NRF_FSTORAGE_SD_MAX_RETRIES 8 +#endif + +// NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation +// This value must be a multiple of four. +// Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity. +// This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write. +// That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs. + +#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE +#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096 +#endif + +// +//========================================================== + +// + +// NRF_GFX_ENABLED - nrf_gfx - GFX module + + +#ifndef NRF_GFX_ENABLED +#define NRF_GFX_ENABLED 0 +#endif + +// NRF_MEMOBJ_ENABLED - nrf_memobj - Linked memory allocator module + + +#ifndef NRF_MEMOBJ_ENABLED +#define NRF_MEMOBJ_ENABLED 1 +#endif + +// NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module +//========================================================== +#ifndef NRF_PWR_MGMT_ENABLED +#define NRF_PWR_MGMT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. + +// Selected pin will be set when CPU is in sleep mode. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED +#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0 +#endif +// NRF_PWR_MGMT_SLEEP_DEBUG_PIN - Pin number + +// <0=> 0 (P0.0) +// <1=> 1 (P0.1) +// <2=> 2 (P0.2) +// <3=> 3 (P0.3) +// <4=> 4 (P0.4) +// <5=> 5 (P0.5) +// <6=> 6 (P0.6) +// <7=> 7 (P0.7) +// <8=> 8 (P0.8) +// <9=> 9 (P0.9) +// <10=> 10 (P0.10) +// <11=> 11 (P0.11) +// <12=> 12 (P0.12) +// <13=> 13 (P0.13) +// <14=> 14 (P0.14) +// <15=> 15 (P0.15) +// <16=> 16 (P0.16) +// <17=> 17 (P0.17) +// <18=> 18 (P0.18) +// <19=> 19 (P0.19) +// <20=> 20 (P0.20) +// <21=> 21 (P0.21) +// <22=> 22 (P0.22) +// <23=> 23 (P0.23) +// <24=> 24 (P0.24) +// <25=> 25 (P0.25) +// <26=> 26 (P0.26) +// <27=> 27 (P0.27) +// <28=> 28 (P0.28) +// <29=> 29 (P0.29) +// <30=> 30 (P0.30) +// <31=> 31 (P0.31) +// <32=> 32 (P1.0) +// <33=> 33 (P1.1) +// <34=> 34 (P1.2) +// <35=> 35 (P1.3) +// <36=> 36 (P1.4) +// <37=> 37 (P1.5) +// <38=> 38 (P1.6) +// <39=> 39 (P1.7) +// <40=> 40 (P1.8) +// <41=> 41 (P1.9) +// <42=> 42 (P1.10) +// <43=> 43 (P1.11) +// <44=> 44 (P1.12) +// <45=> 45 (P1.13) +// <46=> 46 (P1.14) +// <47=> 47 (P1.15) +// <4294967295=> Not connected + +#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN +#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - Enables CPU usage monitor. + + +// Module will trace percentage of CPU usage in one second intervals. + +#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED +#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). +// Shutdown procedure will begin no earlier than after this number of seconds. + +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED - Enables FPU event cleaning. + + +#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED +#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - Blocked shutdown procedure will be retried every second. + + +#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY +#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0 +#endif + +// NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - Module will use @ref app_scheduler. + + +#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER +#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0 +#endif + +// NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. +// The number of stages of the shutdown process. + +#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT +#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3 +#endif + +// + +// NRF_QUEUE_ENABLED - nrf_queue - Queue module +//========================================================== +#ifndef NRF_QUEUE_ENABLED +#define NRF_QUEUE_ENABLED 0 +#endif +// NRF_QUEUE_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_QUEUE_CLI_CMDS +#define NRF_QUEUE_CLI_CMDS 0 +#endif + +// + +// NRF_SECTION_ITER_ENABLED - nrf_section_iter - Section iterator + + +#ifndef NRF_SECTION_ITER_ENABLED +#define NRF_SECTION_ITER_ENABLED 1 +#endif + +// NRF_SORTLIST_ENABLED - nrf_sortlist - Sorted list + + +#ifndef NRF_SORTLIST_ENABLED +#define NRF_SORTLIST_ENABLED 1 +#endif + +// NRF_SPI_MNGR_ENABLED - nrf_spi_mngr - SPI transaction manager + + +#ifndef NRF_SPI_MNGR_ENABLED +#define NRF_SPI_MNGR_ENABLED 0 +#endif + +// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. + + +#ifndef NRF_STRERROR_ENABLED +#define NRF_STRERROR_ENABLED 1 +#endif + +// NRF_TWI_MNGR_ENABLED - nrf_twi_mngr - TWI transaction manager + + +#ifndef NRF_TWI_MNGR_ENABLED +#define NRF_TWI_MNGR_ENABLED 0 +#endif + +// SLIP_ENABLED - slip - SLIP encoding and decoding + + +#ifndef SLIP_ENABLED +#define SLIP_ENABLED 0 +#endif + +// TASK_MANAGER_ENABLED - task_manager - Task manager. +//========================================================== +#ifndef TASK_MANAGER_ENABLED +#define TASK_MANAGER_ENABLED 0 +#endif +// TASK_MANAGER_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef TASK_MANAGER_CLI_CMDS +#define TASK_MANAGER_CLI_CMDS 0 +#endif + +// TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created +#ifndef TASK_MANAGER_CONFIG_MAX_TASKS +#define TASK_MANAGER_CONFIG_MAX_TASKS 2 +#endif + +// TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) +#ifndef TASK_MANAGER_CONFIG_STACK_SIZE +#define TASK_MANAGER_CONFIG_STACK_SIZE 1024 +#endif + +// TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED - Enable stack profiling. + + +#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED +#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1 +#endif + +// TASK_MANAGER_CONFIG_STACK_GUARD - Configures stack guard. + +// <0=> Disabled +// <4=> 32 bytes +// <5=> 64 bytes +// <6=> 128 bytes +// <7=> 256 bytes +// <8=> 512 bytes + +#ifndef TASK_MANAGER_CONFIG_STACK_GUARD +#define TASK_MANAGER_CONFIG_STACK_GUARD 7 +#endif + +// + +// app_button - buttons handling module + +//========================================================== +// BUTTON_ENABLED - Enables Button module + + +#ifndef BUTTON_ENABLED +#define BUTTON_ENABLED 0 +#endif + +// BUTTON_HIGH_ACCURACY_ENABLED - Enables GPIOTE high accuracy for buttons + + +#ifndef BUTTON_HIGH_ACCURACY_ENABLED +#define BUTTON_HIGH_ACCURACY_ENABLED 0 +#endif + +// +//========================================================== + +// app_usbd_cdc_acm - USB CDC ACM class + +//========================================================== +// APP_USBD_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library + + +#ifndef APP_USBD_CDC_ACM_ENABLED +#define APP_USBD_CDC_ACM_ENABLED 0 +#endif + +// APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE - Send ZLP on write with same size as endpoint + + +// If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint. +// This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent. + +#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE +#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1 +#endif + +// +//========================================================== + +// nrf_cli - Command line interface + +//========================================================== +// NRF_CLI_ENABLED - Enable/disable the CLI module. + + +#ifndef NRF_CLI_ENABLED +#define NRF_CLI_ENABLED 0 +#endif + +// NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. +#ifndef NRF_CLI_ARGC_MAX +#define NRF_CLI_ARGC_MAX 12 +#endif + +// NRF_CLI_BUILD_IN_CMDS_ENABLED - CLI built-in commands. + + +#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED +#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1 +#endif + +// NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. +#ifndef NRF_CLI_CMD_BUFF_SIZE +#define NRF_CLI_CMD_BUFF_SIZE 128 +#endif + +// NRF_CLI_ECHO_STATUS - CLI echo status. If set, echo is ON. + + +#ifndef NRF_CLI_ECHO_STATUS +#define NRF_CLI_ECHO_STATUS 1 +#endif + +// NRF_CLI_WILDCARD_ENABLED - Enable wildcard functionality for CLI commands. + + +#ifndef NRF_CLI_WILDCARD_ENABLED +#define NRF_CLI_WILDCARD_ENABLED 0 +#endif + +// NRF_CLI_METAKEYS_ENABLED - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u + + +#ifndef NRF_CLI_METAKEYS_ENABLED +#define NRF_CLI_METAKEYS_ENABLED 0 +#endif + +// NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. +#ifndef NRF_CLI_PRINTF_BUFF_SIZE +#define NRF_CLI_PRINTF_BUFF_SIZE 23 +#endif + +// NRF_CLI_HISTORY_ENABLED - Enable CLI history mode. +//========================================================== +#ifndef NRF_CLI_HISTORY_ENABLED +#define NRF_CLI_HISTORY_ENABLED 1 +#endif +// NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. +#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE +#define NRF_CLI_HISTORY_ELEMENT_SIZE 32 +#endif + +// NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. +#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT +#define NRF_CLI_HISTORY_ELEMENT_COUNT 8 +#endif + +// + +// NRF_CLI_VT100_COLORS_ENABLED - CLI VT100 colors. + + +#ifndef NRF_CLI_VT100_COLORS_ENABLED +#define NRF_CLI_VT100_COLORS_ENABLED 1 +#endif + +// NRF_CLI_STATISTICS_ENABLED - Enable CLI statistics. + + +#ifndef NRF_CLI_STATISTICS_ENABLED +#define NRF_CLI_STATISTICS_ENABLED 1 +#endif + +// NRF_CLI_LOG_BACKEND - Enable logger backend interface. + + +#ifndef NRF_CLI_LOG_BACKEND +#define NRF_CLI_LOG_BACKEND 1 +#endif + +// NRF_CLI_USES_TASK_MANAGER_ENABLED - Enable CLI to use task_manager + + +#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED +#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0 +#endif + +// +//========================================================== + +// nrf_fprintf - fprintf function. + +//========================================================== +// NRF_FPRINTF_ENABLED - Enable/disable fprintf module. + + +#ifndef NRF_FPRINTF_ENABLED +#define NRF_FPRINTF_ENABLED 1 +#endif + +// NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED - For each printed LF, function will add CR. + + +#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED +#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1 +#endif + +// NRF_FPRINTF_DOUBLE_ENABLED - Enable IEEE-754 double precision formatting. + + +#ifndef NRF_FPRINTF_DOUBLE_ENABLED +#define NRF_FPRINTF_DOUBLE_ENABLED 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Log + +//========================================================== +// NRF_LOG_ENABLED - nrf_log - Logger +//========================================================== +#ifndef NRF_LOG_ENABLED +#define NRF_LOG_ENABLED 0 +#endif +// Log message pool - Configuration of log message pool + +//========================================================== +// NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. +// If a small value is set, then performance of logs processing +// is degraded because data is fragmented. Bigger value impacts +// RAM memory utilization. The size is set to fit a message with +// a timestamp and up to 2 arguments in a single memory object. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE +#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20 +#endif + +// NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects +// If a small value is set, then it may lead to a deadlock +// in certain cases if backend has high latency and holds +// multiple messages for long time. Bigger value impacts +// RAM memory usage. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT +#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8 +#endif + +// +//========================================================== + +// NRF_LOG_ALLOW_OVERFLOW - Configures behavior when circular buffer is full. + + +// If set then oldest logs are overwritten. Otherwise a +// marker is injected informing about overflow. + +#ifndef NRF_LOG_ALLOW_OVERFLOW +#define NRF_LOG_ALLOW_OVERFLOW 1 +#endif + +// NRF_LOG_BUFSIZE - Size of the buffer for storing logs (in bytes). + + +// Must be power of 2 and multiple of 4. +// If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum. +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 +// <2048=> 2048 +// <4096=> 4096 +// <8192=> 8192 +// <16384=> 16384 + +#ifndef NRF_LOG_BUFSIZE +#define NRF_LOG_BUFSIZE 1024 +#endif + +// NRF_LOG_CLI_CMDS - Enable CLI commands for the module. + + +#ifndef NRF_LOG_CLI_CMDS +#define NRF_LOG_CLI_CMDS 0 +#endif + +// NRF_LOG_DEFAULT_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 3 +#endif + +// NRF_LOG_DEFERRED - Enable deffered logger. + + +// Log data is buffered and can be processed in idle. + +#ifndef NRF_LOG_DEFERRED +#define NRF_LOG_DEFERRED 1 +#endif + +// NRF_LOG_FILTERS_ENABLED - Enable dynamic filtering of logs. + + +#ifndef NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_FILTERS_ENABLED 0 +#endif + +// NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED - Enable use of critical region for non deffered mode when flushing logs. + + +// When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used. +// Log output will never be corrupted as access to the log backend is exclusive +// but system will spend significant amount of time in critical section + +#ifndef NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED +#define NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED 0 +#endif + +// NRF_LOG_STR_PUSH_BUFFER_SIZE - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH. + +// <16=> 16 +// <32=> 32 +// <64=> 64 +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE +#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 +#endif + +// NRF_LOG_STR_PUSH_BUFFER_SIZE - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH. + +// <16=> 16 +// <32=> 32 +// <64=> 64 +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE +#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 +#endif + +// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string +//========================================================== +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif +// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_ERROR_COLOR +#define NRF_LOG_ERROR_COLOR 2 +#endif + +// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_WARNING_COLOR +#define NRF_LOG_WARNING_COLOR 4 +#endif + +// + +// NRF_LOG_USES_TIMESTAMP - Enable timestamping + +// Function for getting the timestamp is provided by the user +//========================================================== +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif +// NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency. +#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY +#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0 +#endif + +// + +// nrf_log module configuration + +//========================================================== +// nrf_log in nRF_Core + +//========================================================== +// NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MPU_LIB_CONFIG_LOG_ENABLED +#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MPU_LIB_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL +#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MPU_LIB_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR +#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MPU_LIB_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR +#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED +#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL +#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_STACK_GUARD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR +#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0 +#endif + +// NRF_STACK_GUARD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR +#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED +#define TASK_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// TASK_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL +#define TASK_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// TASK_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_INFO_COLOR +#define TASK_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// TASK_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR +#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Drivers + +//========================================================== +// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef CLOCK_CONFIG_LOG_ENABLED +#define CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef CLOCK_CONFIG_LOG_LEVEL +#define CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_INFO_COLOR +#define CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_DEBUG_COLOR +#define CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMP_CONFIG_LOG_ENABLED +#define COMP_CONFIG_LOG_ENABLED 0 +#endif +// COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMP_CONFIG_LOG_LEVEL +#define COMP_CONFIG_LOG_LEVEL 3 +#endif + +// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_INFO_COLOR +#define COMP_CONFIG_INFO_COLOR 0 +#endif + +// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_DEBUG_COLOR +#define COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef GPIOTE_CONFIG_LOG_ENABLED +#define GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef GPIOTE_CONFIG_LOG_LEVEL +#define GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_INFO_COLOR +#define GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_DEBUG_COLOR +#define GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef LPCOMP_CONFIG_LOG_ENABLED +#define LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef LPCOMP_CONFIG_LOG_LEVEL +#define LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_INFO_COLOR +#define LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_DEBUG_COLOR +#define LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MAX3421E_HOST_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef MAX3421E_HOST_CONFIG_LOG_ENABLED +#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0 +#endif +// MAX3421E_HOST_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL +#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3 +#endif + +// MAX3421E_HOST_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MAX3421E_HOST_CONFIG_INFO_COLOR +#define MAX3421E_HOST_CONFIG_INFO_COLOR 0 +#endif + +// MAX3421E_HOST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR +#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef NRFX_USBD_CONFIG_LOG_ENABLED +#define NRFX_USBD_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_USBD_CONFIG_LOG_LEVEL +#define NRFX_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_INFO_COLOR +#define NRFX_USBD_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR +#define NRFX_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PDM_CONFIG_LOG_ENABLED +#define PDM_CONFIG_LOG_ENABLED 0 +#endif +// PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PDM_CONFIG_LOG_LEVEL +#define PDM_CONFIG_LOG_LEVEL 3 +#endif + +// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_INFO_COLOR +#define PDM_CONFIG_INFO_COLOR 0 +#endif + +// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_DEBUG_COLOR +#define PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PPI_CONFIG_LOG_ENABLED +#define PPI_CONFIG_LOG_ENABLED 0 +#endif +// PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PPI_CONFIG_LOG_LEVEL +#define PPI_CONFIG_LOG_LEVEL 3 +#endif + +// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_INFO_COLOR +#define PPI_CONFIG_INFO_COLOR 0 +#endif + +// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_DEBUG_COLOR +#define PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PWM_CONFIG_LOG_ENABLED +#define PWM_CONFIG_LOG_ENABLED 0 +#endif +// PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PWM_CONFIG_LOG_LEVEL +#define PWM_CONFIG_LOG_LEVEL 3 +#endif + +// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_INFO_COLOR +#define PWM_CONFIG_INFO_COLOR 0 +#endif + +// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_DEBUG_COLOR +#define PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef QDEC_CONFIG_LOG_ENABLED +#define QDEC_CONFIG_LOG_ENABLED 0 +#endif +// QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef QDEC_CONFIG_LOG_LEVEL +#define QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_INFO_COLOR +#define QDEC_CONFIG_INFO_COLOR 0 +#endif + +// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_DEBUG_COLOR +#define QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RNG_CONFIG_LOG_ENABLED +#define RNG_CONFIG_LOG_ENABLED 0 +#endif +// RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RNG_CONFIG_LOG_LEVEL +#define RNG_CONFIG_LOG_LEVEL 3 +#endif + +// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_INFO_COLOR +#define RNG_CONFIG_INFO_COLOR 0 +#endif + +// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_DEBUG_COLOR +#define RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - Enables logging of random numbers. + + +#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED +#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 +#endif + +// + +// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RTC_CONFIG_LOG_ENABLED +#define RTC_CONFIG_LOG_ENABLED 0 +#endif +// RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RTC_CONFIG_LOG_LEVEL +#define RTC_CONFIG_LOG_LEVEL 3 +#endif + +// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_INFO_COLOR +#define RTC_CONFIG_INFO_COLOR 0 +#endif + +// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_DEBUG_COLOR +#define RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SAADC_CONFIG_LOG_ENABLED +#define SAADC_CONFIG_LOG_ENABLED 0 +#endif +// SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SAADC_CONFIG_LOG_LEVEL +#define SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_INFO_COLOR +#define SAADC_CONFIG_INFO_COLOR 0 +#endif + +// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_DEBUG_COLOR +#define SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPIS_CONFIG_LOG_ENABLED +#define SPIS_CONFIG_LOG_ENABLED 0 +#endif +// SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPIS_CONFIG_LOG_LEVEL +#define SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_INFO_COLOR +#define SPIS_CONFIG_INFO_COLOR 0 +#endif + +// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_DEBUG_COLOR +#define SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPI_CONFIG_LOG_ENABLED +#define SPI_CONFIG_LOG_ENABLED 0 +#endif +// SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPI_CONFIG_LOG_LEVEL +#define SPI_CONFIG_LOG_LEVEL 3 +#endif + +// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_INFO_COLOR +#define SPI_CONFIG_INFO_COLOR 0 +#endif + +// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_DEBUG_COLOR +#define SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TIMER_CONFIG_LOG_ENABLED +#define TIMER_CONFIG_LOG_ENABLED 0 +#endif +// TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TIMER_CONFIG_LOG_LEVEL +#define TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_INFO_COLOR +#define TIMER_CONFIG_INFO_COLOR 0 +#endif + +// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_DEBUG_COLOR +#define TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWIS_CONFIG_LOG_ENABLED +#define TWIS_CONFIG_LOG_ENABLED 0 +#endif +// TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWIS_CONFIG_LOG_LEVEL +#define TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_INFO_COLOR +#define TWIS_CONFIG_INFO_COLOR 0 +#endif + +// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_DEBUG_COLOR +#define TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWI_CONFIG_LOG_ENABLED +#define TWI_CONFIG_LOG_ENABLED 0 +#endif +// TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWI_CONFIG_LOG_LEVEL +#define TWI_CONFIG_LOG_LEVEL 3 +#endif + +// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_INFO_COLOR +#define TWI_CONFIG_INFO_COLOR 0 +#endif + +// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_DEBUG_COLOR +#define TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef UART_CONFIG_LOG_ENABLED +#define UART_CONFIG_LOG_ENABLED 0 +#endif +// UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef UART_CONFIG_LOG_LEVEL +#define UART_CONFIG_LOG_LEVEL 3 +#endif + +// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_INFO_COLOR +#define UART_CONFIG_INFO_COLOR 0 +#endif + +// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_DEBUG_COLOR +#define UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef USBD_CONFIG_LOG_ENABLED +#define USBD_CONFIG_LOG_ENABLED 0 +#endif +// USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef USBD_CONFIG_LOG_LEVEL +#define USBD_CONFIG_LOG_LEVEL 3 +#endif + +// USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_INFO_COLOR +#define USBD_CONFIG_INFO_COLOR 0 +#endif + +// USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_DEBUG_COLOR +#define USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef WDT_CONFIG_LOG_ENABLED +#define WDT_CONFIG_LOG_ENABLED 0 +#endif +// WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef WDT_CONFIG_LOG_LEVEL +#define WDT_CONFIG_LOG_LEVEL 3 +#endif + +// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_INFO_COLOR +#define WDT_CONFIG_INFO_COLOR 0 +#endif + +// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_DEBUG_COLOR +#define WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Libraries + +//========================================================== +// APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_BUTTON_CONFIG_LOG_ENABLED +#define APP_BUTTON_CONFIG_LOG_ENABLED 0 +#endif +// APP_BUTTON_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_BUTTON_CONFIG_LOG_LEVEL +#define APP_BUTTON_CONFIG_LOG_LEVEL 3 +#endif + +// APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL +#define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// APP_BUTTON_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_BUTTON_CONFIG_INFO_COLOR +#define APP_BUTTON_CONFIG_INFO_COLOR 0 +#endif + +// APP_BUTTON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_BUTTON_CONFIG_DEBUG_COLOR +#define APP_BUTTON_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_TIMER_CONFIG_LOG_ENABLED +#define APP_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// APP_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_TIMER_CONFIG_LOG_LEVEL +#define APP_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// APP_TIMER_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL +#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// APP_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_TIMER_CONFIG_INFO_COLOR +#define APP_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// APP_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_TIMER_CONFIG_DEBUG_COLOR +#define APP_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED +#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL +#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CDC_ACM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR +#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR +#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module. +//========================================================== +#ifndef APP_USBD_CONFIG_LOG_ENABLED +#define APP_USBD_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CONFIG_LOG_LEVEL +#define APP_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CONFIG_INFO_COLOR +#define APP_USBD_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CONFIG_DEBUG_COLOR +#define APP_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED +#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_DUMMY_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL +#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_DUMMY_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR +#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_DUMMY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR +#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED +#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_MSC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL +#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_MSC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR +#define APP_USBD_MSC_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_MSC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR +#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED +#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0 +#endif +// NRF_ATFIFO_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL +#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_ATFIFO_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR +#define NRF_ATFIFO_CONFIG_INFO_COLOR 0 +#endif + +// NRF_ATFIFO_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR +#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED +#define NRF_BALLOC_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL +#define NRF_BALLOC_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL +#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_INFO_COLOR +#define NRF_BALLOC_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BALLOC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR +#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_BLE_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR +#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED +#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL +#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR +#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR +#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR +#define NRF_CLI_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED +#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL +#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR +#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR +#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED +#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MEMOBJ_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL +#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MEMOBJ_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR +#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MEMOBJ_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR +#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED +#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL +#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_PWR_MGMT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR +#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0 +#endif + +// NRF_PWR_MGMT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR +#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED +#define NRF_QUEUE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_QUEUE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL +#define NRF_QUEUE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_QUEUE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_QUEUE_CONFIG_INFO_COLOR +#define NRF_QUEUE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_QUEUE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR +#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module. +//========================================================== +#ifndef NRF_SDH_ANT_LOG_ENABLED +#define NRF_SDH_ANT_LOG_ENABLED 0 +#endif +// NRF_SDH_ANT_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_ANT_LOG_LEVEL +#define NRF_SDH_ANT_LOG_LEVEL 3 +#endif + +// NRF_SDH_ANT_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_INFO_COLOR +#define NRF_SDH_ANT_INFO_COLOR 0 +#endif + +// NRF_SDH_ANT_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_DEBUG_COLOR +#define NRF_SDH_ANT_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module. +//========================================================== +#ifndef NRF_SDH_BLE_LOG_ENABLED +#define NRF_SDH_BLE_LOG_ENABLED 1 +#endif +// NRF_SDH_BLE_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_BLE_LOG_LEVEL +#define NRF_SDH_BLE_LOG_LEVEL 3 +#endif + +// NRF_SDH_BLE_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_INFO_COLOR +#define NRF_SDH_BLE_INFO_COLOR 0 +#endif + +// NRF_SDH_BLE_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_DEBUG_COLOR +#define NRF_SDH_BLE_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module. +//========================================================== +#ifndef NRF_SDH_LOG_ENABLED +#define NRF_SDH_LOG_ENABLED 1 +#endif +// NRF_SDH_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_LOG_LEVEL +#define NRF_SDH_LOG_LEVEL 3 +#endif + +// NRF_SDH_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_INFO_COLOR +#define NRF_SDH_INFO_COLOR 0 +#endif + +// NRF_SDH_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_DEBUG_COLOR +#define NRF_SDH_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module. +//========================================================== +#ifndef NRF_SDH_SOC_LOG_ENABLED +#define NRF_SDH_SOC_LOG_ENABLED 1 +#endif +// NRF_SDH_SOC_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_SOC_LOG_LEVEL +#define NRF_SDH_SOC_LOG_LEVEL 3 +#endif + +// NRF_SDH_SOC_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_INFO_COLOR +#define NRF_SDH_SOC_INFO_COLOR 0 +#endif + +// NRF_SDH_SOC_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_DEBUG_COLOR +#define NRF_SDH_SOC_DEBUG_COLOR 0 +#endif + +// + +// NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED +#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0 +#endif +// NRF_SORTLIST_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL +#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_SORTLIST_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR +#define NRF_SORTLIST_CONFIG_INFO_COLOR 0 +#endif + +// NRF_SORTLIST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR +#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED +#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0 +#endif +// NRF_TWI_SENSOR_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL +#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_TWI_SENSOR_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR +#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0 +#endif + +// NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR +#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PM_LOG_ENABLED - Enable logging in Peer Manager and its submodules. +//========================================================== +#ifndef PM_LOG_ENABLED +#define PM_LOG_ENABLED 1 +#endif +// PM_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PM_LOG_LEVEL +#define PM_LOG_LEVEL 3 +#endif + +// PM_LOG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PM_LOG_INFO_COLOR +#define PM_LOG_INFO_COLOR 0 +#endif + +// PM_LOG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PM_LOG_DEBUG_COLOR +#define PM_LOG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Serialization + +//========================================================== +// SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED +#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0 +#endif +// SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL +#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3 +#endif + +// SER_HAL_TRANSPORT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR +#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0 +#endif + +// SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR +#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// +//========================================================== + +// + +// NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED - nrf_log_str_formatter - Log string formatter + + +#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED +#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1 +#endif + +// +//========================================================== + +// nRF_NFC + +//========================================================== +// NFC_AC_REC_ENABLED - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder + + +#ifndef NFC_AC_REC_ENABLED +#define NFC_AC_REC_ENABLED 0 +#endif + +// NFC_AC_REC_PARSER_ENABLED - nfc_ac_rec_parser - Alternative Carrier record parser + + +#ifndef NFC_AC_REC_PARSER_ENABLED +#define NFC_AC_REC_PARSER_ENABLED 0 +#endif + +// NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder +//========================================================== +#ifndef NFC_BLE_OOB_ADVDATA_ENABLED +#define NFC_BLE_OOB_ADVDATA_ENABLED 0 +#endif +// ADVANCED_ADVDATA_SUPPORT - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs) + +// <1=> Enabled +// <0=> Disabled + +#ifndef ADVANCED_ADVDATA_SUPPORT +#define ADVANCED_ADVDATA_SUPPORT 0 +#endif + +// + +// NFC_BLE_OOB_ADVDATA_PARSER_ENABLED - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser + + +#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED +#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0 +#endif + +// NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters +//========================================================== +#ifndef NFC_BLE_PAIR_LIB_ENABLED +#define NFC_BLE_PAIR_LIB_ENABLED 0 +#endif +// NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED +#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0 +#endif +// NFC_BLE_PAIR_LIB_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL +#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3 +#endif + +// NFC_BLE_PAIR_LIB_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR +#define NFC_BLE_PAIR_LIB_INFO_COLOR 0 +#endif + +// NFC_BLE_PAIR_LIB_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR +#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0 +#endif + +// + +// NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters. + +//========================================================== +// BLE_NFC_SEC_PARAM_BOND - Enables device bonding. + +// If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled. +//========================================================== +#ifndef BLE_NFC_SEC_PARAM_BOND +#define BLE_NFC_SEC_PARAM_BOND 1 +#endif +// BLE_NFC_SEC_PARAM_KDIST_OWN_ENC - Enables Long Term Key and Master Identification distribution by device. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC +#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_OWN_ID - Enables Identity Resolving Key and Identity Address Information distribution by device. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID +#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_PEER_ENC - Enables Long Term Key and Master Identification distribution by peer. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC +#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_PEER_ID - Enables Identity Resolving Key and Identity Address Information distribution by peer. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID +#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1 +#endif + +// + +// BLE_NFC_SEC_PARAM_MIN_KEY_SIZE - Minimal size of a security key. + +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <16=> 16 + +#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE +#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7 +#endif + +// BLE_NFC_SEC_PARAM_MAX_KEY_SIZE - Maximal size of a security key. + +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <16=> 16 + +#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE +#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16 +#endif + +// +//========================================================== + +// + +// NFC_BLE_PAIR_MSG_ENABLED - nfc_ble_pair_msg - NDEF message for OOB pairing encoder + + +#ifndef NFC_BLE_PAIR_MSG_ENABLED +#define NFC_BLE_PAIR_MSG_ENABLED 0 +#endif + +// NFC_CH_COMMON_ENABLED - nfc_ble_pair_common - OOB pairing common data + + +#ifndef NFC_CH_COMMON_ENABLED +#define NFC_CH_COMMON_ENABLED 0 +#endif + +// NFC_EP_OOB_REC_ENABLED - nfc_ep_oob_rec - EP record for BLE pairing encoder + + +#ifndef NFC_EP_OOB_REC_ENABLED +#define NFC_EP_OOB_REC_ENABLED 0 +#endif + +// NFC_HS_REC_ENABLED - nfc_hs_rec - Handover Select NDEF record encoder + + +#ifndef NFC_HS_REC_ENABLED +#define NFC_HS_REC_ENABLED 0 +#endif + +// NFC_LE_OOB_REC_ENABLED - nfc_le_oob_rec - LE record for BLE pairing encoder + + +#ifndef NFC_LE_OOB_REC_ENABLED +#define NFC_LE_OOB_REC_ENABLED 0 +#endif + +// NFC_LE_OOB_REC_PARSER_ENABLED - nfc_le_oob_rec_parser - LE record parser + + +#ifndef NFC_LE_OOB_REC_PARSER_ENABLED +#define NFC_LE_OOB_REC_PARSER_ENABLED 0 +#endif + +// NFC_NDEF_LAUNCHAPP_MSG_ENABLED - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag + + +#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED +#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0 +#endif + +// NFC_NDEF_LAUNCHAPP_REC_ENABLED - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag + + +#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED +#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0 +#endif + +// NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module +//========================================================== +#ifndef NFC_NDEF_MSG_ENABLED +#define NFC_NDEF_MSG_ENABLED 0 +#endif +// NFC_NDEF_MSG_TAG_TYPE - NFC Tag Type + +// <2=> Type 2 Tag +// <4=> Type 4 Tag + +#ifndef NFC_NDEF_MSG_TAG_TYPE +#define NFC_NDEF_MSG_TAG_TYPE 2 +#endif + +// + +// NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module +//========================================================== +#ifndef NFC_NDEF_MSG_PARSER_ENABLED +#define NFC_NDEF_MSG_PARSER_ENABLED 0 +#endif +// NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED +#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0 +#endif +// NFC_NDEF_MSG_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL +#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3 +#endif + +// NFC_NDEF_MSG_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR +#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_NDEF_RECORD_ENABLED - nfc_ndef_record - NFC NDEF Record generator module + + +#ifndef NFC_NDEF_RECORD_ENABLED +#define NFC_NDEF_RECORD_ENABLED 0 +#endif + +// NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module +//========================================================== +#ifndef NFC_NDEF_RECORD_PARSER_ENABLED +#define NFC_NDEF_RECORD_PARSER_ENABLED 0 +#endif +// NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED +#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0 +#endif +// NFC_NDEF_RECORD_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL +#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3 +#endif + +// NFC_NDEF_RECORD_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR +#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_NDEF_TEXT_RECORD_ENABLED - nfc_text_rec - Encoding data for a text record for NFC Tag + + +#ifndef NFC_NDEF_TEXT_RECORD_ENABLED +#define NFC_NDEF_TEXT_RECORD_ENABLED 0 +#endif + +// NFC_NDEF_URI_MSG_ENABLED - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag + + +#ifndef NFC_NDEF_URI_MSG_ENABLED +#define NFC_NDEF_URI_MSG_ENABLED 0 +#endif + +// NFC_NDEF_URI_REC_ENABLED - nfc_uri_rec - Encoding data for a URI record for NFC Tag + + +#ifndef NFC_NDEF_URI_REC_ENABLED +#define NFC_NDEF_URI_REC_ENABLED 0 +#endif + +// NFC_PLATFORM_ENABLED - nfc_platform - NFC platform module for Clock control. +//========================================================== +#ifndef NFC_PLATFORM_ENABLED +#define NFC_PLATFORM_ENABLED 0 +#endif +// NFC_PLATFORM_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_PLATFORM_LOG_ENABLED +#define NFC_PLATFORM_LOG_ENABLED 0 +#endif +// NFC_PLATFORM_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_PLATFORM_LOG_LEVEL +#define NFC_PLATFORM_LOG_LEVEL 3 +#endif + +// NFC_PLATFORM_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_PLATFORM_INFO_COLOR +#define NFC_PLATFORM_INFO_COLOR 0 +#endif + +// NFC_PLATFORM_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_PLATFORM_DEBUG_COLOR +#define NFC_PLATFORM_DEBUG_COLOR 0 +#endif + +// + +// + +// NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data +//========================================================== +#ifndef NFC_T2T_PARSER_ENABLED +#define NFC_T2T_PARSER_ENABLED 0 +#endif +// NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T2T_PARSER_LOG_ENABLED +#define NFC_T2T_PARSER_LOG_ENABLED 0 +#endif +// NFC_T2T_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T2T_PARSER_LOG_LEVEL +#define NFC_T2T_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T2T_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T2T_PARSER_INFO_COLOR +#define NFC_T2T_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_APDU_ENABLED +#define NFC_T4T_APDU_ENABLED 0 +#endif +// NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_APDU_LOG_ENABLED +#define NFC_T4T_APDU_LOG_ENABLED 0 +#endif +// NFC_T4T_APDU_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_APDU_LOG_LEVEL +#define NFC_T4T_APDU_LOG_LEVEL 3 +#endif + +// NFC_T4T_APDU_LOG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_APDU_LOG_COLOR +#define NFC_T4T_APDU_LOG_COLOR 0 +#endif + +// + +// + +// NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED +#define NFC_T4T_CC_FILE_PARSER_ENABLED 0 +#endif +// NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED +#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0 +#endif +// NFC_T4T_CC_FILE_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL +#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T4T_CC_FILE_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR +#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED +#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0 +#endif +// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED +#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0 +#endif +// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL +#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3 +#endif + +// NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR +#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0 +#endif + +// + +// APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage +#ifndef APDU_BUFF_SIZE +#define APDU_BUFF_SIZE 250 +#endif + +// CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage +#ifndef CC_STORAGE_BUFF_SIZE +#define CC_STORAGE_BUFF_SIZE 64 +#endif + +// + +// NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED +#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0 +#endif +// NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED +#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0 +#endif +// NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL +#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR +#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// +//========================================================== + +// nRF_SoftDevice + +//========================================================== +// NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler +//========================================================== +#ifndef NRF_SDH_BLE_ENABLED +#define NRF_SDH_BLE_ENABLED 0 +#endif +// BLE Stack configuration - Stack configuration parameters + +// The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set. +// Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set. +//========================================================== +// NRF_SDH_BLE_GAP_DATA_LENGTH <27-251> + + +// Requested BLE GAP data length to be negotiated. + +#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH +#define NRF_SDH_BLE_GAP_DATA_LENGTH 27 +#endif + +// NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. +#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT +#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0 +#endif + +// NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. +#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT +#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0 +#endif + +// NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. +// Maximum number of total concurrent connections using the default configuration. + +#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT +#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1 +#endif + +// NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. +// The time set aside for this connection on every connection interval in 1.25 ms units. + +#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH +#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6 +#endif + +// NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. +#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE +#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23 +#endif + +// NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. +#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE +#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408 +#endif + +// NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. +#ifndef NRF_SDH_BLE_VS_UUID_COUNT +#define NRF_SDH_BLE_VS_UUID_COUNT 0 +#endif + +// NRF_SDH_BLE_SERVICE_CHANGED - Include the Service Changed characteristic in the Attribute Table. + + +#ifndef NRF_SDH_BLE_SERVICE_CHANGED +#define NRF_SDH_BLE_SERVICE_CHANGED 0 +#endif + +// +//========================================================== + +// BLE Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. +// This setting configures the number of priority levels available for BLE event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4 +#endif + +// BLE Observers priorities - Invididual priorities + +//========================================================== +// BLE_ADV_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Advertising module. + +#ifndef BLE_ADV_BLE_OBSERVER_PRIO +#define BLE_ADV_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_ANCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Apple Notification Service Client. + +#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO +#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_ANS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Alert Notification Service Client. + +#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO +#define BLE_ANS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service. + +#ifndef BLE_BAS_BLE_OBSERVER_PRIO +#define BLE_BAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service Client. + +#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO +#define BLE_BAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Blood Pressure Service. + +#ifndef BLE_BPS_BLE_OBSERVER_PRIO +#define BLE_BPS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection parameters module. + +#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_CONN_STATE_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection State module. + +#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO +#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0 +#endif + +// BLE_CSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service. + +#ifndef BLE_CSCS_BLE_OBSERVER_PRIO +#define BLE_CSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Current Time Service Client. + +#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO +#define BLE_CTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DB_DISC_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Database Discovery module. + +#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO +#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_DFU_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_BLE_OBSERVER_PRIO +#define BLE_DFU_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DIS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Device Information Client. + +#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO +#define BLE_DIS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_GLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Glucose Service. + +#ifndef BLE_GLS_BLE_OBSERVER_PRIO +#define BLE_GLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HIDS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Human Interface Device Service. + +#ifndef BLE_HIDS_BLE_OBSERVER_PRIO +#define BLE_HIDS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service. + +#ifndef BLE_HRS_BLE_OBSERVER_PRIO +#define BLE_HRS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service Client. + +#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO +#define BLE_HRS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Health Thermometer Service. + +#ifndef BLE_HTS_BLE_OBSERVER_PRIO +#define BLE_HTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service. + +#ifndef BLE_IAS_BLE_OBSERVER_PRIO +#define BLE_IAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service Client. + +#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO +#define BLE_IAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service. + +#ifndef BLE_LBS_BLE_OBSERVER_PRIO +#define BLE_LBS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service Client. + +#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO +#define BLE_LBS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Link Loss Service. + +#ifndef BLE_LLS_BLE_OBSERVER_PRIO +#define BLE_LLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LNS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Location Navigation Service. + +#ifndef BLE_LNS_BLE_OBSERVER_PRIO +#define BLE_LNS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Service. + +#ifndef BLE_NUS_BLE_OBSERVER_PRIO +#define BLE_NUS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Central Service. + +#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO +#define BLE_NUS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service. + +#ifndef BLE_OTS_BLE_OBSERVER_PRIO +#define BLE_OTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service client. + +#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO +#define BLE_OTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Service. + +#ifndef BLE_RSCS_BLE_OBSERVER_PRIO +#define BLE_RSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Client. + +#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO +#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_TPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the TX Power Service. + +#ifndef BLE_TPS_BLE_OBSERVER_PRIO +#define BLE_TPS_BLE_OBSERVER_PRIO 2 +#endif + +// BSP_BTN_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Button Control module. + +#ifndef BSP_BTN_BLE_OBSERVER_PRIO +#define BSP_BTN_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_BMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Bond Management Service. + +#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO +#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_CGMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service. + +#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO +#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_ES_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Eddystone module. + +#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO +#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT Service Client. + +#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATT_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT module. + +#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO +#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_GQ_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT Queue module. + +#ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO +#define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_QWR_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Queued writes module. + +#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO +#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_SCAN_OBSERVER_PRIO +// Priority for dispatching the BLE events to the Scanning Module. + +#ifndef NRF_BLE_SCAN_OBSERVER_PRIO +#define NRF_BLE_SCAN_OBSERVER_PRIO 1 +#endif + +// PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. +#ifndef PM_BLE_OBSERVER_PRIO +#define PM_BLE_OBSERVER_PRIO 1 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler +//========================================================== +#ifndef NRF_SDH_ENABLED +#define NRF_SDH_ENABLED 0 +#endif +// Dispatch model + +// This setting configures how Stack events are dispatched to the application. +//========================================================== +// NRF_SDH_DISPATCH_MODEL + + +// NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context. +// NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler. +// NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually. +// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT +// <1=> NRF_SDH_DISPATCH_MODEL_APPSH +// <2=> NRF_SDH_DISPATCH_MODEL_POLLING + +#ifndef NRF_SDH_DISPATCH_MODEL +#define NRF_SDH_DISPATCH_MODEL 0 +#endif + +// +//========================================================== + +// Clock - SoftDevice clock configuration + +//========================================================== +// NRF_SDH_CLOCK_LF_SRC - SoftDevice clock source. + +// <0=> NRF_CLOCK_LF_SRC_RC +// <1=> NRF_CLOCK_LF_SRC_XTAL +// <2=> NRF_CLOCK_LF_SRC_SYNTH + +#ifndef NRF_SDH_CLOCK_LF_SRC +#define NRF_SDH_CLOCK_LF_SRC 1 +#endif + +// NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. +#ifndef NRF_SDH_CLOCK_LF_RC_CTIV +#define NRF_SDH_CLOCK_LF_RC_CTIV 0 +#endif + +// NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. +// How often (in number of calibration intervals) the RC oscillator shall be calibrated +// if the temperature has not changed. + +#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV +#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 +#endif + +// NRF_SDH_CLOCK_LF_ACCURACY - External clock accuracy used in the LL to compute timing. + +// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM +// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM +// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM +// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM +// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM +// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM +// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM +// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM +// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM +// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM +// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM +// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM + +#ifndef NRF_SDH_CLOCK_LF_ACCURACY +#define NRF_SDH_CLOCK_LF_ACCURACY 7 +#endif + +// +//========================================================== + +// SDH Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. +// This setting configures the number of priority levels available for the SoftDevice request event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS +#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. +// This setting configures the number of priority levels available for the SoftDevice state event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. +// This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC). +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2 +#endif + + +// State Observers priorities - Invididual priorities + +//========================================================== +// CLOCK_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO +#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO +#define POWER_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// RNG_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to this module. + +#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO +#define RNG_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// Stack Event Observers priorities - Invididual priorities + +//========================================================== +// NRF_SDH_ANT_STACK_OBSERVER_PRIO +// This setting configures the priority with which ANT events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO +#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_BLE_STACK_OBSERVER_PRIO +// This setting configures the priority with which BLE events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO +#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_SOC_STACK_OBSERVER_PRIO +// This setting configures the priority with which SoC events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE. +// Zero is the highest priority. + +#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO +#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler +//========================================================== +#ifndef NRF_SDH_SOC_ENABLED +#define NRF_SDH_SOC_ENABLED 0 +#endif +// SoC Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. +// This setting configures the number of priority levels available for the SoC event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS +#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2 +#endif + +// SoC Observers priorities - Invididual priorities + +//========================================================== +// BLE_DFU_SOC_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_SOC_OBSERVER_PRIO +#define BLE_DFU_SOC_OBSERVER_PRIO 1 +#endif + +// CLOCK_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO +#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO +#define POWER_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver +//========================================================== +#ifndef NRFX_NVMC_ENABLED +#define NRFX_NVMC_ENABLED 1 +#endif +// + +//========================================================== +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 1 +#endif +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H + diff --git a/bsp/nrf5x/nrf52832/project.uvoptx b/bsp/nrf5x/nrf52832/project.uvoptx index b672a88f0c0ef3f08539ba648e524d5761a50281..955f05ebf681e0c09fd2297ff68ccb1299675fcd 100644 --- a/bsp/nrf5x/nrf52832/project.uvoptx +++ b/bsp/nrf5x/nrf52832/project.uvoptx @@ -120,12 +120,12 @@ 0 JL2CM3 - -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm) + -U682327541 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm) 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm) @@ -175,8 +175,8 @@ - Kernel - 0 + Applications + 1 0 0 0 @@ -187,763 +187,763 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c + applications\application.c + application.c 0 0 + + + + cpu + 0 + 0 + 0 + 0 - 1 + 2 2 1 0 0 0 - ..\..\..\src\components.c - components.c + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c 0 0 - 1 + 2 3 1 0 0 0 - ..\..\..\src\device.c - device.c + ..\..\..\libcpu\arm\common\div0.c + div0.c 0 0 - 1 + 2 4 1 0 0 0 - ..\..\..\src\idle.c - idle.c + ..\..\..\libcpu\arm\common\showmem.c + showmem.c 0 0 - 1 + 2 5 1 0 0 0 - ..\..\..\src\ipc.c - ipc.c + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c 0 0 - 1 + 2 6 - 1 + 2 0 0 0 - ..\..\..\src\irq.c - irq.c + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S 0 0 + + + + DeviceDrivers + 0 + 0 + 0 + 0 - 1 + 3 7 1 0 0 0 - ..\..\..\src\kservice.c - kservice.c + ..\..\..\components\drivers\misc\pin.c + pin.c 0 0 - 1 + 3 8 1 0 0 0 - ..\..\..\src\mem.c - mem.c + ..\..\..\components\drivers\serial\serial.c + serial.c 0 0 - 1 + 3 9 1 0 0 0 - ..\..\..\src\mempool.c - mempool.c + ..\..\..\components\drivers\src\completion.c + completion.c 0 0 - 1 + 3 10 1 0 0 0 - ..\..\..\src\object.c - object.c + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c 0 0 - 1 + 3 11 1 0 0 0 - ..\..\..\src\scheduler.c - scheduler.c + ..\..\..\components\drivers\src\pipe.c + pipe.c 0 0 - 1 + 3 12 1 0 0 0 - ..\..\..\src\signal.c - signal.c + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c 0 0 - 1 + 3 13 1 0 0 0 - ..\..\..\src\thread.c - thread.c + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c 0 0 - 1 + 3 14 1 0 0 0 - ..\..\..\src\timer.c - timer.c + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c 0 0 - Applications - 0 + Drivers + 1 0 0 0 - 2 - 15 + 4 + 16 1 0 0 0 - applications\application.c - application.c + board\board.c + board.c 0 0 - 2 - 16 + 4 + 17 1 0 0 0 - applications\ble_nus_app.c - ble_nus_app.c + ..\libraries\drivers\drv_uart.c + drv_uart.c 0 0 - 2 - 17 + 4 + 18 1 0 0 0 - applications\startup.c - startup.c + ..\libraries\drivers\drv_gpio.c + drv_gpio.c 0 0 - Drivers + finsh 1 0 0 0 - 3 - 18 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 + 5 19 1 0 0 0 - ..\libraries\drivers\drv_uart.c - drv_uart.c + ..\..\..\components\finsh\shell.c + shell.c 0 0 - - - - BLE_STACK - 1 - 0 - 0 - 0 - 4 + 5 20 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\common\ble_advdata.c - ble_advdata.c + ..\..\..\components\finsh\cmd.c + cmd.c 0 0 - 4 + 5 21 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\common\ble_conn_params.c - ble_conn_params.c + ..\..\..\components\finsh\msh.c + msh.c 0 0 + + + + Kernel + 1 + 0 + 0 + 0 - 4 + 6 22 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\common\ble_conn_state.c - ble_conn_state.c + ..\..\..\src\clock.c + clock.c 0 0 - 4 + 6 23 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\common\ble_srv_common.c - ble_srv_common.c + ..\..\..\src\components.c + components.c 0 0 - 4 + 6 24 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\nrf_ble_gatt\nrf_ble_gatt.c - nrf_ble_gatt.c + ..\..\..\src\device.c + device.c 0 0 - 4 + 6 25 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\ble_services\ble_nus\ble_nus.c - ble_nus.c + ..\..\..\src\idle.c + idle.c 0 0 - 4 + 6 26 1 0 0 0 - packages\Nordic_sdk-latest\components\ble\ble_advertising\ble_advertising.c - ble_advertising.c + ..\..\..\src\ipc.c + ipc.c 0 0 - 4 + 6 27 1 0 0 0 - packages\Nordic_sdk-latest\components\softdevice\common\softdevice_handler\softdevice_handler.c - softdevice_handler.c + ..\..\..\src\irq.c + irq.c 0 0 - - - - NRF_DRIVERS - 1 - 0 - 0 - 0 - 5 + 6 28 1 0 0 0 - packages\Nordic_sdk-latest\components\drivers_nrf\hal\nrf_saadc.c - nrf_saadc.c + ..\..\..\src\kservice.c + kservice.c 0 0 - 5 + 6 29 1 0 0 0 - packages\Nordic_sdk-latest\components\drivers_nrf\common\nrf_drv_common.c - nrf_drv_common.c + ..\..\..\src\mem.c + mem.c 0 0 - 5 + 6 30 1 0 0 0 - packages\Nordic_sdk-latest\components\drivers_nrf\clock\nrf_drv_clock.c - nrf_drv_clock.c + ..\..\..\src\mempool.c + mempool.c 0 0 - 5 + 6 31 1 0 0 0 - packages\Nordic_sdk-latest\components\drivers_nrf\gpiote\nrf_drv_gpiote.c - nrf_drv_gpiote.c + ..\..\..\src\object.c + object.c 0 0 - 5 + 6 32 1 0 0 0 - packages\Nordic_sdk-latest\components\drivers_nrf\pwm\nrf_drv_pwm.c - nrf_drv_pwm.c + ..\..\..\src\scheduler.c + scheduler.c 0 0 - 5 + 6 33 1 0 0 0 - packages\Nordic_sdk-latest\components\drivers_nrf\saadc\nrf_drv_saadc.c - nrf_drv_saadc.c + ..\..\..\src\signal.c + signal.c 0 0 - 5 + 6 34 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\log\src\nrf_log_backend_serial.c - nrf_log_backend_serial.c + ..\..\..\src\thread.c + thread.c 0 0 - 5 + 6 35 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\log\src\nrf_log_frontend.c - nrf_log_frontend.c + ..\..\..\src\timer.c + timer.c 0 0 + + + + libc + 1 + 0 + 0 + 0 - 5 + 7 36 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\timer\app_timer_rtthread.c - app_timer_rtthread.c + ..\..\..\components\libc\compilers\armlibc\libc.c + libc.c 0 0 - 5 + 7 37 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\util\app_error.c - app_error.c + ..\..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c 0 0 - 5 + 7 38 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\util\app_error_weak.c - app_error_weak.c + ..\..\..\components\libc\compilers\armlibc\stubs.c + stubs.c 0 0 - 5 + 7 39 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\util\app_util_platform.c - app_util_platform.c + ..\..\..\components\libc\compilers\common\time.c + time.c 0 0 + + + + nrfx + 1 + 0 + 0 + 0 - 5 + 8 40 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\util\nrf_assert.c - nrf_assert.c + packages\nrfx-v2.1.0\drivers\src\nrfx_adc.c + nrfx_adc.c 0 0 - 5 + 8 41 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\util\sdk_mapped_flags.c - sdk_mapped_flags.c + packages\nrfx-v2.1.0\drivers\src\nrfx_clock.c + nrfx_clock.c 0 0 - 5 + 8 42 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\fstorage\fstorage.c - fstorage.c + packages\nrfx-v2.1.0\drivers\src\nrfx_comp.c + nrfx_comp.c 0 0 - 5 + 8 43 1 0 0 0 - packages\Nordic_sdk-latest\components\libraries\strerror\nrf_strerror.c - nrf_strerror.c + packages\nrfx-v2.1.0\drivers\src\nrfx_dppi.c + nrfx_dppi.c 0 0 - 5 + 8 44 1 0 0 0 - packages\Nordic_sdk-latest\components\toolchain\system_nrf52.c - system_nrf52.c + packages\nrfx-v2.1.0\drivers\src\nrfx_egu.c + nrfx_egu.c 0 0 - 5 + 8 45 - 2 + 1 0 0 0 - packages\Nordic_sdk-latest\components\toolchain\arm\arm_startup_nrf52.s - arm_startup_nrf52.s + packages\nrfx-v2.1.0\drivers\src\nrfx_gpiote.c + nrfx_gpiote.c 0 0 - - - - cpu - 1 - 0 - 0 - 0 - 6 + 8 46 1 0 0 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c + packages\nrfx-v2.1.0\drivers\src\nrfx_i2s.c + nrfx_i2s.c 0 0 - 6 + 8 47 1 0 0 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c + packages\nrfx-v2.1.0\drivers\src\nrfx_ipc.c + nrfx_ipc.c 0 0 - 6 + 8 48 1 0 0 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c + packages\nrfx-v2.1.0\drivers\src\nrfx_lpcomp.c + nrfx_lpcomp.c 0 0 - 6 + 8 49 1 0 0 0 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c + packages\nrfx-v2.1.0\drivers\src\nrfx_nfct.c + nrfx_nfct.c 0 0 - 6 + 8 50 - 2 + 1 0 0 0 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S + packages\nrfx-v2.1.0\drivers\src\nrfx_nvmc.c + nrfx_nvmc.c 0 0 - - - - DeviceDrivers - 1 - 0 - 0 - 0 - 7 + 8 51 1 0 0 0 - ..\..\..\components\drivers\misc\pin.c - pin.c + packages\nrfx-v2.1.0\drivers\src\nrfx_pdm.c + nrfx_pdm.c 0 0 - 7 + 8 52 1 0 0 0 - ..\..\..\components\drivers\serial\serial.c - serial.c + packages\nrfx-v2.1.0\drivers\src\nrfx_power.c + nrfx_power.c 0 0 - 7 + 8 53 1 0 0 0 - ..\..\..\components\drivers\src\completion.c - completion.c + packages\nrfx-v2.1.0\drivers\src\nrfx_ppi.c + nrfx_ppi.c 0 0 - 7 + 8 54 1 0 0 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c + packages\nrfx-v2.1.0\drivers\src\nrfx_pwm.c + nrfx_pwm.c 0 0 - 7 + 8 55 1 0 0 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c + packages\nrfx-v2.1.0\drivers\src\nrfx_qdec.c + nrfx_qdec.c 0 0 - 7 + 8 56 1 0 0 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c + packages\nrfx-v2.1.0\drivers\src\nrfx_rng.c + nrfx_rng.c 0 0 - 7 + 8 57 1 0 0 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c + packages\nrfx-v2.1.0\drivers\src\nrfx_rtc.c + nrfx_rtc.c 0 0 - 7 + 8 58 1 0 0 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c + packages\nrfx-v2.1.0\drivers\src\nrfx_saadc.c + nrfx_saadc.c 0 0 - 7 + 8 59 1 0 0 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c + packages\nrfx-v2.1.0\drivers\src\nrfx_spi.c + nrfx_spi.c 0 0 - - - - finsh - 1 - 0 - 0 - 0 8 60 @@ -951,8 +951,8 @@ 0 0 0 - ..\..\..\components\finsh\shell.c - shell.c + packages\nrfx-v2.1.0\drivers\src\nrfx_spim.c + nrfx_spim.c 0 0 @@ -963,8 +963,8 @@ 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + packages\nrfx-v2.1.0\drivers\src\nrfx_spis.c + nrfx_spis.c 0 0 @@ -975,64 +975,164 @@ 0 0 0 - ..\..\..\components\finsh\msh.c - msh.c + packages\nrfx-v2.1.0\drivers\src\nrfx_systick.c + nrfx_systick.c 0 0 - - - - libc - 1 - 0 - 0 - 0 - 9 + 8 63 1 0 0 0 - ..\..\..\components\libc\compilers\armlibc\libc.c - libc.c + packages\nrfx-v2.1.0\drivers\src\nrfx_temp.c + nrfx_temp.c 0 0 - 9 + 8 64 1 0 0 0 - ..\..\..\components\libc\compilers\armlibc\mem_std.c - mem_std.c + packages\nrfx-v2.1.0\drivers\src\nrfx_timer.c + nrfx_timer.c 0 0 - 9 + 8 65 1 0 0 0 - ..\..\..\components\libc\compilers\armlibc\stubs.c - stubs.c + packages\nrfx-v2.1.0\drivers\src\nrfx_twi.c + nrfx_twi.c 0 0 - 9 + 8 66 1 0 0 0 - ..\..\..\components\libc\compilers\common\time.c - time.c + packages\nrfx-v2.1.0\drivers\src\nrfx_twi_twim.c + nrfx_twi_twim.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_twim.c + nrfx_twim.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_twis.c + nrfx_twis.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_uart.c + nrfx_uart.c + 0 + 0 + + + 8 + 70 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_uarte.c + nrfx_uarte.c + 0 + 0 + + + 8 + 71 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_usbd.c + nrfx_usbd.c + 0 + 0 + + + 8 + 72 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_usbreg.c + nrfx_usbreg.c + 0 + 0 + + + 8 + 73 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\drivers\src\nrfx_wdt.c + nrfx_wdt.c + 0 + 0 + + + 8 + 74 + 1 + 0 + 0 + 0 + packages\nrfx-v2.1.0\mdk\system_nrf52.c + system_nrf52.c + 0 + 0 + + + 8 + 75 + 2 + 0 + 0 + 0 + packages\nrfx-v2.1.0\mdk\arm_startup_nrf52.s + arm_startup_nrf52.s 0 0 diff --git a/bsp/nrf5x/nrf52832/project.uvprojx b/bsp/nrf5x/nrf52832/project.uvprojx index 5e217cca289978a47a5919185da1df55d712f180..b91c026743a09f667c58888203e11ef3b2781477 100644 --- a/bsp/nrf5x/nrf52832/project.uvprojx +++ b/bsp/nrf5x/nrf52832/project.uvprojx @@ -18,7 +18,7 @@ Nordic Semiconductor NordicSemiconductor.nRF_DeviceFamilyPack.8.27.1 http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ - IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x00010000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) @@ -274,8 +274,8 @@ 1 - 0x1f000 - 0x61000 + 0x0 + 0x80000 1 @@ -299,8 +299,8 @@ 0 - 0x200025f8 - 0xda08 + 0x20000000 + 0x10000 0 @@ -315,7 +315,7 @@ 1 0 0 - 1 + 0 0 0 0 @@ -336,9 +336,9 @@ 0 --reduce_paths - NRF52_PAN_55, NRF52_PAN_12, NRF52_PAN_15, NRF52_PAN_58, SWI_DISABLE0, SOFTDEVICE_PRESENT, NRF52_PAN_54, NRF52, BLE_STACK_SUPPORT_REQD, NRF52_PAN_51, NRF52_PAN_36, RTTHREAD, CONFIG_GPIO_AS_PINRESET, NRF52_PAN_64, NRF52_PAN_20, NRF52_PAN_74, NRF52832_XXAA, S132, NRF_SD_BLE_API_VERSION=4, NRF52_PAN_31, RT_USING_ARM_LIBC + USE_APP_CONFIG, NRF52832_XXAA, RT_USING_ARM_LIBC - .;..\..\..\include;applications;.;board;..\libraries\drivers;packages\Nordic_sdk-latest\components;packages\Nordic_sdk-latest\components\softdevice\common\softdevice_handler;packages\Nordic_sdk-latest\components\softdevice\s132\headers;packages\Nordic_sdk-latest\components\softdevice\s132\headers\nrf52;packages\Nordic_sdk-latest\components\ble\common;packages\Nordic_sdk-latest\components\ble\nrf_ble_gatt;packages\Nordic_sdk-latest\components\ble\ble_advertising;packages\Nordic_sdk-latest\components\ble\ble_services\ble_nus;packages\Nordic_sdk-latest\components;packages\Nordic_sdk-latest\components\device;packages\Nordic_sdk-latest\components\drivers_nrf\delay;packages\Nordic_sdk-latest\components\drivers_nrf\uart;packages\Nordic_sdk-latest\components\drivers_nrf\clock;packages\Nordic_sdk-latest\components\drivers_nrf\gpiote;packages\Nordic_sdk-latest\components\drivers_nrf\common;packages\Nordic_sdk-latest\components\drivers_nrf\hal;packages\Nordic_sdk-latest\components\drivers_nrf\pwm;packages\Nordic_sdk-latest\components\drivers_nrf\saadc;packages\Nordic_sdk-latest\components\libraries\util;packages\Nordic_sdk-latest\components\libraries\timer;packages\Nordic_sdk-latest\components\libraries\fstorage;packages\Nordic_sdk-latest\components\libraries\experimental_section_vars;packages\Nordic_sdk-latest\components\libraries\log;packages\Nordic_sdk-latest\components\libraries\log\src;packages\Nordic_sdk-latest\components\libraries\strerror;packages\Nordic_sdk-latest\components\toolchain\cmsis\include;packages\Nordic_sdk-latest\components\toolchain;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common + applications;.;..\libraries\cmsis\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;packages\nrfx-v2.1.0;packages\nrfx-v2.1.0\drivers;packages\nrfx-v2.1.0\drivers\include;packages\nrfx-v2.1.0\mdk;packages\nrfx-v2.1.0\hal @@ -354,7 +354,7 @@ 0 --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 - BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74 + @@ -380,377 +380,417 @@ - Kernel + Applications - clock.c + application.c 1 - ..\..\..\src\clock.c + applications\application.c + + + + cpu + - components.c + backtrace.c 1 - ..\..\..\src\components.c + ..\..\..\libcpu\arm\common\backtrace.c - device.c + div0.c 1 - ..\..\..\src\device.c + ..\..\..\libcpu\arm\common\div0.c - idle.c + showmem.c 1 - ..\..\..\src\idle.c + ..\..\..\libcpu\arm\common\showmem.c - ipc.c + cpuport.c 1 - ..\..\..\src\ipc.c + ..\..\..\libcpu\arm\cortex-m4\cpuport.c - irq.c + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c 1 - ..\..\..\src\irq.c + ..\..\..\components\drivers\misc\pin.c - kservice.c + serial.c 1 - ..\..\..\src\kservice.c + ..\..\..\components\drivers\serial\serial.c - mem.c + completion.c 1 - ..\..\..\src\mem.c + ..\..\..\components\drivers\src\completion.c - mempool.c + dataqueue.c 1 - ..\..\..\src\mempool.c + ..\..\..\components\drivers\src\dataqueue.c - object.c + pipe.c 1 - ..\..\..\src\object.c + ..\..\..\components\drivers\src\pipe.c - scheduler.c + ringblk_buf.c 1 - ..\..\..\src\scheduler.c + ..\..\..\components\drivers\src\ringblk_buf.c - signal.c + ringbuffer.c 1 - ..\..\..\src\signal.c + ..\..\..\components\drivers\src\ringbuffer.c - thread.c + waitqueue.c 1 - ..\..\..\src\thread.c + ..\..\..\components\drivers\src\waitqueue.c - timer.c + workqueue.c 1 - ..\..\..\src\timer.c + ..\..\..\components\drivers\src\workqueue.c - Applications + Drivers - application.c + board.c 1 - applications\application.c + board\board.c - ble_nus_app.c + drv_uart.c 1 - applications\ble_nus_app.c + ..\libraries\drivers\drv_uart.c - startup.c + drv_gpio.c 1 - applications\startup.c + ..\libraries\drivers\drv_gpio.c - Drivers + finsh - board.c + shell.c 1 - board\board.c + ..\..\..\components\finsh\shell.c - drv_uart.c + cmd.c 1 - ..\libraries\drivers\drv_uart.c + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c - BLE_STACK + Kernel - ble_advdata.c + clock.c 1 - packages\Nordic_sdk-latest\components\ble\common\ble_advdata.c + ..\..\..\src\clock.c - ble_conn_params.c + components.c 1 - packages\Nordic_sdk-latest\components\ble\common\ble_conn_params.c + ..\..\..\src\components.c - ble_conn_state.c + device.c 1 - packages\Nordic_sdk-latest\components\ble\common\ble_conn_state.c + ..\..\..\src\device.c - ble_srv_common.c + idle.c 1 - packages\Nordic_sdk-latest\components\ble\common\ble_srv_common.c + ..\..\..\src\idle.c - nrf_ble_gatt.c + ipc.c 1 - packages\Nordic_sdk-latest\components\ble\nrf_ble_gatt\nrf_ble_gatt.c + ..\..\..\src\ipc.c - ble_nus.c + irq.c 1 - packages\Nordic_sdk-latest\components\ble\ble_services\ble_nus\ble_nus.c + ..\..\..\src\irq.c - ble_advertising.c + kservice.c 1 - packages\Nordic_sdk-latest\components\ble\ble_advertising\ble_advertising.c + ..\..\..\src\kservice.c - softdevice_handler.c + mem.c 1 - packages\Nordic_sdk-latest\components\softdevice\common\softdevice_handler\softdevice_handler.c + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c - NRF_DRIVERS + libc - nrf_saadc.c + libc.c 1 - packages\Nordic_sdk-latest\components\drivers_nrf\hal\nrf_saadc.c + ..\..\..\components\libc\compilers\armlibc\libc.c - nrf_drv_common.c + mem_std.c 1 - packages\Nordic_sdk-latest\components\drivers_nrf\common\nrf_drv_common.c + ..\..\..\components\libc\compilers\armlibc\mem_std.c - nrf_drv_clock.c + stubs.c 1 - packages\Nordic_sdk-latest\components\drivers_nrf\clock\nrf_drv_clock.c + ..\..\..\components\libc\compilers\armlibc\stubs.c - nrf_drv_gpiote.c + time.c 1 - packages\Nordic_sdk-latest\components\drivers_nrf\gpiote\nrf_drv_gpiote.c + ..\..\..\components\libc\compilers\common\time.c + + + + nrfx + - nrf_drv_pwm.c + nrfx_adc.c 1 - packages\Nordic_sdk-latest\components\drivers_nrf\pwm\nrf_drv_pwm.c + packages\nrfx-v2.1.0\drivers\src\nrfx_adc.c - nrf_drv_saadc.c + nrfx_clock.c 1 - packages\Nordic_sdk-latest\components\drivers_nrf\saadc\nrf_drv_saadc.c + packages\nrfx-v2.1.0\drivers\src\nrfx_clock.c - nrf_log_backend_serial.c + nrfx_comp.c 1 - packages\Nordic_sdk-latest\components\libraries\log\src\nrf_log_backend_serial.c + packages\nrfx-v2.1.0\drivers\src\nrfx_comp.c - nrf_log_frontend.c + nrfx_dppi.c 1 - packages\Nordic_sdk-latest\components\libraries\log\src\nrf_log_frontend.c + packages\nrfx-v2.1.0\drivers\src\nrfx_dppi.c - app_timer_rtthread.c + nrfx_egu.c 1 - packages\Nordic_sdk-latest\components\libraries\timer\app_timer_rtthread.c + packages\nrfx-v2.1.0\drivers\src\nrfx_egu.c - app_error.c + nrfx_gpiote.c 1 - packages\Nordic_sdk-latest\components\libraries\util\app_error.c + packages\nrfx-v2.1.0\drivers\src\nrfx_gpiote.c - app_error_weak.c + nrfx_i2s.c 1 - packages\Nordic_sdk-latest\components\libraries\util\app_error_weak.c + packages\nrfx-v2.1.0\drivers\src\nrfx_i2s.c - app_util_platform.c + nrfx_ipc.c 1 - packages\Nordic_sdk-latest\components\libraries\util\app_util_platform.c + packages\nrfx-v2.1.0\drivers\src\nrfx_ipc.c - nrf_assert.c + nrfx_lpcomp.c 1 - packages\Nordic_sdk-latest\components\libraries\util\nrf_assert.c + packages\nrfx-v2.1.0\drivers\src\nrfx_lpcomp.c - sdk_mapped_flags.c + nrfx_nfct.c 1 - packages\Nordic_sdk-latest\components\libraries\util\sdk_mapped_flags.c + packages\nrfx-v2.1.0\drivers\src\nrfx_nfct.c - fstorage.c + nrfx_nvmc.c 1 - packages\Nordic_sdk-latest\components\libraries\fstorage\fstorage.c + packages\nrfx-v2.1.0\drivers\src\nrfx_nvmc.c - nrf_strerror.c + nrfx_pdm.c 1 - packages\Nordic_sdk-latest\components\libraries\strerror\nrf_strerror.c + packages\nrfx-v2.1.0\drivers\src\nrfx_pdm.c - system_nrf52.c + nrfx_power.c 1 - packages\Nordic_sdk-latest\components\toolchain\system_nrf52.c + packages\nrfx-v2.1.0\drivers\src\nrfx_power.c - arm_startup_nrf52.s - 2 - packages\Nordic_sdk-latest\components\toolchain\arm\arm_startup_nrf52.s + nrfx_ppi.c + 1 + packages\nrfx-v2.1.0\drivers\src\nrfx_ppi.c - - - - cpu - - backtrace.c + nrfx_pwm.c 1 - ..\..\..\libcpu\arm\common\backtrace.c + packages\nrfx-v2.1.0\drivers\src\nrfx_pwm.c - div0.c + nrfx_qdec.c 1 - ..\..\..\libcpu\arm\common\div0.c + packages\nrfx-v2.1.0\drivers\src\nrfx_qdec.c - showmem.c + nrfx_rng.c 1 - ..\..\..\libcpu\arm\common\showmem.c + packages\nrfx-v2.1.0\drivers\src\nrfx_rng.c - cpuport.c + nrfx_rtc.c 1 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c + packages\nrfx-v2.1.0\drivers\src\nrfx_rtc.c - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + nrfx_saadc.c + 1 + packages\nrfx-v2.1.0\drivers\src\nrfx_saadc.c - - - - DeviceDrivers - - pin.c + nrfx_spi.c 1 - ..\..\..\components\drivers\misc\pin.c + packages\nrfx-v2.1.0\drivers\src\nrfx_spi.c - serial.c + nrfx_spim.c 1 - ..\..\..\components\drivers\serial\serial.c + packages\nrfx-v2.1.0\drivers\src\nrfx_spim.c - completion.c + nrfx_spis.c 1 - ..\..\..\components\drivers\src\completion.c + packages\nrfx-v2.1.0\drivers\src\nrfx_spis.c - dataqueue.c + nrfx_systick.c 1 - ..\..\..\components\drivers\src\dataqueue.c + packages\nrfx-v2.1.0\drivers\src\nrfx_systick.c - pipe.c + nrfx_temp.c 1 - ..\..\..\components\drivers\src\pipe.c + packages\nrfx-v2.1.0\drivers\src\nrfx_temp.c - ringblk_buf.c + nrfx_timer.c 1 - ..\..\..\components\drivers\src\ringblk_buf.c + packages\nrfx-v2.1.0\drivers\src\nrfx_timer.c - ringbuffer.c + nrfx_twi.c 1 - ..\..\..\components\drivers\src\ringbuffer.c + packages\nrfx-v2.1.0\drivers\src\nrfx_twi.c - waitqueue.c + nrfx_twi_twim.c 1 - ..\..\..\components\drivers\src\waitqueue.c + packages\nrfx-v2.1.0\drivers\src\nrfx_twi_twim.c - workqueue.c + nrfx_twim.c 1 - ..\..\..\components\drivers\src\workqueue.c + packages\nrfx-v2.1.0\drivers\src\nrfx_twim.c - - - - finsh - - shell.c + nrfx_twis.c 1 - ..\..\..\components\finsh\shell.c + packages\nrfx-v2.1.0\drivers\src\nrfx_twis.c - cmd.c + nrfx_uart.c 1 - ..\..\..\components\finsh\cmd.c + packages\nrfx-v2.1.0\drivers\src\nrfx_uart.c - msh.c + nrfx_uarte.c 1 - ..\..\..\components\finsh\msh.c + packages\nrfx-v2.1.0\drivers\src\nrfx_uarte.c - - - - libc - - libc.c + nrfx_usbd.c 1 - ..\..\..\components\libc\compilers\armlibc\libc.c + packages\nrfx-v2.1.0\drivers\src\nrfx_usbd.c - mem_std.c + nrfx_usbreg.c 1 - ..\..\..\components\libc\compilers\armlibc\mem_std.c + packages\nrfx-v2.1.0\drivers\src\nrfx_usbreg.c - stubs.c + nrfx_wdt.c 1 - ..\..\..\components\libc\compilers\armlibc\stubs.c + packages\nrfx-v2.1.0\drivers\src\nrfx_wdt.c - time.c + system_nrf52.c 1 - ..\..\..\components\libc\compilers\common\time.c + packages\nrfx-v2.1.0\mdk\system_nrf52.c + + + arm_startup_nrf52.s + 2 + packages\nrfx-v2.1.0\mdk\arm_startup_nrf52.s diff --git a/bsp/nrf5x/nrf52832/rtconfig.h b/bsp/nrf5x/nrf52832/rtconfig.h index cce968f75b19a62df24c8d579ff12fad1605bb33..a42405872e986d375578057bc486c64a29f3e323 100644 --- a/bsp/nrf5x/nrf52832/rtconfig.h +++ b/bsp/nrf5x/nrf52832/rtconfig.h @@ -46,6 +46,9 @@ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ @@ -74,7 +77,6 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -138,6 +140,8 @@ /* peripheral libraries and drivers */ +#define PKG_USING_NRFX +#define PKG_USING_NRFX_V210 /* miscellaneous packages */ @@ -148,11 +152,25 @@ /* Hardware Drivers Config */ #define SOC_NRF52832 +#define SOC_NORDIC /* Onboard Peripheral Drivers */ + /* On-chip Peripheral Drivers */ +#define BSP_USING_GPIO #define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_PIN 8 +#define BSP_UART0_TX_PIN 6 + +/* On-chip flash config */ + +#define MCU_FLASH_START_ADDRESS 0x00000000 +#define MCU_FLASH_SIZE_KB 1024 +#define MCU_SRAM_START_ADDRESS 0x20000000 +#define MCU_SRAM_SIZE_KB 256 +#define MCU_FLASH_PAGE_SIZE 0x1000 #endif diff --git a/bsp/nrf5x/nrf52832/template.uvoptx b/bsp/nrf5x/nrf52832/template.uvoptx index 7bd9338b2b8b19c723a277c105ee05a750c5b983..082de4487b95d1b91a83f11c977f49fea6afd7db 100644 --- a/bsp/nrf5x/nrf52832/template.uvoptx +++ b/bsp/nrf5x/nrf52832/template.uvoptx @@ -120,12 +120,12 @@ 0 JL2CM3 - -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm) + -U682327541 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm) 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm) diff --git a/bsp/nrf5x/nrf52832/template.uvprojx b/bsp/nrf5x/nrf52832/template.uvprojx index 0bf64c89f2adcaf70a3124d358771a47c5134d4c..887cfb552e91af47c0b7af3ad84c74ebaccdb22f 100644 --- a/bsp/nrf5x/nrf52832/template.uvprojx +++ b/bsp/nrf5x/nrf52832/template.uvprojx @@ -16,9 +16,9 @@ nRF52832_xxAA Nordic Semiconductor - NordicSemiconductor.nRF_DeviceFamilyPack.8.24.1 + NordicSemiconductor.nRF_DeviceFamilyPack.8.27.1 http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/ - IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x00010000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)) @@ -274,8 +274,8 @@ 1 - 0x1f000 - 0x61000 + 0x0 + 0x80000 1 @@ -299,8 +299,8 @@ 0 - 0x200025f8 - 0xda08 + 0x20000000 + 0x10000 0 @@ -315,7 +315,7 @@ 1 0 0 - 1 + 0 0 0 0 @@ -336,7 +336,7 @@ 0 --reduce_paths - BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74 + @@ -354,7 +354,7 @@ 0 --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74 - BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74 + diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index 9f95a9177e36f0838879cf658ff4a0d57ff61b4b..1bf97f6e4dce7561278d70b86a9285547b4229a5 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -7,6 +7,12 @@ config SOC_NRF52840 select RT_USING_USER_MAIN default y +config SOC_NORDIC + bool + config SOC_NORDIC + default y + + menu "Onboard Peripheral Drivers" config BSP_USING_JLINK_TO_USART bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)" @@ -55,38 +61,142 @@ menu "On-chip Peripheral Drivers" bool "Enable GPIO" select RT_USING_PIN default y + menuconfig BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default n + if BSP_USING_PWM + config NRFX_PWM_ENABLED + int + default 1 + config BSP_USING_PWM0 + bool "Enable PWM0 bus" + default y + if BSP_USING_PWM0 + config NRFX_PWM0_ENABLED + int + default 1 + config BSP_USING_PWM0_CH0 + int "PWM0 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM0_CH1 + int "PWM0 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM0_CH2 + int "PWM0 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM0_CH3 + int "PWM0 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM1 + bool "Enable PWM1 bus" + default n + if BSP_USING_PWM1 + config NRFX_PWM1_ENABLED + int + default 1 + config BSP_USING_PWM1_CH0 + int "PWM1 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM1_CH1 + int "PWM1 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM1_CH2 + int "PWM1 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM1_CH3 + int "PWM1 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM2 + bool "Enable PWM2 bus" + default n + if BSP_USING_PWM2 + config NRFX_PWM2_ENABLED + int + default 1 + config BSP_USING_PWM2_CH0 + int "PWM2 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM2_CH1 + int "PWM2 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM2_CH2 + int "PWM2 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM2_CH3 + int "PWM2 channel 3 pin number set" + range 0 47 + default 16 + endif + config BSP_USING_PWM3 + bool "Enable PWM3 bus" + default n + if BSP_USING_PWM3 + config NRFX_PWM3_ENABLED + int + default 1 + config BSP_USING_PWM3_CH0 + int "PWM3 channel 0 pin number set" + range 0 47 + default 13 + config BSP_USING_PWM3_CH1 + int "PWM3 channel 1 pin number set" + range 0 47 + default 14 + config BSP_USING_PWM3_CH2 + int "PWM3 channel 2 pin number set" + range 0 47 + default 15 + config BSP_USING_PWM3_CH3 + int "PWM3 channel 3 pin number set" + range 0 47 + default 16 + endif + endif menuconfig BSP_USING_SOFTDEVICE bool "Enable NRF SOFTDEVICE" select PKG_USING_NRF5X_SDK + select NRFX_CLOCK_ENABLED default n if BSP_USING_SOFTDEVICE config NRFX_CLOCK_ENABLED - int "NRFX_CLOCK_ENABLED" + int default 1 - config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - int "NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY" + config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY + int default 7 - config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - int "NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY" - default 7 - config NRFX_RTC_ENABLED - int "NRFX_RTC_ENABLED" + config NRFX_RTC_ENABLED + int + default 1 + config NRFX_RTC1_ENABLED + int default 1 - config NRF_CLOCK_ENABLED - int "NRF_CLOCK_ENABLED" + config NRF_CLOCK_ENABLED + int default 1 - config NRF_SDH_BLE_ENABLED - int "NRF_SDH_BLE_ENABLED" + config NRF_SDH_BLE_ENABLED + int default 1 - config NRF_SDH_ENABLED - int "NRF_SDH_ENABLED" + config NRF_SDH_ENABLED + int default 1 - config NRF_SDH_SOC_ENABLED - int "NRF_SDH_SOC_ENABLED" + config NRF_SDH_SOC_ENABLED + int default 1 - endif - menuconfig BSP_USING_UART bool "Enable UART" default y diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h index c9bd0ef39bcfe92a4c5a05e6b739b3f942dfc5f3..c19021fed956a6ab75721074b761bb43f6a2830d 100644 --- a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h @@ -433,11 +433,12 @@ extern "C" u32ModuleNum,\ u32Condition,\ u16CMPData,\ - u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ (u32Condition) |\ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ - EADC_CMP_ADCMPEN_Msk)) + EADC_CMP_ADCMPEN_Msk))) /** * @brief Configure the comparator 1 and enable it. @@ -458,11 +459,12 @@ extern "C" u32ModuleNum,\ u32Condition,\ u16CMPData,\ - u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ (u32Condition) |\ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ - EADC_CMP_ADCMPEN_Msk)) + EADC_CMP_ADCMPEN_Msk))) /** * @brief Configure the comparator 2 and enable it. @@ -483,11 +485,12 @@ extern "C" u32ModuleNum,\ u32Condition,\ u16CMPData,\ - u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ (u32Condition) |\ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ - EADC_CMP_ADCMPEN_Msk)) + EADC_CMP_ADCMPEN_Msk))) /** * @brief Configure the comparator 3 and enable it. @@ -508,11 +511,12 @@ extern "C" u32ModuleNum,\ u32Condition,\ u16CMPData,\ - u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ (u32Condition) |\ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ - EADC_CMP_ADCMPEN_Msk)) + EADC_CMP_ADCMPEN_Msk))) /** * @brief Enable the compare window mode. diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h index 64114525e1e151a1798cb89a34120a24cd87ca0d..10b52c030f7696a9567b798d2635e92886757c5e 100644 --- a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h @@ -95,6 +95,15 @@ extern "C" */ #define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk)) + /** * @brief Disable RX PDMA transfer. * @param[in] qspi The pointer of the specified QSPI module. @@ -113,6 +122,15 @@ extern "C" */ #define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + /** * @brief Get the count of available data in RX FIFO. * @param[in] qspi The pointer of the specified QSPI module. diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h index 77eeda3b96c5fce1de1779d17ad48da0fada8978..4a1e23ec4334aec88c425723fb029dee4d5573f5 100644 --- a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h @@ -133,6 +133,15 @@ extern "C" */ #define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk) +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk)) + /** * @brief Disable RX PDMA transfer. * @param[in] spi The pointer of the specified SPI module. @@ -151,6 +160,15 @@ extern "C" */ #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + /** * @brief Get the count of available data in RX FIFO. * @param[in] spi The pointer of the specified SPI module. diff --git a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h index 68d4e02a897b5f66f07a0b80a1c2c42958f79a01..002076027ee155e3333eb48181272280f5472d4b 100644 --- a/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h +++ b/bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h @@ -361,6 +361,15 @@ extern "C" */ #define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + /** * @brief Disable RX PDMA transfer. * @param[in] uspi The pointer of the specified USCI_SPI module. @@ -379,6 +388,15 @@ extern "C" */ #define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk)) + uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); void USPI_Close(USPI_T *uspi); void USPI_ClearRxBuf(USPI_T *uspi); diff --git a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig index 262776534d3d6a067fecd09704fd56b451fe7726..2e5fd7a81b185d847ac66f84617c02e78010e5b8 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig @@ -57,7 +57,7 @@ config SOC_SERIES_M480 select RT_USING_NETDEV config NU_EMAC_PDMA_MEMCOPY - bool "Use PDMA for data tranferring" + bool "Use PDMA for data transferring" select BSP_USING_PDMA depends on BSP_USING_EMAC default y @@ -82,14 +82,15 @@ config SOC_SERIES_M480 menuconfig BSP_USING_EADC bool "Enable Enhanced Analog-to-Digital Converter(EADC)" + select RT_USING_ADC - config BSP_USING_EADC0 - bool "Enable EADC0" - depends on BSP_USING_EADC && RT_USING_ADC + if BSP_USING_EADC + config BSP_USING_EADC0 + bool "Enable EADC0" - config BSP_USING_EADC1 - bool "Enable EADC1" - depends on BSP_USING_EADC && RT_USING_ADC + config BSP_USING_EADC1 + bool "Enable EADC1" + endif menuconfig BSP_USING_TMR bool "Enable Timer Controller(TIMER)" @@ -371,12 +372,14 @@ config SOC_SERIES_M480 config BSP_USING_UI2C0 select RT_USING_I2C + select BSP_USING_UI2C bool "UI2C0" help Choose this option if you need I2C function mode. config BSP_USING_USPI0 select RT_USING_SPI + select BSP_USING_USPI bool "USPI0" help Choose this option if you need SPI function mode. @@ -391,7 +394,7 @@ config SOC_SERIES_M480 depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA config BSP_USING_USPI0_PDMA - bool "Use PDMA for data tranferring" + bool "Use PDMA for data transferring" select BSP_USING_USPI_PDMA depends on BSP_USING_USPI0 endif @@ -405,21 +408,21 @@ config SOC_SERIES_M480 config BSP_USING_UUART1 select RT_USING_SERIAL - select BSP_USING_UUART + select BSP_USING_UUART bool "UUART1" help Choose this option if you need UART function mode. config BSP_USING_UI2C1 select RT_USING_I2C - select BSP_USING_UI2C + select BSP_USING_UI2C bool "UI2C1" help Choose this option if you need I2C function mode. config BSP_USING_USPI1 select RT_USING_SPI - select BSP_USING_USPI + select BSP_USING_USPI bool "USPI1" help Choose this option if you need SPI function mode. @@ -434,7 +437,7 @@ config SOC_SERIES_M480 depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA config BSP_USING_USPI1_PDMA - bool "Use PDMA for data tranferring" + bool "Use PDMA for data transferring" select BSP_USING_USPI_PDMA depends on BSP_USING_USPI1 endif @@ -459,6 +462,10 @@ config SOC_SERIES_M480 config NU_SDH_HOTPLUG bool "Using HOTPLUG" default y + + config NU_SDH_MOUNT_ON_ROOT + bool "Mount on root" + endif menuconfig BSP_USING_CAN @@ -652,7 +659,7 @@ config SOC_SERIES_M480 select BSP_USING_SPI_PDMA depends on BSP_USING_SPI1 endif - + choice prompt "Select SPI2 function mode" config BSP_USING_SPI2_NONE @@ -686,7 +693,7 @@ config SOC_SERIES_M480 bool "NONE" help Choose this option if you need not SPI3. - + config BSP_USING_SPI3 bool "Enable SPI3" help @@ -724,20 +731,23 @@ config SOC_SERIES_M480 bool "Enable Quad Serial Peripheral Interface(QSPI)" select RT_USING_SPI select RT_USING_QSPI + select BSP_USING_SPI - if BSP_USING_QSPI + if BSP_USING_QSPI config BSP_USING_QSPI0 bool "Enable QSPI0" config BSP_USING_QSPI0_PDMA bool "Enable PDMA for QSPI0" + select BSP_USING_SPI_PDMA depends on BSP_USING_QSPI0 config BSP_USING_QSPI1 bool "Enable QSPI1" config BSP_USING_QSPI1_PDMA - bool "Enable PDMA for QSPI1" + bool "Enable PDMA for QSPI1" + select BSP_USING_SPI_PDMA depends on BSP_USING_QSPI1 endif @@ -857,7 +867,7 @@ config SOC_SERIES_M480 if BSP_USING_CRC config NU_CRC_USE_PDMA - bool "Use PDMA for data tranferring." + bool "Use PDMA for data transferring." select BSP_USING_PDMA default y endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c index f9cc4a973838072bc012772c82c3f06980dd4ffe..a0fd7d37fabdc1ed3774a1387cccffb0fc777a70 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c @@ -97,7 +97,7 @@ static struct nu_can nu_can_arr[] = }, #endif {0} -}; /* usart nu_usart */ +}; /* struct nu_can */ /* Public functions ------------------------------------------------------------*/ @@ -112,7 +112,7 @@ static const struct rt_can_ops nu_can_ops = static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT; -/* Interrupt Handle Funtion ----------------------------------------------------*/ +/* Interrupt Handle Function ----------------------------------------------------*/ #if defined(BSP_USING_CAN0) /* CAN0 interrupt entry */ void CAN0_IRQHandler(void) @@ -238,7 +238,7 @@ static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure RT_ASSERT(can != RT_NULL); RT_ASSERT(cfg != RT_NULL); - /* Get base address of uart register */ + /* Get base address of CAN register */ CAN_T *can_base = ((nu_can_t)can)->can_base; RT_ASSERT(can_base != RT_NULL); @@ -312,7 +312,7 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg) #ifdef RT_CAN_USING_HDR struct rt_can_filter_config *filter_cfg; #endif - /* Get base address of uart register */ + /* Get base address of CAN register */ CAN_T *can_base = ((nu_can_t)can)->can_base; RT_ASSERT(can_base != RT_NULL); @@ -346,7 +346,6 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg) { /* Enable Status Change Interrupt */ CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk); - NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2); /* Enable NVIC interrupt. */ NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n); @@ -355,7 +354,6 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg) { /* Enable Error Status and Status Change Interrupt */ CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); - NVIC_SetPriority(((nu_can_t)can)->can_irq_n, (1 << __NVIC_PRIO_BITS) - 2); /* Enable NVIC interrupt. */ NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n); } @@ -440,6 +438,9 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg) rt_memcpy(arg, &can->status, sizeof(can->status)); } break; + default: + return -(RT_EINVAL); + } return RT_EOK; @@ -449,7 +450,7 @@ static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_ { STR_CANMSG_T tMsg; struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; - /* Get base address of uart register */ + /* Get base address of CAN register */ CAN_T *can_base = ((nu_can_t)can)->can_base; RT_ASSERT(can_base != RT_NULL); @@ -495,7 +496,7 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn { STR_CANMSG_T tMsg; struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; - /* Get base address of uart register */ + /* Get base address of CAN register */ CAN_T *can_base = ((nu_can_t)can)->can_base; RT_ASSERT(can_base != RT_NULL); @@ -558,7 +559,7 @@ static int rt_hw_can_init(void) RT_ASSERT(ret == RT_EOK); } - return ret; + return (int)ret; } INIT_DEVICE_EXPORT(rt_hw_can_init); #endif //#if defined(BSP_USING_CAN) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c index 9ed0233bb2f65fe88917f70a25a8e1e8576f11ec..abbefbeebe23e75e0afdb07513d9b6557961b287 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c @@ -165,8 +165,8 @@ static void pm_run(struct rt_pm *pm, rt_uint8_t mode) SYS_UnlockReg(); - /* Switch run mdoe frequency using PLL + HXT if HXT is enabled. - Otherwise, the systme clock will use PLL + HIRC. */ + /* Switch run mode frequency using PLL + HXT if HXT is enabled. + Otherwise, the system clock will use PLL + HIRC. */ switch (mode) { case PM_RUN_MODE_HIGH_SPEED: @@ -209,7 +209,7 @@ static void hw_timer_init(void) CLK_EnableModuleClock(PM_TIMER_MODULE); SYS_LockReg(); - /* Initialise timer and enable wakeup function. */ + /* Initialize timer and enable wakeup function. */ TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1); TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0); TIMER_EnableInt(PM_TIMER); @@ -262,7 +262,7 @@ static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) if (timeout == RT_TICK_MAX) return; - /* start pm timer to compenstate the os tick in power down mode */ + /* start pm timer to compensate the os tick in power down mode */ tick = pm_tick_from_os_tick(timeout); TIMER_SET_CMP_VALUE(PM_TIMER, tick); TIMER_Start(PM_TIMER); @@ -277,7 +277,7 @@ static void pm_timer_stop(struct rt_pm *pm) } -/* pm device driver initialise. */ +/* pm device driver initialize. */ int rt_hw_pm_init(void) { rt_uint8_t timer_mask; diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c index 79e66dbac0d7f7d5f322cf75e411c5f5d2c94342..e0e3b5f56b2894c94988c614ceb271bf9a8c0b04 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.c @@ -21,9 +21,9 @@ #endif /* Private define ---------------------------------------------------------------*/ -#define NU_GETBYTE_OFST(addr) ((addr&0x3)*8) -#define NU_GET_WALIGN(addr) (addr&~0x3) -#define NU_GET_LSB2BIT(addr) (addr&0x3) +#define NU_GETBYTE_OFST(addr) (((addr)&0x3)*8) +#define NU_GET_WALIGN(addr) ((addr)&~0x3) +#define NU_GET_LSB2BIT(addr) ((addr)&0x3) /* Private typedef --------------------------------------------------------------*/ /* Private functions ------------------------------------------------------------*/ @@ -159,7 +159,8 @@ int nu_fmc_erase(long addr, size_t size) uint32_t addr_end = addr + size; #if defined(NU_SUPPORT_NONALIGN) - uint8_t *page_sdtemp = RT_NULL, *page_edtemp = RT_NULL; + uint8_t *page_sdtemp = RT_NULL; + uint8_t *page_edtemp = RT_NULL; addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1); @@ -315,7 +316,7 @@ static int nu_fmc_init(void) g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO); - return RT_EOK; + return (int)RT_EOK; } INIT_APP_EXPORT(nu_fmc_init); diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c index 4790d6500142bf7b629217dcc146d042352ddc3d..47c26136a26813f9936bf55e4586e3dda3de68cf 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c @@ -166,7 +166,7 @@ static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_ if ((irqindex = nu_find_irqindex(pin)) >= 0) goto exit_nu_gpio_attach_irq; - // Find avaiable index of pin in pool. + // Find available index of pin in pool. if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones ==> Find First Zero goto exit_nu_gpio_attach_irq; diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h index c353a1e772551080bf1f0776f3c552bac9c7a773..6b831467a8f597294343ea4f234916e3a6149706 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.h @@ -26,7 +26,7 @@ typedef enum NU_PORT_CNT, } nu_gpio_port; -#define NU_GET_PININDEX(port, pin) (port*16+pin) +#define NU_GET_PININDEX(port, pin) ((port)*16+(pin)) #define NU_GET_PINS(rt_pin_index) ((rt_pin_index) & 0x0000000F) #define NU_GET_PORT(rt_pin_index) (((rt_pin_index)>>4) & 0x0000000F) #define NU_GET_PIN_MASK(nu_gpio_pin) (1 << (nu_gpio_pin)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c index 35b73832103a7dec8953ee75e1ab7048564d15c5..d76cb27314f3e3b9523fbb3fd039254dc1d32939 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c @@ -306,6 +306,10 @@ static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_ca } // switch (caps->sub_type) break; + default: + result = -RT_ERROR; + break; + } // switch (caps->main_type) return result; @@ -449,6 +453,9 @@ static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream) LOG_I("Start record."); } break; + + default: + return -RT_ERROR; } return RT_EOK; diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c index a39e0716392a22b1e707bbc06741c4495f28b4df..4d99dba711b45690a4011aca70a3ed304a9549fc 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_qspi.c @@ -12,6 +12,14 @@ #include #if defined(BSP_USING_QSPI) + +#define LOG_TAG "drv.qspi" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + #include #include @@ -87,8 +95,8 @@ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { struct nu_spi *spi_bus; - uint32_t u32SPIMode; - uint32_t u32BusClock; + rt_uint32_t u32SPIMode; + rt_uint32_t u32BusClock; rt_err_t ret = RT_EOK; RT_ASSERT(device != RT_NULL); @@ -130,7 +138,7 @@ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); if (configuration->max_hz > u32BusClock) { - rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); + LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); configuration->max_hz = u32BusClock; } @@ -173,7 +181,7 @@ exit_nu_qspi_bus_configure: } #if defined(RT_SFUD_USING_QSPI) -static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx, int qspi_lines) +static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines) { QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; if (qspi_lines > 1) @@ -188,6 +196,9 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx case 4: QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base); break; + default: + LOG_E("Data line is not supported.\n"); + break; } } else @@ -200,6 +211,9 @@ static int nu_qspi_mode_config(struct nu_spi *qspi_bus, uint8_t *tx, uint8_t *rx case 4: QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base); break; + default: + LOG_E("Data line is not supported.\n"); + break; } } } @@ -218,11 +232,11 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_ struct rt_qspi_configuration *qspi_configuration; #if defined(RT_SFUD_USING_QSPI) struct rt_qspi_message *qspi_message; - int last = 1; + rt_uint8_t u8last = 1; #endif - uint8_t bytes_per_word; + rt_uint8_t bytes_per_word; QSPI_T *qspi_base; - int len = 0; + rt_uint32_t u32len = 0; RT_ASSERT(device != RT_NULL); RT_ASSERT(message != RT_NULL); @@ -252,9 +266,9 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_ /* Command stage */ if (qspi_message->instruction.content != 0) { - last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines); + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines); nu_spi_transfer((struct nu_spi *)qspi_bus, - (uint8_t *) &qspi_message->instruction.content, + (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, 1, 1); @@ -263,29 +277,29 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_ /* Address stage */ if (qspi_message->address.size != 0) { - uint32_t u32ReversedAddr = 0; - uint32_t u32AddrNumOfByte = qspi_message->address.size / 8; + rt_uint32_t u32ReversedAddr = 0; + rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8; switch (u32AddrNumOfByte) { case 1: u32ReversedAddr = (qspi_message->address.content & 0xff); break; case 2: - nu_set16_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content); + nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); break; case 3: - nu_set24_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content); + nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); break; case 4: - nu_set32_be((uint8_t *)&u32ReversedAddr, qspi_message->address.content); + nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); break; default: RT_ASSERT(0); break; } - last = nu_qspi_mode_config(qspi_bus, (uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines); + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines); nu_spi_transfer((struct nu_spi *)qspi_bus, - (uint8_t *) &u32ReversedAddr, + (rt_uint8_t *) &u32ReversedAddr, RT_NULL, u32AddrNumOfByte, 1); @@ -294,32 +308,32 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_ /* Dummy_cycles stage */ if (qspi_message->dummy_cycles != 0) { - qspi_bus->dummy = 0xff; + qspi_bus->dummy = 0x00; - last = nu_qspi_mode_config(qspi_bus, (uint8_t *) &qspi_bus->dummy, RT_NULL, last); + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_bus->dummy, RT_NULL, u8last); nu_spi_transfer((struct nu_spi *)qspi_bus, - (uint8_t *) &qspi_bus->dummy, + (rt_uint8_t *) &qspi_bus->dummy, RT_NULL, - qspi_message->dummy_cycles / (8 / last), + qspi_message->dummy_cycles / (8 / u8last), 1); } /* Data stage */ - nu_qspi_mode_config(qspi_bus, (uint8_t *) message->send_buf, (uint8_t *) message->recv_buf, qspi_message->qspi_data_lines); + nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines); #endif //#if defined(RT_SFUD_USING_QSPI) if (message->length != 0) { nu_spi_transfer((struct nu_spi *)qspi_bus, - (uint8_t *) message->send_buf, - (uint8_t *) message->recv_buf, + (rt_uint8_t *) message->send_buf, + (rt_uint8_t *) message->recv_buf, message->length, bytes_per_word); - len = message->length; + u32len = message->length; } else { - len = 1; + u32len = 1; } if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) @@ -334,12 +348,12 @@ static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_ } } - return len; + return u32len; } -static int nu_qspi_register_bus(struct nu_spi *qspi_device, const char *name) +static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name) { - return rt_qspi_bus_register(&qspi_device->dev, name, &nu_qspi_poll_ops); + return rt_qspi_bus_register(&qspi_bus->dev, name, &nu_qspi_poll_ops); } /** @@ -347,19 +361,21 @@ static int nu_qspi_register_bus(struct nu_spi *qspi_device, const char *name) */ static int rt_hw_qspi_init(void) { - int i; + rt_uint8_t i; for (i = (QSPI_START + 1); i < QSPI_CNT; i++) { nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name); -#if defined(BSP_USING_QSPI_PDMA) +#if defined(BSP_USING_SPI_PDMA) nu_qspi_arr[i].pdma_chanid_tx = -1; nu_qspi_arr[i].pdma_chanid_rx = -1; +#endif +#if defined(BSP_USING_QSPI_PDMA) if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) { if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK) { - rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name); + LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name); } } #endif @@ -381,7 +397,7 @@ rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device)); if (qspi_device == RT_NULL) { - rt_kprintf("no memory, qspi bus attach device failed!\n"); + LOG_E("no memory, qspi bus attach device failed!\n"); result = -RT_ENOMEM; goto __exit; } diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c index d15750e7768c59e1805b16f1bbdc0891aa0eeda4..f187690f33b058b47d16bcf1999313d1d2ae5aca 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c @@ -1,25 +1,26 @@ /**************************************************************************//** -* -* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. -* -* SPDX-License-Identifier: Apache-2.0 -* -* Change Logs: -* Date Author Notes -* 2020-5-31 Egbert First version -* -******************************************************************************/ + * + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-7-21 Egbert First version + * + ******************************************************************************/ #include #if defined(BSP_USING_SCUART) +#include #include #include -#include -/* Private define ---------------------------------------------------------------*/ -#define LOG_TAG "drv.scuart" +/* Private definition + * ---------------------------------------------------------------*/ +#define LOG_TAG "drv.scuart" #define DBG_ENABLE #define DBG_SECTION_NAME "drv.scuart" #define DBG_LEVEL DBG_ERROR @@ -41,7 +42,8 @@ enum SCUART_CNT }; -/* Private typedef --------------------------------------------------------------*/ +/* Private typedef + * --------------------------------------------------------------*/ struct nu_scuart { rt_serial_t dev; @@ -49,34 +51,32 @@ struct nu_scuart SC_T *scuart_base; uint32_t scuart_rst; IRQn_Type scuart_irq_n; - }; typedef struct nu_scuart *nu_scuart_t; -/* Private functions ------------------------------------------------------------*/ -static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); -static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg); +/* Private functions + * ------------------------------------------------------------*/ +static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg); +static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, + void *arg); static int nu_scuart_send(struct rt_serial_device *serial, char c); static int nu_scuart_receive(struct rt_serial_device *serial); static void nu_scuart_isr(nu_scuart_t serial); -/* Public functions ------------------------------------------------------------*/ - -/* Private variables ------------------------------------------------------------*/ - static const struct rt_uart_ops nu_scuart_ops = { - .configure = nu_scuart_configure, - .control = nu_scuart_control, - .putc = nu_scuart_send, - .getc = nu_scuart_receive, - .dma_transmit = RT_NULL /* not support DMA mode */ + .configure = nu_scuart_configure, + .control = nu_scuart_control, + .putc = nu_scuart_send, + .getc = nu_scuart_receive, + .dma_transmit = RT_NULL /* not support DMA mode */ }; static const struct serial_configure nu_scuart_default_config = RT_SERIAL_CONFIG_DEFAULT; -static struct nu_scuart nu_scuart_arr [] = +static struct nu_scuart nu_scuart_arr[] = { #if defined(BSP_USING_SCUART0) { @@ -108,7 +108,8 @@ static struct nu_scuart nu_scuart_arr [] = {0} }; /* scuart nu_scuart */ -/* Interrupt Handle Funtion ----------------------------------------------------*/ +/* Interrupt Handle Function + * ----------------------------------------------------*/ #if defined(BSP_USING_SCUART0) /* SCUART0 interrupt entry */ void SC0_IRQHandler(void) @@ -151,8 +152,6 @@ void SC2_IRQHandler(void) } #endif - - /** * All SCUART interrupt service routine */ @@ -177,9 +176,10 @@ static void nu_scuart_isr(nu_scuart_t serial) } /** - * Configurae scuart port + * Configure scuart port */ -static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) { rt_err_t ret = RT_EOK; uint32_t scuart_word_len = 0; @@ -189,7 +189,7 @@ static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct seri /* Get base address of scuart register */ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; - /* Check baudrate */ + /* Check baud rate */ RT_ASSERT(cfg->baud_rate != 0); /* Check word len */ @@ -258,11 +258,12 @@ static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct seri /* Reset this module */ SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst); - /* Open SCUART and set SCUART Baudrate */ + /* Open SCUART and set SCUART baud rate */ SCUART_Open(scuart_base, cfg->baud_rate); /* Set line configuration. */ - SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity, scuart_stop_bit); + SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity, + scuart_stop_bit); /* Enable NVIC interrupt. */ NVIC_EnableIRQ(((nu_scuart_t)serial)->scuart_irq_n); @@ -278,14 +279,14 @@ exit_nu_scuart_configure: /** * SCUART interrupt control */ -static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg) +static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, + void *arg) { rt_err_t result = RT_EOK; rt_uint32_t flag; rt_ubase_t ctrl_arg = (rt_ubase_t)arg; RT_ASSERT(serial != RT_NULL); - RT_ASSERT(arg != RT_NULL); /* Get base address of scuart register */ SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; @@ -298,10 +299,6 @@ static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk; SCUART_DISABLE_INT(scuart_base, flag); } - else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ - { - LOG_E("SCUART does not support dma transmission"); - } break; case RT_DEVICE_CTRL_SET_INT: @@ -312,6 +309,21 @@ static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void } break; + case RT_DEVICE_CTRL_CLOSE: + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(((nu_scuart_t)serial)->scuart_irq_n); + + /* Reset this module */ + SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst); + + /* Close SCUART port */ + SCUART_Close(scuart_base); + + break; + + default: + result = -RT_EINVAL; + break; } return result; } @@ -327,7 +339,8 @@ static int nu_scuart_send(struct rt_serial_device *serial, char c) SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base; /* Waiting if TX-FIFO is full. */ - while (SCUART_IS_TX_FULL(scuart_base)); + while (SCUART_IS_TX_FULL(scuart_base)) + ; /* Put char into TX-FIFO */ SCUART_WRITE(scuart_base, c); @@ -368,10 +381,11 @@ static int rt_hw_scuart_init(void) { flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; - nu_scuart_arr[i].dev.ops = &nu_scuart_ops; + nu_scuart_arr[i].dev.ops = &nu_scuart_ops; nu_scuart_arr[i].dev.config = nu_scuart_default_config; - ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, flag, NULL); + ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, + flag, NULL); RT_ASSERT(ret == RT_EOK); } diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c index 6c6dd768b82ac835b84b087fde34e921d4e5d20c..aa7d29b39a682efc1d243ab383ef625815ace187 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c @@ -25,17 +25,30 @@ #endif /* Private define ---------------------------------------------------------------*/ -// RT_DEV_NAME_PREFIX sdh -#ifndef NU_SDH_MOUNTPOINT_ROOT - #define NU_SDH_MOUNTPOINT_ROOT "/mnt" +#if defined(NU_SDH_MOUNT_ON_ROOT) + + #if !defined(NU_SDH_MOUNTPOINT_SDH0) + #define NU_SDH_MOUNTPOINT_SDH0 "/" + #endif + + #if !defined(NU_SDH_MOUNTPOINT_SDH1) + #define NU_SDH_MOUNTPOINT_SDH1 NU_SDH_MOUNTPOINT_SDH0"/sd1" + #endif + +#else + + #if !defined(NU_SDH_MOUNTPOINT_ROOT) + #define NU_SDH_MOUNTPOINT_ROOT "/mnt" + #endif + #endif -#ifndef NU_SDH_MOUNTPOINT_SDH0 +#if !defined(NU_SDH_MOUNTPOINT_SDH0) #define NU_SDH_MOUNTPOINT_SDH0 NU_SDH_MOUNTPOINT_ROOT"/sd0" #endif -#ifndef NU_SDH_MOUNTPOINT_SDH1 +#if !defined(NU_SDH_MOUNTPOINT_SDH1) #define NU_SDH_MOUNTPOINT_SDH1 NU_SDH_MOUNTPOINT_ROOT"/sd1" #endif @@ -66,11 +79,9 @@ enum #if defined(NU_SDH_HOTPLUG) enum { - NU_SDH_CARD_INSERTED_SD0 = (1 << 0), - NU_SDH_CARD_REMOVED_SD0 = (1 << 1), - NU_SDH_CARD_INSERTED_SD1 = (1 << 2), - NU_SDH_CARD_REMOVED_SD1 = (1 << 3), - NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_INSERTED_SD0 | NU_SDH_CARD_REMOVED_SD0 | NU_SDH_CARD_INSERTED_SD1 | NU_SDH_CARD_REMOVED_SD1) + NU_SDH_CARD_DETECTED_SD0 = (1 << 0), + NU_SDH_CARD_DETECTED_SD1 = (1 << 1), + NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_DETECTED_SD0 | NU_SDH_CARD_DETECTED_SD1) }; #endif @@ -166,40 +177,12 @@ static void nu_sdh_isr(nu_sdh_t sdh) if (isr & SDH_INTSTS_CDIF_Msk) // card detect { - /* SD interrupt status */ - // it is work to delay 50 times for SD_CLK = 200KHz - { - int volatile i; // delay 30 fail, 50 OK - for (i = 0; i < 0x500; i++); // delay to make sure got updated value from REG_SDISR. - isr = sdh_base->INTSTS; - } - - if (isr & SDH_INTSTS_CDSTS_Msk) - { - /* Card removed */ -#if defined(NU_SDH_HOTPLUG) - if (sdh->base == SDH0) - rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD0); - else if (sdh->base == SDH1) - rt_event_send(&sdh_event, NU_SDH_CARD_REMOVED_SD1); -#endif - sdh->info->IsCardInsert = FALSE; // SDISR_CD_Card = 1 means card remove for GPIO mode - rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T)); - } - else - { - SDH_Open(sdh_base, CardDetect_From_GPIO); - if (!SDH_Probe(sdh_base)) - { - /* Card inserted */ #if defined(NU_SDH_HOTPLUG) - if (sdh->base == SDH0) - rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD0); - else if (sdh->base == SDH1) - rt_event_send(&sdh_event, NU_SDH_CARD_INSERTED_SD1); + if (sdh->base == SDH0) + rt_event_send(&sdh_event, NU_SDH_CARD_DETECTED_SD0); + else if (sdh->base == SDH1) + rt_event_send(&sdh_event, NU_SDH_CARD_DETECTED_SD1); #endif - } - } /* Clear CDIF interrupt flag */ SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CDIF_Msk); } @@ -210,14 +193,14 @@ static void nu_sdh_isr(nu_sdh_t sdh) if (!(isr & SDH_INTSTS_CRC16_Msk)) { /* CRC_16 error */ - // handle CRC 16 error + // TODO: handle CRC 16 error } else if (!(isr & SDH_INTSTS_CRC7_Msk)) { if (!pSD->R3Flag) { /* CRC_7 error */ - // handle CRC 7 error + // TODO: handle CRC 7 error } } /* Clear CRCIF interrupt flag */ @@ -502,6 +485,7 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh) { closedir(t); } +#if !defined(NU_SDH_MOUNT_ON_ROOT) else { @@ -523,6 +507,7 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh) } } //else +#endif if ((ret = dfs_mount(sdh->name, sdh->mounted_point, "elm", 0, 0)) == 0) { @@ -567,6 +552,29 @@ exit_nu_sdh_hotplug_unmount: return -(ret); } + +static void nu_card_detector(nu_sdh_t sdh) +{ + SDH_T *sdh_base = sdh->base; + unsigned int volatile isr = sdh_base->INTSTS; + if (isr & SDH_INTSTS_CDSTS_Msk) + { + /* Card removed */ + sdh->info->IsCardInsert = FALSE; // SDISR_CD_Card = 1 means card remove for GPIO mode + rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T)); + nu_sdh_hotplug_unmount(sdh); + } + else + { + SDH_Open(sdh_base, CardDetect_From_GPIO); + if (!SDH_Probe(sdh_base)) + { + /* Card inserted */ + nu_sdh_hotplug_mount(sdh); + } + } +} + static void sdh_hotplugger(void *param) { rt_uint32_t e; @@ -586,24 +594,18 @@ static void sdh_hotplugger(void *param) RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &e) == RT_EOK) { - /* Debouce */ + /* Debounce */ rt_thread_delay(200); switch (e) { #if defined(BSP_USING_SDH0) - case NU_SDH_CARD_INSERTED_SD0: - nu_sdh_hotplug_mount(&nu_sdh_arr[SDH0_IDX]); - break; - case NU_SDH_CARD_REMOVED_SD0: - nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH0_IDX]); + case NU_SDH_CARD_DETECTED_SD0: + nu_card_detector(&nu_sdh_arr[SDH0_IDX]); break; #endif #if defined(BSP_USING_SDH1) - case NU_SDH_CARD_INSERTED_SD1: - nu_sdh_hotplug_mount(&nu_sdh_arr[SDH1_IDX]); - break; - case NU_SDH_CARD_REMOVED_SD1: - nu_sdh_hotplug_unmount(&nu_sdh_arr[SDH1_IDX]); + case NU_SDH_CARD_DETECTED_SD1: + nu_card_detector(&nu_sdh_arr[SDH1_IDX]); break; #endif default: diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c index 05f9906def180dd59668657d831bb4db656e127d..7c8fe84a9214a63d2ac0fb45b3cdd1f7fd4b85c4 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c @@ -24,7 +24,6 @@ #define DBG_ENABLE #define DBG_SECTION_NAME LOG_TAG #define DBG_LEVEL DBG_INFO -#define DBG_COLOR #include #ifdef BSP_USING_SOFT_I2C0 @@ -58,7 +57,7 @@ struct nu_soft_i2c_config rt_uint8_t sda; const char *bus_name; }; -/* soft i2c dirver class */ +/* soft i2c driver class */ struct nu_soft_i2c { struct rt_i2c_bit_ops ops; diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c index 8a29a847caaaba9834eafa9d60285be271ddba22..c3fc7882032428c99e2aa6c8dcef6f0268d6347e 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.c @@ -11,7 +11,15 @@ ******************************************************************************/ #include -#if defined(BSP_USING_SPI) || defined(BSP_USING_QSPI) +#if defined(BSP_USING_SPI) + +#define LOG_TAG "drv.spi" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + #include #include #include @@ -22,7 +30,7 @@ /* Private define ---------------------------------------------------------------*/ #ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD - #define NU_SPI_USE_PDMA_MIN_THRESHOLD 128 + #define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) #endif enum @@ -52,9 +60,8 @@ static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name); static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); -#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) +#if defined(BSP_USING_SPI_PDMA) static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter); - static void nu_pdma_spi_tx_cb(void *pvUserData, uint32_t u32EventFilter); static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); @@ -63,10 +70,6 @@ static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); void nu_spi_drain_rxfifo(SPI_T *spi_base); -#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) - rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus); -#endif - /* Private variables ------------------------------------------------------------*/ static struct rt_spi_ops nu_spi_poll_ops = { @@ -193,7 +196,7 @@ static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, u32BusClock = SPI_SetBusClock(spi_bus->spi_base, configuration->max_hz); if (configuration->max_hz > u32BusClock) { - rt_kprintf("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); + LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz); configuration->max_hz = u32BusClock; } @@ -235,21 +238,14 @@ exit_nu_spi_bus_configure: return -(ret); } -#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) +#if defined(BSP_USING_SPI_PDMA) static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter) { - struct nu_spi *spi_bus; - spi_bus = (struct nu_spi *)pvUserData; + struct nu_spi *spi_bus = (struct nu_spi *)pvUserData; RT_ASSERT(spi_bus != RT_NULL); - /* Get base address of spi register */ - SPI_T *spi_base = spi_bus->spi_base; - - if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) - { - SPI_DISABLE_RX_PDMA(spi_base); // Stop DMA TX transfer - } + rt_sem_release(spi_bus->m_psSemBus); } static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) { @@ -299,24 +295,6 @@ exit_nu_pdma_spi_rx_config: return result; } -static void nu_pdma_spi_tx_cb(void *pvUserData, uint32_t u32EventFilter) -{ - struct nu_spi *spi_bus; - spi_bus = (struct nu_spi *)pvUserData; - - RT_ASSERT(spi_bus != RT_NULL); - - /* Get base address of spi register */ - SPI_T *spi_base = spi_bus->spi_base; - - if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) - { - SPI_DISABLE_TX_PDMA(spi_base); // Stop DMA TX transfer - } - rt_sem_release(spi_bus->m_psSemBus); - -} - static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) { rt_err_t result = RT_EOK; @@ -328,15 +306,6 @@ static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8 rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx; - result = nu_pdma_callback_register(spi_pdma_tx_chid, - nu_pdma_spi_tx_cb, - (void *)spi_bus, - NU_PDMA_EVENT_TRANSFER_DONE); - if (result != RT_EOK) - { - goto exit_nu_pdma_spi_tx_config; - } - if (pu8Buf == RT_NULL) { spi_bus->dummy = 0; @@ -382,14 +351,14 @@ static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *sen result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word); RT_ASSERT(result == RT_EOK); - /* Trigger TX/RX at the same time. */ - SPI_TRIGGER_TX_PDMA(spi_base); - SPI_TRIGGER_RX_PDMA(spi_base); + /* Trigger TX/RX PDMA transfer. */ + SPI_TRIGGER_TX_RX_PDMA(spi_base); - /* Wait PDMA transfer done */ + /* Wait RX-PDMA transfer done */ rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER); - while (SPI_IS_BUSY(spi_base)); + /* Stop TX/RX DMA transfer. */ + SPI_DISABLE_TX_RX_PDMA(spi_base); return result; } @@ -416,7 +385,7 @@ exit_nu_hw_spi_pdma_allocate: return -(RT_ERROR); } -#endif /* #if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) */ +#endif /* #if defined(BSP_USING_SPI_PDMA) */ void nu_spi_drain_rxfifo(SPI_T *spi_base) { @@ -432,11 +401,11 @@ void nu_spi_drain_rxfifo(SPI_T *spi_base) static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word) { int size = 0; - uint32_t val; // Read RX data if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) { + uint32_t val; // Read data from SPI RX FIFO switch (bytes_per_word) { @@ -455,6 +424,9 @@ static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_wo case 1: *recv_addr = SPI_READ_RX(spi_base); break; + default: + LOG_E("Data length is not supported.\n"); + break; } size = bytes_per_word; } @@ -481,6 +453,9 @@ static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes case 1: SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr)); break; + default: + LOG_E("Data length is not supported.\n"); + break; } return bytes_per_word; @@ -534,7 +509,7 @@ static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, } } // else - /* Wait RX or drian RX-FIFO */ + /* Wait RX or drain RX-FIFO */ if (recv_addr) { // Wait SPI transmission done @@ -565,8 +540,8 @@ void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int lengt #if defined(BSP_USING_SPI_PDMA) /* DMA transfer constrains */ if ((spi_bus->pdma_chanid_rx >= 0) && - (!(uint32_t)tx % bytes_per_word) && - (!(uint32_t)rx % bytes_per_word) && + !((uint32_t)tx % bytes_per_word) && + !((uint32_t)rx % bytes_per_word) && (bytes_per_word != 3) && (length >= NU_SPI_USE_PDMA_MIN_THRESHOLD)) nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word); @@ -594,7 +569,7 @@ static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_m if ((message->length % bytes_per_word) != 0) { /* Say bye. */ - rt_kprintf("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word); + LOG_E("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word); return 0; } @@ -653,7 +628,7 @@ static int rt_hw_spi_init(void) { if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK) { - rt_kprintf("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name); + LOG_W("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name); } } #endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h index c75a126bee85e13b879ffaf0337497ac44275a6c..1e7bd0db442b183c20f8e48f1d41d4942ea16a15 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h @@ -13,11 +13,13 @@ #ifndef __DRV_SPI_H__ #define __DRV_SPI_H__ +#include + #include #include #include -#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_QSPI_PDMA) +#if defined(BSP_USING_SPI_PDMA) #include #endif @@ -27,7 +29,7 @@ struct nu_spi char *name; SPI_T *spi_base; uint32_t dummy; -#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI_PDMA) int16_t pdma_perp_tx; int8_t pdma_chanid_tx; int16_t pdma_perp_rx; @@ -42,7 +44,7 @@ typedef struct nu_spi *nu_spi_t; void nu_spi_drain_rxfifo(SPI_T *spi_base); void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); -#if defined(BSP_USING_SPI_PDMA) || defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI_PDMA) rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus); #endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c index 0b555fe8e78ff8088c1c297ed0cd7f5dcf820923..58181d2400d9a061bf29a60f02680c6d3145068b 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_tpwm.c @@ -19,7 +19,6 @@ #define DBG_ENABLE #define DBG_SECTION_NAME LOG_TAG #define DBG_LEVEL DBG_INFO -#define DBG_COLOR #define TPWM_CHANNEL_NUM 2 #include diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c index b1c5ff45914c7157c35fda21b3b959ee9a513bb2..d8f9ba1777d1c9e6ffb3b7ba7cc1036f671d6906 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c @@ -291,7 +291,7 @@ static struct nu_uart nu_uart_arr [] = {0} }; /* uart nu_uart */ -/* Interrupt Handle Funtion ----------------------------------------------------*/ +/* Interrupt Handle Function ----------------------------------------------------*/ #if defined(BSP_USING_UART0) /* UART0 interrupt entry */ void UART0_IRQHandler(void) @@ -419,6 +419,8 @@ static void nu_uart_isr(nu_uart_t serial) #if defined(RT_SERIAL_USING_DMA) if (u32IntSts & UART_INTSTS_HWRLSIF_Msk) { + /* Drain RX FIFO to remove remain FEF frames in FIFO. */ + uart_base->FIFO |= UART_FIFO_RXRST_Msk; uart_base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk); return; } @@ -434,7 +436,7 @@ static void nu_uart_isr(nu_uart_t serial) } /** - * Configurae uart port + * Configure uart port */ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -544,6 +546,10 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t nu_pdma_uart_rx_cb, (void *)serial, NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); + if ( result != RT_EOK ) + { + goto exit_nu_pdma_uart_rx_config; + } result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_rx, 8, @@ -551,17 +557,24 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t (uint32_t)pu8Buf, i32TriggerLen, 1000); //Idle-timeout, 1ms + if ( result != RT_EOK ) + { + goto exit_nu_pdma_uart_rx_config; + } /* Enable Receive Line interrupt & Start DMA RX transfer. */ UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk); UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk); + +exit_nu_pdma_uart_rx_config: + return result; } static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events) { - rt_size_t recv_len=0; + rt_size_t recv_len = 0; rt_size_t transferred_rxbyte = 0; struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner; nu_uart_t puart = (nu_uart_t)serial; @@ -715,7 +728,6 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void * rt_ubase_t ctrl_arg = (rt_ubase_t)arg; RT_ASSERT(serial != RT_NULL); - RT_ASSERT(arg != RT_NULL); /* Get base address of uart register */ UART_T *uart_base = ((nu_uart_t)serial)->uart_base; @@ -763,6 +775,27 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void * break; #endif + case RT_DEVICE_CTRL_CLOSE: + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n); + +#if defined(RT_SERIAL_USING_DMA) + nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx); + nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx); +#endif + + /* Reset this module */ + SYS_ResetModule(((nu_uart_t)serial)->uart_rst); + + /* Close UART port */ + UART_Close(uart_base); + + break; + + default: + result = -RT_EINVAL; + break; + } return result; } diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c index 52d7e53e7131abd875d76f204a4327f1fa90e158..04d25f453be88acb390cf27d5cb16e3722c3a696 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c @@ -22,7 +22,6 @@ #define DBG_ENABLE #define DBG_SECTION_NAME LOG_TAG #define DBG_LEVEL DBG_INFO -#define DBG_COLOR #include #define SLV_10BIT_ADDR (0x1E<<2) //1111+0xx+r/w @@ -110,7 +109,7 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c, LOG_D("addr1: %d, addr2: %d\n", addr1, addr2); ret = nu_ui2c_send_data(nu_ui2c, addr1); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition return -RT_EIO; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) @@ -122,7 +121,7 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c, UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); ret = nu_ui2c_send_data(nu_ui2c, addr2); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition return -RT_EIO; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) @@ -139,7 +138,7 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c, UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STA)); ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition return -RT_EIO; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk) && !ignore_nack) @@ -150,16 +149,15 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c, } UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk); - addr1 |= 0x01; + addr1 |= RT_I2C_RD; ret = nu_ui2c_send_data(nu_ui2c, addr1); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition return -RT_EIO; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack) { LOG_E("NACK: sending repeated addr\n"); - return -RT_EIO; } UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk); @@ -170,11 +168,11 @@ static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c, /* 7-bit addr */ addr1 = msg->addr << 1; if (flags & RT_I2C_RD) - addr1 |= 1; + addr1 |= RT_I2C_RD; /* Send device address */ ret = nu_ui2c_send_data(nu_ui2c, addr1); /* Send Address */ - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition return -RT_EIO; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) @@ -210,7 +208,7 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_STA); ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition { rt_set_errno(-RT_ETIMEOUT); return 0; @@ -235,7 +233,7 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, { UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STA));/* Send repeat START */ ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition break; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) /* Check Send repeat START */ @@ -272,7 +270,7 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, } ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition break; if (nu_ui2c->ui2c_base->PROTCTL & UI2C_CTL_AA) @@ -303,12 +301,12 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, { /* Send register number and MSB of data */ ret = nu_ui2c_send_data(nu_ui2c, (uint8_t)(nu_ui2c->msg[i].buf[cnt_data])); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition break; if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack - ) /* Send aata and get Ack */ + ) /* Send data and get Ack */ { i = 0; break; @@ -320,7 +318,7 @@ static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus, UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STO)); /* Send STOP signal */ ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c); - if (ret != RT_EOK) //for timeout conditrion + if (ret != RT_EOK) //for timeout condition { rt_set_errno(-RT_ETIMEOUT); return 0; @@ -357,8 +355,11 @@ int rt_hw_ui2c_init(void) #if defined(BSP_USING_UI2C0) /* Enable UI2C0 clock */ + SYS_UnlockReg(); CLK_EnableModuleClock(USCI0_MODULE); SYS_ResetModule(USCI0_RST); + SYS_LockReg(); + nu_ui2c0.ui2c_dev.ops = &nu_ui2c_ops; ret = rt_i2c_bus_device_register(&nu_ui2c0.ui2c_dev, nu_ui2c0.dev_name); RT_ASSERT(RT_EOK == ret); @@ -366,8 +367,11 @@ int rt_hw_ui2c_init(void) #if defined(BSP_USING_UI2C1) /* Enable UI2C1 clock */ + SYS_UnlockReg(); CLK_EnableModuleClock(USCI1_MODULE); SYS_ResetModule(USCI1_RST); + SYS_LockReg(); + nu_ui2c1.ui2c_dev.ops = &nu_ui2c_ops; ret = rt_i2c_bus_device_register(&nu_ui2c1.ui2c_dev, nu_ui2c1.dev_name); RT_ASSERT(RT_EOK == ret); diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c index 96fab9857a277bddd8599802024e0a1d61babd84..c670420eb8b0239225bfe51bcf1cc6e59298af88 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c @@ -56,14 +56,12 @@ typedef struct nu_uspi *uspi_t; /* Private functions ------------------------------------------------------------*/ static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); static rt_uint32_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); -static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, - uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name); static void nu_uspi_drain_rxfifo(USPI_T *uspi_base); #if defined(BSP_USING_USPI_PDMA) static void nu_pdma_uspi_rx_cb(void *pvUserData, uint32_t u32EventFilter); - static void nu_pdma_uspi_tx_cb(void *pvUserData, uint32_t u32EventFilter); static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); @@ -187,12 +185,12 @@ static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, if (configuration->mode & RT_SPI_MSB) { /* Set sequence to MSB first */ - SPI_SET_MSB_FIRST(uspi_bus->uspi_base); + USPI_SET_MSB_FIRST(uspi_bus->uspi_base); } else { /* Set sequence to LSB first */ - SPI_SET_LSB_FIRST(uspi_bus->uspi_base); + USPI_SET_LSB_FIRST(uspi_bus->uspi_base); } } @@ -212,17 +210,11 @@ static void nu_pdma_uspi_rx_cb(void *pvUserData, uint32_t u32EventFilter) RT_ASSERT(uspi_bus != RT_NULL); - /* Get base address of uspi register */ - USPI_T *uspi_base = uspi_bus->uspi_base; - - if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) - { - USPI_DISABLE_RX_PDMA(uspi_base); // Stop DMA TX transfer - } + rt_sem_release(uspi_bus->m_psSemBus); } static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) { - rt_err_t result = RT_EOK; + rt_err_t result = RT_ERROR; rt_uint8_t *dst_addr = NULL; nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; @@ -269,27 +261,9 @@ exit_nu_pdma_uspi_rx_config: return result; } -static void nu_pdma_uspi_tx_cb(void *pvUserData, uint32_t u32EventFilter) -{ - struct nu_uspi *uspi_bus; - uspi_bus = (struct nu_uspi *)pvUserData; - - RT_ASSERT(uspi_bus != RT_NULL); - - /* Get base address of uspi register */ - USPI_T *uspi_base = uspi_bus->uspi_base; - - if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) - { - USPI_DISABLE_TX_PDMA(uspi_base); // Stop DMA TX transfer - } - rt_sem_release(uspi_bus->m_psSemBus); - -} - static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) { - rt_err_t result = RT_EOK; + rt_err_t result = RT_ERROR; rt_uint8_t *src_addr = NULL; nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; @@ -298,15 +272,6 @@ static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t * rt_uint8_t uspi_pdma_tx_chid = uspi_bus->pdma_chanid_tx; - result = nu_pdma_callback_register(uspi_pdma_tx_chid, - nu_pdma_uspi_tx_cb, - (void *)uspi_bus, - NU_PDMA_EVENT_TRANSFER_DONE); - if (result != RT_EOK) - { - goto exit_nu_pdma_uspi_tx_config; - } - if (pu8Buf == RT_NULL) { uspi_bus->dummy = 0; @@ -343,7 +308,7 @@ exit_nu_pdma_uspi_tx_config: */ static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) { - rt_err_t result = RT_EOK; + rt_err_t result = RT_ERROR; /* Get base address of uspi register */ USPI_T *uspi_base = uspi_bus->uspi_base; @@ -354,13 +319,13 @@ static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t * RT_ASSERT(result == RT_EOK); /* Trigger TX/RX at the same time. */ - USPI_TRIGGER_TX_PDMA(uspi_base); - USPI_TRIGGER_RX_PDMA(uspi_base); + USPI_TRIGGER_TX_RX_PDMA(uspi_base); /* Wait PDMA transfer done */ rt_sem_take(uspi_bus->m_psSemBus, RT_WAITING_FOREVER); - while (USPI_IS_BUSY(uspi_base)); + /* Stop DMA TX/RX transfer */ + USPI_DISABLE_TX_RX_PDMA(uspi_base); return result; } @@ -404,7 +369,6 @@ static void nu_uspi_drain_rxfifo(USPI_T *uspi_base) static int nu_uspi_read(USPI_T *uspi_base, uint8_t *recv_addr, uint8_t bytes_per_word) { int size = 0; - uint32_t val; // Read RX data if (!USPI_GET_RX_EMPTY_FLAG(uspi_base)) @@ -412,6 +376,7 @@ static int nu_uspi_read(USPI_T *uspi_base, uint8_t *recv_addr, uint8_t bytes_per // Read data from USPI RX FIFO switch (bytes_per_word) { + uint32_t val; case 2: val = USPI_READ_RX(uspi_base); nu_set16_le(recv_addr, val); @@ -419,6 +384,8 @@ static int nu_uspi_read(USPI_T *uspi_base, uint8_t *recv_addr, uint8_t bytes_per case 1: *recv_addr = USPI_READ_RX(uspi_base); break; + default: + break; } size = bytes_per_word; } @@ -439,6 +406,8 @@ static int nu_uspi_write(USPI_T *uspi_base, const uint8_t *send_addr, uint8_t by case 1: USPI_WRITE_TX(uspi_base, *((uint8_t *)send_addr)); break; + default: + break; } return bytes_per_word; @@ -475,6 +444,7 @@ static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, length -= nu_uspi_write(uspi_base, (const uint8_t *)&uspi_bus->dummy, bytes_per_word); /* Read data from RX FIFO */ + while (USPI_GET_RX_EMPTY_FLAG(uspi_base)); recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); } } // else if (send_addr == RT_NULL && recv_addr != RT_NULL) @@ -488,11 +458,12 @@ static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus, length -= bytes_per_word; /* Read data from RX FIFO */ + while (USPI_GET_RX_EMPTY_FLAG(uspi_base)); recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word); } } // else - /* Wait RX or drian RX-FIFO */ + /* Wait RX or drain RX-FIFO */ if (recv_addr) { // Wait SPI transmission done @@ -521,9 +492,8 @@ static void nu_uspi_transfer(struct nu_uspi *uspi_bus, uint8_t *tx, uint8_t *rx, #if defined(BSP_USING_USPI_PDMA) /* DMA transfer constrains */ if ((uspi_bus->pdma_chanid_rx >= 0) && - (!(uint32_t)tx % bytes_per_word) && - (!(uint32_t)rx % bytes_per_word) && - (bytes_per_word != 3)) + !((uint32_t)tx % bytes_per_word) && + !((uint32_t)rx % bytes_per_word) ) nu_uspi_pdma_transmit(uspi_bus, tx, rx, length, bytes_per_word); else nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word); diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c index 0ced7ea397cfefa93ac5ed79ef69a85fac90b815..1be9643f47ec34f59e58439936292659dad2223a 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c @@ -139,7 +139,7 @@ static struct nu_uuart nu_uuart_arr [] = {0} }; /* uuart nu_uuart */ -/* Interrupt Handle Funtion ----------------------------------------------------*/ +/* Interrupt Handle Function ----------------------------------------------------*/ #if defined(BSP_USING_UUART0) /* USCI0 interrupt entry */ void USCI0_IRQHandler(void) @@ -197,7 +197,7 @@ static void nu_uuart_isr(nu_uuart_t serial) } /** - * Configurae uuart port + * Configure uuart port */ static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -209,12 +209,9 @@ static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct seria /* Get base address of uuart register */ UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; - - /* Check baudrate */ + /* Check baud rate */ RT_ASSERT(cfg->baud_rate != 0); - - /* Check word len */ switch (cfg->data_bits) { @@ -280,8 +277,7 @@ static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct seria /* Reset this module */ SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst); - - /* Open UUart and set UUART Baudrate */ + /* Open UUart and set UUART baud rate */ UUART_Open(uuart_base, cfg->baud_rate); /* Set line configuration. */ @@ -311,6 +307,11 @@ static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t (void *)serial, NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); + if (result != RT_EOK) + { + goto exit_nu_pdma_uuart_rx_config; + } + result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_rx, 8, (uint32_t)&uuart_base->RXDAT, @@ -318,7 +319,10 @@ static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t i32TriggerLen, 1000); //Idle-timeout, 1ms - + if (result != RT_EOK) + { + goto exit_nu_pdma_uuart_rx_config; + } //UUART PDMA reset UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_PDMARST_Msk); @@ -327,6 +331,7 @@ static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t UUART_EnableInt(uuart_base, UUART_RLS_INT_MASK); UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk); +exit_nu_pdma_uuart_rx_config: return result; } @@ -483,7 +488,6 @@ static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void rt_ubase_t ctrl_arg = (rt_ubase_t)arg; RT_ASSERT(serial != RT_NULL); - RT_ASSERT(arg != RT_NULL); /* Get base address of uuart register */ UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base; @@ -530,6 +534,25 @@ static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void break; #endif + case RT_DEVICE_CTRL_CLOSE: + /* Disable NVIC interrupt. */ + NVIC_DisableIRQ(((nu_uuart_t)serial)->uuart_irq_n); + +#if defined(RT_SERIAL_USING_DMA) + nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_tx); + nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx); +#endif + + /* Reset this module */ + SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst); + + /* Close UUART port */ + UUART_Close(uuart_base); + + break; + default: + result = -RT_EINVAL; + break; } return result; } @@ -599,7 +622,7 @@ static int rt_hw_uuart_init(void) RT_ASSERT(ret == RT_EOK); } - return ret; + return (int)ret; } INIT_DEVICE_EXPORT(rt_hw_uuart_init); diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c index a4160600e68c65a58d6ba6001e69679ced004e89..82572325d26fb73675f3ad03567a8ef01abd7bcf 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c @@ -13,7 +13,6 @@ #include #if defined(BSP_USING_WDT) - #include #include #include @@ -22,7 +21,7 @@ /*-------------------------------------------------------------------------------*/ /* watchdog timer timeout look up table */ /*-------------------------------------------------------------------------------*/ -/* clock = LIRC 10Khz. */ +/* clock = LIRC 10KHz. */ /* */ /* working hz toutsel exp cycles timeout (s) */ /* 10000 0 4 16 0.0016 */ @@ -34,7 +33,7 @@ /* 6 16 65536 6.5536 */ /* 7 18 262144 26.2144 */ /*-------------------------------------------------------------------------------*/ -/* clock = LXT 32.76Khz. */ +/* clock = LXT 32768Hz. */ /* */ /* working hz toutsel exp cycles timeout (s) */ /* 32768 0 4 16 0.0005 */ @@ -46,7 +45,7 @@ /* 6 16 65536 2.0000 */ /* 7 18 262144 8.0000 */ /*-------------------------------------------------------------------------------*/ -/* clock = 192Mhz HCLK divide 2048 = 93750 hz. */ +/* clock = 192MHz HCLK divide 2048 = 93750 Hz. */ /* */ /* working hz toutsel exp cycles timeout (s) */ /* 93750 0 4 16 0.00017 */ @@ -69,10 +68,10 @@ #define MIN_CYCLES (1024) -/* Macros to convert the value bewtween the timeout interval and the soft time iterations. */ +/* Macros to convert the value between the timeout interval and the soft time iterations. */ #define ROUND_TO_INTEGER(value) ((int)(((value) * 10 + 5) / 10)) -#define CONV_SEC_TO_IT(hz, secs) ROUND_TO_INTEGER((float)((secs) * (hz)) / (float)MIN_CYCLES) -#define CONV_IT_TO_SEC(hz, iterations) ROUND_TO_INTEGER((float)(iterations * MIN_CYCLES) / (float)hz) +#define CONV_SEC_TO_IT(hz, secs) (ROUND_TO_INTEGER((float)((secs) * (hz)) / (float)(MIN_CYCLES))) +#define CONV_IT_TO_SEC(hz, iterations) (ROUND_TO_INTEGER((float)((iterations) * (MIN_CYCLES)) / (float)(hz))) /* Private typedef --------------------------------------------------------------*/ @@ -98,12 +97,10 @@ static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t static void soft_time_feed_dog(soft_time_handle_t *const soft_time); #if defined(RT_USING_PM) - static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode); - static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode); - static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode); - - static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time); - +static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode); +static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode); +static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode); +static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time); #endif /* Public functions -------------------------------------------------------------*/ @@ -129,8 +126,6 @@ static struct rt_device_pm_ops device_pm_ops = #endif - - #if defined(RT_USING_PM) /* device pm suspend() entry. */ @@ -204,7 +199,7 @@ static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mo if (new_hz == soft_time.clock_hz) return (int)(RT_EOK); - /* frequency change occurs in critial section */ + /* frequency change occurs in critical section */ soft_time_freqeucy_change(new_hz, &soft_time); } @@ -241,7 +236,7 @@ static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const if (corner_case) { - LOG_W("pm frequency change cause wdt intenal left iterations convert to 0.\n\r \ + LOG_W("pm frequency change cause wdt internal left iterations convert to 0.\n\r \ wdt driver will add another 1 iteration for this corner case."); } } @@ -263,7 +258,7 @@ static void hw_wdt_init(void) } -/* wdt device driver initialise. */ +/* wdt device driver initialize. */ int rt_hw_wdt_init(void) { rt_err_t ret; @@ -278,13 +273,12 @@ int rt_hw_wdt_init(void) rt_pm_device_register((struct rt_device *)&device_wdt, &device_pm_ops); #endif - return (int)ret; } INIT_BOARD_EXPORT(rt_hw_wdt_init); -/* Reigster rt-thread device.init() entry. */ +/* Register rt-thread device.init() entry. */ static rt_err_t wdt_init(rt_watchdog_t *dev) { soft_time_init(&soft_time); diff --git a/bsp/nuvoton/numaker-iot-m487/README.md b/bsp/nuvoton/numaker-iot-m487/README.md index 185d77cbdfdb8b6b8447acc90f6a0c24ffda4109..480c536936e4f59dd0344a91936f6732b387748c 100644 --- a/bsp/nuvoton/numaker-iot-m487/README.md +++ b/bsp/nuvoton/numaker-iot-m487/README.md @@ -35,7 +35,7 @@ NuMaker-IoT-M487 provides multiple networking, interfaces, audio recording, play |Ethernet PHY| IP101GR | Supported | |Sensor| BMX055 | Supported | |Wi-Fi module| ESP8266-ESP12, AT firmware v1.7 | Supported | -|Audio Codec| NAU88L25, Supports MIC and earphone | Coming soon | +|Audio Codec| NAU88L25, Supports MIC and earphone | Supported | ## 2. Supported compiler Support GCC, MDK4, MDK5, IAR IDE/compilers. More information of these compiler version as following: diff --git a/bsp/nuvoton/numaker-iot-m487/applications/main.c b/bsp/nuvoton/numaker-iot-m487/applications/main.c index bffd9956a01eef3b7692e6b160ed35d9df98e0ba..16126baad09ac6274a332ec1e80e4221135559eb 100644 --- a/bsp/nuvoton/numaker-iot-m487/applications/main.c +++ b/bsp/nuvoton/numaker-iot-m487/applications/main.c @@ -10,7 +10,7 @@ * ******************************************************************************/ -#include +#include #include #include @@ -19,6 +19,8 @@ int main(int argc, char **argv) { +#if defined(RT_USING_PIN) + int counter = 0; /* set LEDR1 pin mode to output */ @@ -32,5 +34,6 @@ int main(int argc, char **argv) rt_thread_mdelay(500); } +#endif return 0; } diff --git a/bsp/nuvoton/numaker-iot-m487/board/board_dev.c b/bsp/nuvoton/numaker-iot-m487/board/board_dev.c index 7f3aafb45eec1fcb633447fced3cdf31495718fa..068573e8fe6304e9196ecffa09600973a7386322 100644 --- a/bsp/nuvoton/numaker-iot-m487/board/board_dev.c +++ b/bsp/nuvoton/numaker-iot-m487/board/board_dev.c @@ -145,7 +145,8 @@ INIT_APP_EXPORT(rt_hw_bmx055_port); #if defined(BOARD_USING_ESP8266) #include -#define LOG_TAG "at.sample.esp" +#define LOG_TAG "at.sample.esp" +#undef DBG_TAG #include static struct at_device_esp8266 esp0 = diff --git a/bsp/nuvoton/numaker-pfm-m487/README.md b/bsp/nuvoton/numaker-pfm-m487/README.md index 3575f3b9c2ca471a1a9605cbe62b7b77b8d98c89..6f9a6c300c2d2be7ae427872c81ff10242b3339b 100644 --- a/bsp/nuvoton/numaker-pfm-m487/README.md +++ b/bsp/nuvoton/numaker-pfm-m487/README.md @@ -32,7 +32,7 @@ NuMaker-PFM-M487 provides multiple networking, interfaces, audio recording, play | -- | -- | -- | |SPI flash | W25Q32 | Supported | |Ethernet PHY| IP101GR | Supported | -|Audio Codec| NAU88L25, Supports MIC and earphone | Coming soon | +|Audio Codec| NAU88L25, Supports MIC and earphone | Supported | ## 2. Supported compiler Support GCC, MDK4, MDK5, IAR IDE/compilers. More information of these compiler version as following: diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c index 030002dbe24d5444ad853179d4a9c3f14672ee69..82e4250a5247b667bd77c42af0a38e0fd12a3711 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c @@ -209,10 +209,12 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch #elif defined(SOC_SERIES_STM32MP1) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5; #endif + #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) ADC_ChanConf.Offset = 0; #endif -#ifdef SOC_SERIES_STM32L4 + +#if defined(SOC_SERIES_STM32L4) ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED; #elif defined(SOC_SERIES_STM32MP1) @@ -221,9 +223,17 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch ADC_ChanConf.SingleDiff = ADC_SINGLE_ENDED; /* ADC channel differential mode */ #endif HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf); -#ifdef SOC_SERIES_STM32MP1 - /* Run the ADC linear calibration in single-ended mode */ - if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) + + /* perform an automatic ADC calibration to improve the conversion accuracy */ +#if defined(SOC_SERIES_STM32L4) + if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_ChanConf.SingleDiff) != HAL_OK) + { + LOG_E("ADC calibration error!\n"); + return -RT_ERROR; + } +#elif defined(SOC_SERIES_STM32MP1) + /* Run the ADC linear calibration in single-ended mode */ + if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_CALIB_OFFSET_LINEARITY, ADC_ChanConf.SingleDiff) != HAL_OK) { LOG_E("ADC open linear calibration error!\n"); /* Calibration Error */ diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s index d38ddd3fa4363518488e36a6b5c95351be1c63ba..4deacdd1e5a1a03e179030d342a46b17840fd93f 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s +++ b/bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s @@ -14,8 +14,8 @@ ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) 2019 STMicroelectronics. -;* All rights reserved.

+;* © Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, ;* the "License"; You may not use this file except in compliance with the @@ -30,7 +30,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000400 +Stack_Size EQU 0x00000800 AREA STACK, NOINIT, READWRITE, ALIGN=3 __stack_limit diff --git a/bsp/stm32/stm32f072-st-nucleo/README.md b/bsp/stm32/stm32f072-st-nucleo/README.md index 1e3f6391a66d98bd026d88508d1dfeca65385341..e2d1a3e0acf0aebfd9d8d70cf32d9dbf1691405f 100644 --- a/bsp/stm32/stm32f072-st-nucleo/README.md +++ b/bsp/stm32/stm32f072-st-nucleo/README.md @@ -29,7 +29,7 @@ NUCLEO-F072RB 开发板常用 **板载资源** 如下： - 常用接口：USB 转串口、Arduino Uno 和 ST morpho 两类扩展接口 - 调试接口：板载 ST-LINK/V2-1 调试器。 -更多相关信息资料见 ST 官网详情页：[NUCLEO_F072RB_STM32Nucleo-64开发板]https://www.stmcu.com.cn/Designresource/design_resource_detail?file_name=NUCLEO_F072RB_STM32Nucleo-64%E5%BC%80%E5%8F%91%E6%9D%BF&lang=EN&ver= +开发板更多详细信息请参考意法半导体[NUCLEO-F072RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f072rb.html) ## 外设支持 diff --git a/bsp/stm32/stm32f091-st-nucleo/README.md b/bsp/stm32/stm32f091-st-nucleo/README.md index 5165ed6f8570a71e727c3f8971385e98df5238b6..5e19d41c65a8ee684fa654dd0b83e9718841f4b4 100644 --- a/bsp/stm32/stm32f091-st-nucleo/README.md +++ b/bsp/stm32/stm32f091-st-nucleo/README.md @@ -1,8 +1,8 @@ -# BSP README 模板 +# NUCLEO-F091RC 开发板 BSP 说明 ## 简介 -本文档为 RT-Thread 开发团队为 STM32F091RC-NuCLEO 开发板提供的 BSP (板级支持包) 说明。 +本文档为 RT-Thread 开发团队为 STM32F091RC-NUCLEO 开发板提供的 BSP (板级支持包) 说明。 主要内容如下： @@ -22,7 +22,7 @@ STM32F091RC-NuCLEO 开发板是 ST 官方推出的一款基于 ARM Cortex-M0 内 该开发板常用 **板载资源** 如下： -- MCU：STM32F091，主频 48MHz，256KB FLASH ，32KB RAM +- MCU：STM32F091RC，主频 48MHz，256KB FLASH ，32KB RAM - 外部 RAM：无 - 外部 FLASH：无 - 常用外设 @@ -30,7 +30,7 @@ STM32F091RC-NuCLEO 开发板是 ST 官方推出的一款基于 ARM Cortex-M0 内 - 常用接口：USB 转串口、arduino 接口等 - 调试接口，标准 SWD -开发板更多详细信息请参考 ST 的 [NUCLEO 开发板介绍](https://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html?querycriteria=productId=LN1847)。 +开发板更多详细信息请参考意法半导体[NUCLEO-F091RC](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f091rc.html)。 ## 外设支持 diff --git a/bsp/stm32/stm32f412-st-nucleo/README.md b/bsp/stm32/stm32f412-st-nucleo/README.md index 10fb2c58fa8097a6b4bbd315a492677bc3a413c5..2502e29e292a03a45eb37cda099c5ab75cf8fc5c 100644 --- a/bsp/stm32/stm32f412-st-nucleo/README.md +++ b/bsp/stm32/stm32f412-st-nucleo/README.md @@ -20,9 +20,9 @@ ![board](figures/board.png) -该开发板常用 ** 板载资源 ** 如下： +该开发板常用 **板载资源** 如下： -- MCU：STM32F411ZG，主频 100MHz，1024KB FLASH ，256KB RAM。 +- MCU：STM32F412ZG，主频 100MHz，1024KB FLASH ，256KB RAM。 - 常用外设 - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 - 按键，2 个，USER and RESET 。 @@ -71,7 +71,7 @@ #### 运行结果 -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、蓝色 LD2 会周期性闪烁。 USB 虚拟 COM 端口默认连接串口 3，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: diff --git a/bsp/stm32/stm32f429-st-disco/.config b/bsp/stm32/stm32f429-st-disco/.config index aa1da658873475d41e46a85f91ef951ce5982198..d2e8ecd25981e157843c9c841239f4a7fa259d98 100644 --- a/bsp/stm32/stm32f429-st-disco/.config +++ b/bsp/stm32/stm32f429-st-disco/.config @@ -42,7 +42,7 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set +CONFIG_RT_USING_SIGNALS=y # # Memory Management @@ -50,10 +50,9 @@ CONFIG_RT_USING_MESSAGEQUEUE=y CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y CONFIG_RT_USING_HEAP=y # @@ -65,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_VER_NUM=0x40003 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -101,7 +100,7 @@ CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_USING_MSH_ONLY=y CONFIG_FINSH_ARG_MAX=10 # @@ -133,16 +132,19 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -162,7 +164,8 @@ CONFIG_RT_USING_PIN=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y -# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set @@ -213,10 +216,15 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -243,6 +251,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -255,8 +264,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -268,6 +279,14 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_ONNX_PARSER is not set # CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set # # security packages @@ -275,6 +294,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -303,6 +324,14 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set # # system packages @@ -314,6 +343,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -322,6 +352,13 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set # # peripheral libraries and drivers @@ -329,6 +366,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -337,10 +375,16 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -348,9 +392,23 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set # # miscellaneous packages @@ -385,6 +443,42 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F4=y @@ -393,6 +487,11 @@ CONFIG_SOC_SERIES_STM32F4=y # CONFIG_SOC_STM32F429ZI=y +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_SDRAM=y + # # On-chip Peripheral Drivers # @@ -400,12 +499,14 @@ CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y # CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_FMC is not set -# CONFIG_BSP_USING_USBD_FS is not set -# CONFIG_BSP_USING_LTDC is not set +CONFIG_BSP_USING_FMC=y +# CONFIG_BSP_USING_USBD is not set +CONFIG_BSP_USING_LCD=y +CONFIG_BSP_USING_LTDC=y # CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_UDID is not set diff --git a/bsp/stm32/stm32f429-st-disco/.cproject b/bsp/stm32/stm32f429-st-disco/.cproject new file mode 100644 index 0000000000000000000000000000000000000000..f753c0fb4c8c7b879bdb5856c6bef7c2d11fd088 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.cproject @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/.project b/bsp/stm32/stm32f429-st-disco/.project new file mode 100644 index 0000000000000000000000000000000000000000..f8150396f50f65a6486bf3a3a26a149c0cfefaa7 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.project @@ -0,0 +1,30 @@ + + + stm32f429 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + diff --git a/bsp/stm32/stm32f429-st-disco/.settings/.rtmenus b/bsp/stm32/stm32f429-st-disco/.settings/.rtmenus new file mode 100644 index 0000000000000000000000000000000000000000..da3a12f5e7568f633bd4529d437671559b4f061b Binary files /dev/null and b/bsp/stm32/stm32f429-st-disco/.settings/.rtmenus differ diff --git a/bsp/stm32/stm32f429-st-disco/.settings/language.settings.xml b/bsp/stm32/stm32f429-st-disco/.settings/language.settings.xml new file mode 100644 index 0000000000000000000000000000000000000000..66e32d6ac6a617792e75970ec4233d0ad94fbc55 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/.settings/org.eclipse.core.runtime.prefs b/bsp/stm32/stm32f429-st-disco/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000000000000000000000000000000000000..b36aae6fb2a4e8309f6c2299be466d8774582ed4 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 diff --git a/bsp/stm32/stm32f429-st-disco/.settings/projcfg.ini b/bsp/stm32/stm32f429-st-disco/.settings/projcfg.ini new file mode 100644 index 0000000000000000000000000000000000000000..9ae064cb867b2d6fabc053849f3e2563340b9ff1 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/projcfg.ini @@ -0,0 +1,9 @@ +#RT-Thread Studio Project Configuration +#Thu Aug 06 07:31:27 CST 2020 +qemu_supported_board=stm32f429-st-disco +mcu_name=STM32F429ZI +hardware_adapter=QEMU +selected_rtt_version=latest +mcu_base_nano_proj=true +project_base_bsp=true +cfg_version=v2.0 diff --git a/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.DAPLink.Debug.rttlaunch b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.DAPLink.Debug.rttlaunch new file mode 100644 index 0000000000000000000000000000000000000000..28087044b28085dc80e76fc40a85036f6f9c01c1 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.DAPLink.Debug.rttlaunch @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.JLink.Debug.rttlaunch b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.JLink.Debug.rttlaunch new file mode 100644 index 0000000000000000000000000000000000000000..5630a7d174287f0af31ab90852fdc8eb5b49053f --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.JLink.Debug.rttlaunch @@ -0,0 +1,83 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.Qemu.Debug.rttlaunch b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.Qemu.Debug.rttlaunch new file mode 100644 index 0000000000000000000000000000000000000000..484ce87d658c2dcfccb8ffeec2172a64094bd753 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.Qemu.Debug.rttlaunch @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.STLink.Debug.rttlaunch b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.STLink.Debug.rttlaunch new file mode 100644 index 0000000000000000000000000000000000000000..1cea70c74d60538c0c23576c7164b8fe82cb1452 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/.settings/stm32f429.STLink.Debug.rttlaunch @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/board/Kconfig b/bsp/stm32/stm32f429-st-disco/board/Kconfig index 20b1a98ab3fccb07f928a60689c8b41ad6b1d811..2461f52bd4929f1437d6cae877f18825901f002e 100644 --- a/bsp/stm32/stm32f429-st-disco/board/Kconfig +++ b/bsp/stm32/stm32f429-st-disco/board/Kconfig @@ -7,7 +7,17 @@ config SOC_STM32F429ZI select RT_USING_USER_MAIN default y +menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + select BSP_USING_FMC + default n + +endmenu + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN @@ -15,8 +25,8 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_UART bool "Enable UART" - select RT_USING_SERIAL default y + select RT_USING_SERIAL if BSP_USING_UART config BSP_USING_UART1 bool "Enable UART1" @@ -26,15 +36,25 @@ menu "On-chip Peripheral Drivers" bool "Enable UART1 RX DMA" depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + endif menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" + default n select RT_USING_I2C select RT_USING_I2C_BITOPS select RT_USING_PIN - default n - if BSP_USING_I2C1 + if BSP_USING_I2C1 config BSP_I2C1_SCL_PIN int "I2C1 scl pin number" range 1 176 @@ -48,7 +68,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_SPI bool "Enable SPI BUS" select RT_USING_SPI - default n + default y if BSP_USING_SPI config BSP_USING_SPI3 bool "Enable SPI3 BUS" @@ -81,11 +101,18 @@ menu "On-chip Peripheral Drivers" select RT_USING_USB_DEVICE default n + config BSP_USING_LCD + bool "Enable LCD" + default n + config BSP_USING_LTDC bool "Enable LTDC" + select BSP_USING_SDRAM + select BSP_USING_LCD default n + source "../libraries/HAL_Drivers/Kconfig" - + endmenu menu "Board extended module Drivers" diff --git a/bsp/stm32/stm32f429-st-disco/board/SConscript b/bsp/stm32/stm32f429-st-disco/board/SConscript index ebaa566f5c84ee43386db189cc53aae7d43427f8..55924547ecfcc261cb2aed5fdf2a792b991209bd 100644 --- a/bsp/stm32/stm32f429-st-disco/board/SConscript +++ b/bsp/stm32/stm32f429-st-disco/board/SConscript @@ -17,19 +17,19 @@ if GetDepend(['BSP_USING_QSPI_FLASH']): if GetDepend(['PKG_USING_FAL']): src += ['ports/qspi_mnt.c'] - -if GetDepend(['BSP_USING_LCD_OTM8009A']): - src += ['ports/drv_otm8009a.c'] - + if GetDepend(['BSP_USING_TOUCH']): src += Glob('ports/touch/*.c') - + if GetDepend(['BSP_USING_SDCARD']): src += ['ports/drv_sdcard.c'] - + if GetDepend(['BSP_USING_QSPI']): src += ['ports/drv_qspi_flash.c'] +if GetDepend(['BSP_USING_LCD']): + src += ['ports/ili9341.c'] + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32f429-st-disco/board/board.c b/bsp/stm32/stm32f429-st-disco/board/board.c index ca12c3724ebef0d4b99272765d3dad3a48562344..0abc70267aea923ccf7977e5c7c1765daa6fdfb1 100644 --- a/bsp/stm32/stm32f429-st-disco/board/board.c +++ b/bsp/stm32/stm32f429-st-disco/board/board.c @@ -48,12 +48,15 @@ void SystemClock_Config(void) { Error_Handler(); } + /*##-2- LTDC Clock Configuration ###########################################*/ + /* LCD clock configuration */ + /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 MHz */ + /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/4 = 48 MHz */ + /* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDIVR_8 = 48/8 = 6 MHz */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; - PeriphClkInitStruct.PLLSAI.PLLSAIN = 50; - PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; - PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 4; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); } diff --git a/bsp/stm32/stm32f429-st-disco/board/board.h b/bsp/stm32/stm32f429-st-disco/board/board.h index 47e439a26042a8ce24261eec683b9fb8d45d37a1..69e3eb1fac729b617d271a6593fe18e0402aa108 100644 --- a/bsp/stm32/stm32f429-st-disco/board/board.h +++ b/bsp/stm32/stm32f429-st-disco/board/board.h @@ -25,8 +25,8 @@ extern "C" { #define STM32_FLASH_SIZE (2048 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) -#define STM32_SRAM_SIZE (256 - 64) -#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) +#define STM32_SRAM_SIZE (256 - 64) +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c new file mode 100644 index 0000000000000000000000000000000000000000..3829193b5c5b956ffb419014d8b23be7d259abd9 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c @@ -0,0 +1,313 @@ +/* + * File : ili9341.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2020, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2020-08-11 RT-Thread the first version + */ +#include "rtthread.h" +#include "stm32f4xx_hal.h" +#include "ili9341.h" + +/** + * @brief LCD Control pin + */ +#define LCD_NCS_PIN GPIO_PIN_2 +#define LCD_NCS_GPIO_PORT GPIOC +#define LCD_NCS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LCD_NCS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +/** + * @brief LCD Command/data pin + */ +#define LCD_WRX_PIN GPIO_PIN_13 +#define LCD_WRX_GPIO_PORT GPIOD +#define LCD_WRX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define LCD_WRX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() + +#define LCD_RDX_PIN GPIO_PIN_12 +#define LCD_RDX_GPIO_PORT GPIOD +#define LCD_RDX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define LCD_RDX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() + +/* Maximum Timeout values for flags waiting loops */ +#define SPIx_TIMEOUT_MAX ((uint32_t)0x1000) + +/* Chip Select macro definition */ +#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_RESET) +#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_SET) + +/* Set WRX High to send data */ +#define LCD_WRX_LOW() HAL_GPIO_WritePin(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PIN_RESET) +#define LCD_WRX_HIGH() HAL_GPIO_WritePin(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PIN_SET) + +/* Set WRX High to send data */ +#define LCD_RDX_LOW() HAL_GPIO_WritePin(LCD_RDX_GPIO_PORT, LCD_RDX_PIN, GPIO_PIN_RESET) +#define LCD_RDX_HIGH() HAL_GPIO_WritePin(LCD_RDX_GPIO_PORT, LCD_RDX_PIN, GPIO_PIN_SET) + +static uint8_t Is_LCD_IO_Initialized = 0; +static SPI_HandleTypeDef SpiHandle; + +/** + * @brief SPIx Bus initialization + */ +static void SPIx_Init(void) +{ + if(HAL_SPI_GetState(&SpiHandle) == HAL_SPI_STATE_RESET) + { + /* SPI configuration -----------------------------------------------------*/ + SpiHandle.Instance = SPI5; + /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz) + */ + SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + + /* On STM32F429I-Discovery, LCD ID cannot be read then keep a common configuration */ + /* for LCD and GYRO (SPI_DIRECTION_2LINES) */ + /* Note: To read a register a LCD, SPI_DIRECTION_1LINE should be set */ + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE; + SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW; + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + SpiHandle.Init.CRCPolynomial = 7; + SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT; + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + SpiHandle.Init.NSS = SPI_NSS_SOFT; + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; + SpiHandle.Init.Mode = SPI_MODE_MASTER; + + HAL_SPI_Init(&SpiHandle); + } +} + +/** + * @brief Configures the LCD_SPI interface. + */ +static void LCD_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + if(Is_LCD_IO_Initialized == 0) + { + Is_LCD_IO_Initialized = 1; + + /* Configure NCS in Output Push-Pull mode */ + LCD_WRX_GPIO_CLK_ENABLE(); + GPIO_InitStructure.Pin = LCD_WRX_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(LCD_WRX_GPIO_PORT, &GPIO_InitStructure); + + LCD_RDX_GPIO_CLK_ENABLE(); + GPIO_InitStructure.Pin = LCD_RDX_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(LCD_RDX_GPIO_PORT, &GPIO_InitStructure); + + /* Configure the LCD Control pins ----------------------------------------*/ + LCD_NCS_GPIO_CLK_ENABLE(); + + /* Configure NCS in Output Push-Pull mode */ + GPIO_InitStructure.Pin = LCD_NCS_PIN; + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); + + /* Set or Reset the control line */ + LCD_CS_LOW(); + LCD_CS_HIGH(); + + SPIx_Init(); + } +} + +/** + * @brief Writes data to the selected LCD register. + * @param data: data to lcd. + * @retval None + */ +static void ili9341_write_data(uint16_t data) +{ + /* Set WRX to send data */ + LCD_WRX_HIGH(); + + /* Reset LCD control line(/CS) and Send data */ + LCD_CS_LOW(); + + HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX); + + /* Deselect: Chip Select high */ + LCD_CS_HIGH(); +} + +/** + * @brief Writes to the selected LCD register. + * @param reg: address of the selected register. + * @retval None + */ +static void ili9341_write_register(uint8_t reg) +{ + /* Reset WRX to send command */ + LCD_WRX_LOW(); + + /* Reset LCD control line(/CS) and Send command */ + LCD_CS_LOW(); + + HAL_SPI_Transmit(&SpiHandle, (uint8_t*) ®, 1, SPIx_TIMEOUT_MAX); + + /* Deselect: Chip Select high */ + LCD_CS_HIGH(); +} + +/** + * @brief Power on the LCD. + * @param None + * @retval int + */ +int ili9341_hw_init(void) +{ + /* Initialize ILI9341 low level bus layer ----------------------------------*/ + LCD_GPIO_Init(); + + /* Configure LCD */ + ili9341_write_register(0xCA); + ili9341_write_data(0xC3); + ili9341_write_data(0x08); + ili9341_write_data(0x50); + ili9341_write_register(LCD_POWERB); + ili9341_write_data(0x00); + ili9341_write_data(0xC1); + ili9341_write_data(0x30); + ili9341_write_register(LCD_POWER_SEQ); + ili9341_write_data(0x64); + ili9341_write_data(0x03); + ili9341_write_data(0x12); + ili9341_write_data(0x81); + ili9341_write_register(LCD_DTCA); + ili9341_write_data(0x85); + ili9341_write_data(0x00); + ili9341_write_data(0x78); + ili9341_write_register(LCD_POWERA); + ili9341_write_data(0x39); + ili9341_write_data(0x2C); + ili9341_write_data(0x00); + ili9341_write_data(0x34); + ili9341_write_data(0x02); + ili9341_write_register(LCD_PRC); + ili9341_write_data(0x20); + ili9341_write_register(LCD_DTCB); + ili9341_write_data(0x00); + ili9341_write_data(0x00); + ili9341_write_register(LCD_FRMCTR1); + ili9341_write_data(0x00); + ili9341_write_data(0x1B); + ili9341_write_register(LCD_DFC); + ili9341_write_data(0x0A); + ili9341_write_data(0xA2); + ili9341_write_register(LCD_POWER1); + ili9341_write_data(0x10); + ili9341_write_register(LCD_POWER2); + ili9341_write_data(0x10); + ili9341_write_register(LCD_VCOM1); + ili9341_write_data(0x45); + ili9341_write_data(0x15); + ili9341_write_register(LCD_VCOM2); + ili9341_write_data(0x90); + ili9341_write_register(LCD_MAC); + ili9341_write_data(0xC8); + ili9341_write_register(LCD_3GAMMA_EN); + ili9341_write_data(0x00); + ili9341_write_register(LCD_RGB_INTERFACE); + ili9341_write_data(0xC2); + ili9341_write_register(LCD_DFC); + ili9341_write_data(0x0A); + ili9341_write_data(0xA7); + ili9341_write_data(0x27); + ili9341_write_data(0x04); + + /* Colomn address set */ + ili9341_write_register(LCD_COLUMN_ADDR); + ili9341_write_data(0x00); + ili9341_write_data(0x00); + ili9341_write_data(0x00); + ili9341_write_data(0xEF); + /* Page address set */ + ili9341_write_register(LCD_PAGE_ADDR); + ili9341_write_data(0x00); + ili9341_write_data(0x00); + ili9341_write_data(0x01); + ili9341_write_data(0x3F); + ili9341_write_register(LCD_INTERFACE); + ili9341_write_data(0x01); + ili9341_write_data(0x00); + ili9341_write_data(0x06); + + ili9341_write_register(LCD_GRAM); + rt_thread_mdelay(20); + + ili9341_write_register(LCD_GAMMA); + ili9341_write_data(0x01); + + ili9341_write_register(LCD_PGAMMA); + ili9341_write_data(0x0F); + ili9341_write_data(0x29); + ili9341_write_data(0x24); + ili9341_write_data(0x0C); + ili9341_write_data(0x0E); + ili9341_write_data(0x09); + ili9341_write_data(0x4E); + ili9341_write_data(0x78); + ili9341_write_data(0x3C); + ili9341_write_data(0x09); + ili9341_write_data(0x13); + ili9341_write_data(0x05); + ili9341_write_data(0x17); + ili9341_write_data(0x11); + ili9341_write_data(0x00); + ili9341_write_register(LCD_NGAMMA); + ili9341_write_data(0x00); + ili9341_write_data(0x16); + ili9341_write_data(0x1B); + ili9341_write_data(0x04); + ili9341_write_data(0x11); + ili9341_write_data(0x07); + ili9341_write_data(0x31); + ili9341_write_data(0x33); + ili9341_write_data(0x42); + ili9341_write_data(0x05); + ili9341_write_data(0x0C); + ili9341_write_data(0x0A); + ili9341_write_data(0x28); + ili9341_write_data(0x2F); + ili9341_write_data(0x0F); + + ili9341_write_register(LCD_SLEEP_OUT); + rt_thread_mdelay(20); + ili9341_write_register(LCD_DISPLAY_ON); + /* GRAM start writing */ + ili9341_write_register(LCD_GRAM); + + return 0; +} +INIT_DEVICE_EXPORT(ili9341_hw_init); + + + diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h new file mode 100644 index 0000000000000000000000000000000000000000..b4c59e6ffab0092c7b1b2dbbe4e3b93fc79c6f58 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h @@ -0,0 +1,145 @@ +/* + * File : ili9341.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2020, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2020-08-11 RT-Thread the first version + */ +#ifndef __ILI9341_H +#define __ILI9341_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief ILI9341 chip IDs + */ +#define ILI9341_ID 0x9341 + +/** + * @brief ILI9341 Registers + */ + +/* Level 1 Commands */ +#define LCD_SWRESET 0x01 /* Software Reset */ +#define LCD_READ_DISPLAY_ID 0x04 /* Read display identification information */ +#define LCD_RDDST 0x09 /* Read Display Status */ +#define LCD_RDDPM 0x0A /* Read Display Power Mode */ +#define LCD_RDDMADCTL 0x0B /* Read Display MADCTL */ +#define LCD_RDDCOLMOD 0x0C /* Read Display Pixel Format */ +#define LCD_RDDIM 0x0D /* Read Display Image Format */ +#define LCD_RDDSM 0x0E /* Read Display Signal Mode */ +#define LCD_RDDSDR 0x0F /* Read Display Self-Diagnostic Result */ +#define LCD_SPLIN 0x10 /* Enter Sleep Mode */ +#define LCD_SLEEP_OUT 0x11 /* Sleep out register */ +#define LCD_PTLON 0x12 /* Partial Mode ON */ +#define LCD_NORMAL_MODE_ON 0x13 /* Normal Display Mode ON */ +#define LCD_DINVOFF 0x20 /* Display Inversion OFF */ +#define LCD_DINVON 0x21 /* Display Inversion ON */ +#define LCD_GAMMA 0x26 /* Gamma register */ +#define LCD_DISPLAY_OFF 0x28 /* Display off register */ +#define LCD_DISPLAY_ON 0x29 /* Display on register */ +#define LCD_COLUMN_ADDR 0x2A /* Colomn address register */ +#define LCD_PAGE_ADDR 0x2B /* Page address register */ +#define LCD_GRAM 0x2C /* GRAM register */ +#define LCD_RGBSET 0x2D /* Color SET */ +#define LCD_RAMRD 0x2E /* Memory Read */ +#define LCD_PLTAR 0x30 /* Partial Area */ +#define LCD_VSCRDEF 0x33 /* Vertical Scrolling Definition */ +#define LCD_TEOFF 0x34 /* Tearing Effect Line OFF */ +#define LCD_TEON 0x35 /* Tearing Effect Line ON */ +#define LCD_MAC 0x36 /* Memory Access Control register*/ +#define LCD_VSCRSADD 0x37 /* Vertical Scrolling Start Address */ +#define LCD_IDMOFF 0x38 /* Idle Mode OFF */ +#define LCD_IDMON 0x39 /* Idle Mode ON */ +#define LCD_PIXEL_FORMAT 0x3A /* Pixel Format register */ +#define LCD_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */ +#define LCD_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */ +#define LCD_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */ +#define LCD_GET_SCANLINE 0x45 /* Get Scanline */ +#define LCD_WDB 0x51 /* Write Brightness Display register */ +#define LCD_RDDISBV 0x52 /* Read Display Brightness */ +#define LCD_WCD 0x53 /* Write Control Display register*/ +#define LCD_RDCTRLD 0x54 /* Read CTRL Display */ +#define LCD_WRCABC 0x55 /* Write Content Adaptive Brightness Control */ +#define LCD_RDCABC 0x56 /* Read Content Adaptive Brightness Control */ +#define LCD_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */ +#define LCD_READ_CABC 0x5F /* Read CABC Minimum Brightness */ +#define LCD_READ_ID1 0xDA /* Read ID1 */ +#define LCD_READ_ID2 0xDB /* Read ID2 */ +#define LCD_READ_ID3 0xDC /* Read ID3 */ + +/* Level 2 Commands */ +#define LCD_RGB_INTERFACE 0xB0 /* RGB Interface Signal Control */ +#define LCD_FRMCTR1 0xB1 /* Frame Rate Control (In Normal Mode) */ +#define LCD_FRMCTR2 0xB2 /* Frame Rate Control (In Idle Mode) */ +#define LCD_FRMCTR3 0xB3 /* Frame Rate Control (In Partial Mode) */ +#define LCD_INVTR 0xB4 /* Display Inversion Control */ +#define LCD_BPC 0xB5 /* Blanking Porch Control register */ +#define LCD_DFC 0xB6 /* Display Function Control register */ +#define LCD_ETMOD 0xB7 /* Entry Mode Set */ +#define LCD_BACKLIGHT1 0xB8 /* Backlight Control 1 */ +#define LCD_BACKLIGHT2 0xB9 /* Backlight Control 2 */ +#define LCD_BACKLIGHT3 0xBA /* Backlight Control 3 */ +#define LCD_BACKLIGHT4 0xBB /* Backlight Control 4 */ +#define LCD_BACKLIGHT5 0xBC /* Backlight Control 5 */ +#define LCD_BACKLIGHT7 0xBE /* Backlight Control 7 */ +#define LCD_BACKLIGHT8 0xBF /* Backlight Control 8 */ +#define LCD_POWER1 0xC0 /* Power Control 1 register */ +#define LCD_POWER2 0xC1 /* Power Control 2 register */ +#define LCD_VCOM1 0xC5 /* VCOM Control 1 register */ +#define LCD_VCOM2 0xC7 /* VCOM Control 2 register */ +#define LCD_NVMWR 0xD0 /* NV Memory Write */ +#define LCD_NVMPKEY 0xD1 /* NV Memory Protection Key */ +#define LCD_RDNVM 0xD2 /* NV Memory Status Read */ +#define LCD_READ_ID4 0xD3 /* Read ID4 */ +#define LCD_PGAMMA 0xE0 /* Positive Gamma Correction register */ +#define LCD_NGAMMA 0xE1 /* Negative Gamma Correction register */ +#define LCD_DGAMCTRL1 0xE2 /* Digital Gamma Control 1 */ +#define LCD_DGAMCTRL2 0xE3 /* Digital Gamma Control 2 */ +#define LCD_INTERFACE 0xF6 /* Interface control register */ + +/* Extend register commands */ +#define LCD_POWERA 0xCB /* Power control A register */ +#define LCD_POWERB 0xCF /* Power control B register */ +#define LCD_DTCA 0xE8 /* Driver timing control A */ +#define LCD_DTCB 0xEA /* Driver timing control B */ +#define LCD_POWER_SEQ 0xED /* Power on sequence register */ +#define LCD_3GAMMA_EN 0xF2 /* 3 Gamma enable register */ +#define LCD_PRC 0xF7 /* Pump ratio control register */ + +/* Size of read registers */ +#define LCD_READ_ID4_SIZE 3 /* Size of Read ID4 */ + + +/** @defgroup ILI9341_Exported_Functions + * @{ + */ +int ili9341_hw_init(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ILI9341_H */ + + diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h new file mode 100644 index 0000000000000000000000000000000000000000..6f8112cc1bd0d79917b9702dd3fcc043369d1daf --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-08 bernard The first version for STM32F429 DISCO + */ + +#ifndef __LCD_PORT_H__ +#define __LCD_PORT_H__ + +/* 240 * 320 */ +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BITS_PER_PIXEL 16 +#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) +#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 + +#define LCD_HSYNC_WIDTH 10 +#define LCD_VSYNC_HEIGHT 2 +#define LCD_HBP 20 +#define LCD_VBP 2 +#define LCD_HFP 10 +#define LCD_VFP 5 + +#define LCD_BACKLIGHT_USING_GPIO +#define LCD_BL_GPIO_NUM GET_PIN(D, 7) +#define LCD_DISP_GPIO_NUM GET_PIN(D, 4) + +#endif /* __LCD_PORT_H__ */ diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h new file mode 100644 index 0000000000000000000000000000000000000000..77c80f58ffebfd6dfd186e48cb8c12dfde421265 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-08 bernard The first version for STM32F429 DISCO + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ +/* Bank1 or Bank2 */ +#define SDRAM_TARGET_BANK 2 +/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */ +#define SDRAM_BANK_ADDR ((uint32_t)0XD0000000) +/* data width: 8, 16, 32 */ +#define SDRAM_DATA_WIDTH 16 +/* column bit numbers: 8, 9, 10, 11 */ +#define SDRAM_COLUMN_BITS 8 +/* row bit numbers: 11, 12, 13 */ +#define SDRAM_ROW_BITS 12 +/* cas latency clock number: 1, 2, 3 */ +#define SDRAM_CAS_LATENCY 3 +/* read pipe delay: 0, 1, 2 */ +#define SDRAM_RPIPE_DELAY 1 +/* clock divid: 2, 3 */ +#define SDCLOCK_PERIOD 2 +/* refresh rate counter */ +#define SDRAM_REFRESH_COUNT ((uint32_t)0x056A) +#define SDRAM_SIZE ((uint32_t)0x800000) + +/* Timing configuration for IS42S16400J */ +/* 90 MHz of SD clock frequency (180MHz/2) */ +/* TMRD: 2 Clock cycles */ +#define LOADTOACTIVEDELAY 2 +/* TXSR: 7x11.90ns */ +#define EXITSELFREFRESHDELAY 7 +/* TRAS: 4x11.90ns */ +#define SELFREFRESHTIME 4 +/* TRC: 7x11.90ns */ +#define ROWCYCLEDELAY 7 +/* TWR: 2 Clock cycles */ +#define WRITERECOVERYTIME 2 +/* TRP: 2x11.90ns */ +#define RPDELAY 2 +/* TRCD: 2x11.90ns */ +#define RCDDELAY 2 + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +#endif diff --git a/bsp/stm32/stm32f429-st-disco/rtconfig.h b/bsp/stm32/stm32f429-st-disco/rtconfig.h index 2837c2f767fc64827c62ac3bdc089097b9cf1db6..9f5b2c77c4c88a1d167949b829045b5aabc4a9d9 100644 --- a/bsp/stm32/stm32f429-st-disco/rtconfig.h +++ b/bsp/stm32/stm32f429-st-disco/rtconfig.h @@ -26,12 +26,13 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS /* Memory Management */ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP -#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP_AS_HEAP #define RT_USING_HEAP /* Kernel Device Object */ @@ -40,7 +41,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 +#define RT_VER_NUM 0x40003 #define ARCH_ARM #define RT_USING_CPU_FFS #define ARCH_ARM_CORTEX_M @@ -69,6 +70,7 @@ #define FINSH_CMD_SIZE 80 #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -90,13 +92,15 @@ #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN - +#define RT_USING_SPI /* Using USB */ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_USING_PTHREADS +#define PTHREAD_NUM_MAX 8 #define RT_USING_POSIX /* Network */ @@ -158,6 +162,12 @@ /* samples: kernel and components samples */ + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F4 @@ -165,11 +175,18 @@ #define SOC_STM32F429ZI +/* Onboard Peripheral Drivers */ + +#define BSP_USING_SDRAM + /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART1 +#define BSP_USING_FMC +#define BSP_USING_LCD +#define BSP_USING_LTDC /* Board extended module Drivers */ diff --git a/bsp/stm32/stm32h743-st-nucleo/board/SConscript b/bsp/stm32/stm32h743-st-nucleo/board/SConscript index 4a4c806804885c0bd77f680732ca7cea5e51df91..86e530023b635df84cdcfa3502b74449a14a851d 100644 --- a/bsp/stm32/stm32h743-st-nucleo/board/SConscript +++ b/bsp/stm32/stm32h743-st-nucleo/board/SConscript @@ -1,6 +1,8 @@ import rtconfig from building import * +Import('SDK_LIB') + cwd = GetCurrentDir() # add the general drivers. @@ -10,12 +12,14 @@ src += Glob('CubeMX_Config/Src/stm32h7xx_hal_msp.c') path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] +startup_path_prefix = SDK_LIB + if rtconfig.CROSS_TOOL == 'gcc': - src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s'] + src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s'] elif rtconfig.CROSS_TOOL == 'keil': - src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s'] + src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s'] elif rtconfig.CROSS_TOOL == 'iar': - src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s'] + src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s'] # STM32H743xx || STM32H750xx || STM32F753xx # You can select chips from the list above diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/SConscript b/bsp/stm32/stm32h750-armfly-h7-tool/board/SConscript index 20c211147fc8cb0509847c69c5088e6cd90724f7..5e388d504736c360ba5a5b93ecc8ab0785209110 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/board/SConscript +++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/SConscript @@ -17,11 +17,11 @@ path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] if rtconfig.CROSS_TOOL == 'gcc': - src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s'] + src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s'] elif rtconfig.CROSS_TOOL == 'keil': - src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s'] + src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s'] elif rtconfig.CROSS_TOOL == 'iar': - src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s'] + src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s'] # STM32H743xx || STM32H750xx || STM32F753xx # You can select chips from the list above diff --git a/bsp/stm32/stm32mp157a-st-ev1/.config b/bsp/stm32/stm32mp157a-st-ev1/.config new file mode 100644 index 0000000000000000000000000000000000000000..4f6a2ab164d5794d1b3c5a21e612f202a125670b --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.config @@ -0,0 +1,450 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32MP1=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32MP157A=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_STLINK_TO_USART=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_WWDG is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_UART3_RX_USING_DMA is not set +CONFIG_BSP_USING_UART4=y +# CONFIG_BSP_UART4_RX_USING_DMA is not set +# CONFIG_BSP_UART4_TX_USING_DMA is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_LPTIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32mp157a-st-ev1/.cproject b/bsp/stm32/stm32mp157a-st-ev1/.cproject new file mode 100644 index 0000000000000000000000000000000000000000..942edf4226eaa33cb7dcaf44fc712a1b66745137 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.cproject @@ -0,0 +1,208 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/.gitignore b/bsp/stm32/stm32mp157a-st-ev1/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7221bde019df6157cbf9e42ef5ab8a78420e3b68 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32mp157a-st-ev1/.project b/bsp/stm32/stm32mp157a-st-ev1/.project new file mode 100644 index 0000000000000000000000000000000000000000..54df11d83de3693eaff5e02029eb1851b7436ad6 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.project @@ -0,0 +1,29 @@ + + + stm32mp157a-st-ev1 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/.settings/.rtmenus b/bsp/stm32/stm32mp157a-st-ev1/.settings/.rtmenus new file mode 100644 index 0000000000000000000000000000000000000000..783439940842712c65369df2165e5cef9281bf14 Binary files /dev/null and b/bsp/stm32/stm32mp157a-st-ev1/.settings/.rtmenus differ diff --git a/bsp/stm32/stm32mp157a-st-ev1/.settings/language.settings.xml b/bsp/stm32/stm32mp157a-st-ev1/.settings/language.settings.xml new file mode 100644 index 0000000000000000000000000000000000000000..a2f05404a046f8bec10b694bc6ba1df3f5106f7c --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/.settings/org.eclipse.core.runtime.prefs b/bsp/stm32/stm32mp157a-st-ev1/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000000000000000000000000000000000000..b36aae6fb2a4e8309f6c2299be466d8774582ed4 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 diff --git a/bsp/stm32/stm32mp157a-st-ev1/.settings/projcfg.ini b/bsp/stm32/stm32mp157a-st-ev1/.settings/projcfg.ini new file mode 100644 index 0000000000000000000000000000000000000000..caa6c69570da951acd7a07f36ef41f797680345a --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.settings/projcfg.ini @@ -0,0 +1,8 @@ +#RT-Thread Studio Project Configuration +#Thu Jul 23 15:17:50 CST 2020 +mcu_name=STM32MP157A +hardware_adapter=ST-LINK +mcu_base_nano_proj=true +selected_rtt_version=latest +project_base_bsp=true +cfg_version=v2.0 diff --git a/bsp/stm32/stm32mp157a-st-ev1/.settings/stm32mp1.JLink.Debug.rttlaunch b/bsp/stm32/stm32mp157a-st-ev1/.settings/stm32mp1.JLink.Debug.rttlaunch new file mode 100644 index 0000000000000000000000000000000000000000..85acda0c11bf806cdd2be84695c33bbf01de17a5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.settings/stm32mp1.JLink.Debug.rttlaunch @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/.settings/stm32mp1.STLink.Debug.rttlaunch b/bsp/stm32/stm32mp157a-st-ev1/.settings/stm32mp1.STLink.Debug.rttlaunch new file mode 100644 index 0000000000000000000000000000000000000000..37b2bf8f69d9ea91f465b2304c634314f03fda28 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/.settings/stm32mp1.STLink.Debug.rttlaunch @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/Kconfig b/bsp/stm32/stm32mp157a-st-ev1/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7a400db91f4a82292908c8b2b99e87e4193f78d0 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/stm32/stm32mp157a-st-ev1/README.md b/bsp/stm32/stm32mp157a-st-ev1/README.md new file mode 100644 index 0000000000000000000000000000000000000000..7a38b4d7fc3f15f74e4eefbf8dabdfb446a8a857 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/README.md @@ -0,0 +1,165 @@ +# STM32MP157A-EV1 BSP (Board Support Package) Execution Instruction + +[中文页](README_zh.md) | + +## Introduction + +This document records the execution instruction of the BSP (board support package) provided by the RT-Thread development team for the STM32MP157A-EV1 development board. + +The document is covered in three parts: + +- STM32MP157A-EV1 Board Resources Introduction + +- Quickly Get Started + +- Advanced Features + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## STM32MP157A-EV1 Board Resources Introduction + +The STM32MP157A-EV1 is a development board based on a dual Cortex-A7 and Cortex-M4 core. The Cortex-A7 core operates at 650 MHZ and the Cortex-M4 operates at 209MHZ. There is no Flash inside the STM32MP157A. + +![board](figures/board.png) + +The mainly-used **on-board resources** are shown as follows: + +- MCU : STM32MP157AAAx +- Common peripherals: + - 4 LEDs: LD4(PD8), LD5(PD9), LD2(PA13), LD3(PA14) + - 4 Buttons: WAKE_UP, RESET (NRST), USER1(PA13), USER2 (PA14) +- Common-used interface: USB, SD card, Ethernet, MIPI, USB HOST, Audio, HDMI, Arduino. +- Debug interface: Standard JTAG/SWD. + +For more details about this board, please refer to the ST official documentation: + +[STM32MP157A-EV1 Development board introduction](https://www.st.com/content/st_com/zh/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-eval-boards/stm32mp157a-ev1.html) + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + +| On-board Peripheral | **Support** | **Remark** | +| :----------------------------- | :---------: | :--------------: | +| USB TO UART | YES | | +| PMIC | NO | | +| CAMERA | NO | OV5640 | +| MFX | NO | | +| FMC | NO | MT25F8G08A8ACAH4 | +| QSPI FLASH | NO | MX25L51245G | +| OpenAMP | NO | | +| POWER | NO | | +| SD Card (SDMMC1) | NO | | +| EMMC(SDMMC2) | NO | | +| ETH | NO | | +| AUDIO | NO | WM8994 | +| **On-chip Peripheral Drivers** | **Support** | **Remark** | +| GPIO | YES | | +| UART | YES | UART4 (ST-Link) | +| EXTI | YES | | +| SPI | YES | | +| TIM | YES | | +| LPTIM | YES | | +| I2C | YES | Software | +| ADC | YES | | +| DAC | YES | | +| WWDG | YES | | +| MDMA | NO | | +| SPDIFRX | NO | | +| DFSDM | NO | | +| PWM | NO | | +| FDCAN | NO | | +| CRC | NO | | +| RNG | NO | | +| HASH | NO | | + +## Execution Instruction + +### Quickly Get Started + +This BSP provides MDK4,MDK5 and IAR projects for developers. Also support GCC development environment,Here's an example of the MDK5 development environment, to introduce how to run the system. + +#### Hardware Connection + +Use a USB cable to connect the development board to the PC and turn on the power switch. + +#### Compile And Download + +Double-click the project.uvprojx file, to open the MDK5 project, compile and download the program to the board. + +> By default, the project uses ST_LINK simulator to download the program, when the ST_LINK connects the board, clicking the download button can download the program to the board. + +#### Running Results + +After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, the orange LD4 will flash periodically. + +Connect the serial port of the board to PC, communicate with it via a serial terminal tool (115200-8-1-N). Restart the board and the startup information of RT-Thread will be observed: + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` + +#### Drivers + +##### 1. DAC + +- Open the [Env](https://www.rt-thread.io/download.html?download=Env) tool under this BSP; +- Enter the `menuconfig` command, enter the Hardware Drivers config and open DAC, save and exit; +- Enter the `scons --target=iar` command to regenerate project. + +###### Finsh + +Before you use a device, you need to find out if the device exists, and you can use the name of the DAC device that is enrolled with the command `dac probe` . As shown as follows. + +```c +msh />dac probe dac1 +probe dac1 success +``` + +Enable the channel of the device can use the command `dac enable` followed by the channel number. + + ```c +msh />dac probe dac1 +probe dac1 success + ``` + +Set up the data of the channel for a DAC device can use the command `dac write` followed by the channel number. + +```c +msh />dac write 1 1000 +dac1 channel 1 write value is 1000 +``` + +Disable the channel of the device can use the command `dac disable` followed by the channel number. + +```c +msh />dac disable 1 +dac1 channel 1 disable success +``` + +### Advanced Features + +This BSP only enables GPIO and serial port 4 by default. If need more advanced features, you need to configure the BSP with RT-Thread Env tools, as follows: + +- Open the [Env](https://www.rt-thread.io/download.html?download=Env) tool under this BSP; +- Enter the `menuconfig` command to configure the project, then save and exit; +- Enter the `pkgs --update` command to update the packages; +- Enter the `scons --target=iar`command to regenerate the project. + +## Notes + +- Before downloading the program, set the board to the mode of "Engineering Mode". The BOOT switch sets to BOOT0=0,BOOT1 = 0 and BOOT2=1, as shown below: + +![boot](figures/boot.png) + +- If need to reburn the program, please reset the development board. + +## Contact Information + +accendant: + +- [liukang](https://github.com/thread-liu) diff --git a/bsp/stm32/stm32mp157a-st-ev1/README_zh.md b/bsp/stm32/stm32mp157a-st-ev1/README_zh.md new file mode 100644 index 0000000000000000000000000000000000000000..e4c41f7eb27d7901bad9a3bf7e5d63d0d38dad75 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/README_zh.md @@ -0,0 +1,179 @@ +# STM32MP157A-EV1 开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 STM32MP157A-EV1 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32MP157A-EV1 是 ST 推出的一款基于双 Cortex-A7 + Cortex-M4 内核的开发板。Cortex-A7 核工作频率为 650MHZ，Cortex-M4 工作频率为 209MHZ。 + +开发板外观如下图所示： + +​ ![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32MP157AAAx +- 常用外设 + - LED：4个 ，LD4(PD8), LD5(PD9), LD2(PA13), LD3(PA14) + - 按键，4个，WAKE_UP, RESET (NRST), USER1(PA13), USER2 (PA14) +- 常用接口：USB 转串口、SD 卡接口、以太网接口、MIPI接口、USB HOST、Audio、HDMI、Arduino +- 调试接口，标准 JTAG/SWD + +开发板更多详细信息请参考 ST 官方文档 [STM32MP157A-DK1 开发板介绍](https://www.st.com/content/st_com/zh/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/stm32mp157a-dk1.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------- | :----------: | :-------------: | +| USB 转串口 | 支持 | | +| PMIC | 暂不支持 | ST 电源管理 IC | +| 摄像头 | 暂不支持 | OV5640 | +| MFX | 暂不支持 | ST 多功能拓展器 | +| FMC | 暂不支持 | NAND FLASH | +| QSPI FLASH | 暂不支持 | MX25L51245G | +| OpenAMP | 暂不支持 | 双核通讯 | +| 低功耗电源管理 | 暂不支持 | | +| SD卡 | 暂不支持 | SDMMC1 | +| eMMC | 暂不支持 | SDMMC2 | +| 以太网 | 暂不支持 | 千兆以太网卡 | +| 音频接口 | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART4 (ST-Link) | +| EXTI | 支持 | | +| SPI | 支持 | | +| TIM | 支持 | | +| LPTIM | 支持 | | +| I2C | 支持 | 软件 | +| ADC | 支持 | | +| DAC | 支持 | | +| WWDG | 支持 | | +| MDMA | 暂不支持 | | +| SPDIFRX | 暂不支持 | | +| DFSDM | 暂不支持 | | +| PWM | 暂不支持 | | +| FDCAN | 暂不支持 | | +| CRC | 暂不支持 | | +| RNG | 暂不支持 | | +| HASH | 暂不支持 | | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，橙色 LD4 会周期性闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），可以看到 RT-Thread 的输出信息: + +> 注：正点原子开发板 在使用终端工具如：PuTTy、XShell 时，会出现系统不能启动的问题，推荐使用串口调试助手如：sscom + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +#### 驱动使用 +##### 1. DAC + +1. 在 bsp 下打开 env 工具； +2. 输入`menuconfig`命令， 进入 Hardware Drivers config 打开 dac，保存并退出； +3. 输入 `scons --target=iar` 命令重新生成工程； + +###### Finsh + +在使用设备前，需要先查找设备是否存在，可以使用命令 `dac probe` 后面跟注册的 DAC 设备的名称。如下所示： + +```c +msh />dac probe dac1 +probe dac1 success +``` + +使能设备的某个通道可以使用命令 `dac enable` 后面跟通道号。 + +```c +msh />dac enable 1 +dac1 channel 1 enables success +``` + +设置 DAC 设备某个通道的数据可以使用命令 `dac write` 后面跟通道号。 + +```c +msh />dac write 1 1000 +dac1 channel 1 write value is 1000 +``` + +关闭设备的某个通道可以使用命令 `dac disable` 后面跟通道号。 + +```c +msh />dac disable 1 +dac1 channel 1 disable success +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口4 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +1. 下载程序前，将开发板设置为 "Engineering Mode" 模式。 在 DK1 开发板上，将底下的BOOT开关设成 BOOT0=0，BOOT2=1状态，就进入"Engineering Mode"，如下图所示： + + ​ boot + +2. 再次烧写程序时，需要复位开发板。 + +## 联系人信息 + +维护人: + +- [liukang](https://github.com/thread-liu) + diff --git a/bsp/stm32/stm32mp157a-st-ev1/SConscript b/bsp/stm32/stm32mp157a-st-ev1/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..20f7689c53ca71a676748f79187f9764065466c5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32mp157a-st-ev1/SConstruct b/bsp/stm32/stm32mp157a-st-ev1/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..e1481a896b0d55ef0037989d313dd10c634b3a4d --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32MPxx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32mp157a-st-ev1/applications/SConscript b/bsp/stm32/stm32mp157a-st-ev1/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..04f04dd5435cd69acd90735e75caaffc0ba0d9ff --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32mp157a-st-ev1/applications/main.c b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..b38732f066590bbcf8bb1715ed44f236ee617790 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-05 thread-liu first version + */ + +#include +#include +#include + +/* defined the LD4 pin: PD8 */ +#define LED4_PIN GET_PIN(D, 8) + +int main(void) +{ + int count = 1; + /* set LD8 pin mode to output */ + rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED4_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED4_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000000000000000000000000000000000..d2274cfbc139d830bcc8c60c325c9e4791bcba79 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/.mxproject @@ -0,0 +1,14 @@ +[PreviousGenFiles] +HeaderPath=D:/3_work/GitRepositories/rt-thread/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc +HeaderFiles=stm32mp1xx_it.h;stm32mp1xx_hal_conf.h;main.h; +SourcePath=D:/3_work/GitRepositories/rt-thread/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src +SourceFiles=stm32mp1xx_it.c;stm32mp1xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_hsem.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cortex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h;Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dac.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dac_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_lptim.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_wwdg.h;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dac.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dac_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c;Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_hsem.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cortex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h;Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dac.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dac_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_lptim.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h;Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_wwdg.h;Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h;Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h;Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h;Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedIarFiles] +SourceFiles=..\CM4\Src\main.c;..\CM4\Src\stm32mp1xx_it.c;..\CM4\Src\stm32mp1xx_hal_msp.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dac.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dac_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c;..\Common/System/system_stm32mp1xx.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dac.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dac_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c;..\Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c;..\Common/System/system_stm32mp1xx.c;..\Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c;; +HeaderPath=..\Drivers\STM32MP1xx_HAL_Driver\Inc;..\Drivers\STM32MP1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32MP1xx\Include;..\Drivers\CMSIS\Include;..\CM4\Inc; +CDefines=CORE_CM4;CORE_CM4;CORE_CM4;USE_HAL_DRIVER;STM32MP157Axx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/main.h b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/main.h new file mode 100644 index 0000000000000000000000000000000000000000..9880e4f884d7cee85cbf308f4940066f92985404 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/main.h @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define STLINK_RX_Pin GPIO_PIN_11 +#define STLINK_RX_GPIO_Port GPIOG +#define STLINK_TX_Pin GPIO_PIN_2 +#define STLINK_TX_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..424bdc02a236d649c0e01396723c6b4d62ae222b --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h @@ -0,0 +1,396 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_HAL_CONF_H +#define STM32MP1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_DFSDM_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +#define HAL_HSEM_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_I2S_MODULE_ENABLED */ +#define HAL_IPCC_MODULE_ENABLED +/*#define HAL_IWDG_MODULE_ENABLED */ +#define HAL_LPTIM_MODULE_ENABLED +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TAMP_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +#define HAL_WWDG_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_CEC_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (24000000U) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority (lowest by default) */ + /* Warning: Must be set to higher priority for HAL_Delay() */ + /* and HAL_GetTick() usage under interrupt context */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 0U +#define DATA_CACHE_ENABLE 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32mp1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32mp1xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32mp1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32mp1xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32mp1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32mp1xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32mp1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32mp1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32mp1xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32mp1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32mp1xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32mp1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32mp1xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32mp1xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32mp1xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32mp1xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32mp1xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32mp1xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32mp1xx_hal_hcd.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32mp1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32mp1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IPCC_MODULE_ENABLED + #include "stm32mp1xx_hal_ipcc.h" +#endif /* HAL_IPCC_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32mp1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32mp1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32mp1xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32mp1xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32mp1xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32mp1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32mp1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32mp1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32mp1xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32mp1xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32mp1xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32mp1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32mp1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32mp1xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32mp1xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32mp1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32mp1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32mp1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_TAMP_MODULE_ENABLED + #include "stm32mp1xx_hal_tamp.h" +#endif /* HAL_TAMP_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32mp1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32mp1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32mp1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32mp1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_it.h b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_it.h new file mode 100644 index 0000000000000000000000000000000000000000..50c502088f88e3da9986847f565d271033822d3e --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Inc/stm32mp1xx_it.h @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32mp1xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32MP1xx_IT_H +#define __STM32MP1xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void WWDG1_IRQHandler(void); +void LPTIM1_IRQHandler(void); +void IPCC_RX1_IRQHandler(void); +void IPCC_TX1_IRQHandler(void); +void LPTIM2_IRQHandler(void); +void LPTIM3_IRQHandler(void); +void LPTIM4_IRQHandler(void); +void LPTIM5_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32MP1xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/main.c b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/main.c new file mode 100644 index 0000000000000000000000000000000000000000..32ea4f86c184f27f6ac2bee4bc418abee46f03ff --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/main.c @@ -0,0 +1,929 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc2; + +DAC_HandleTypeDef hdac1; + +IPCC_HandleTypeDef hipcc; + +LPTIM_HandleTypeDef hlptim1; +LPTIM_HandleTypeDef hlptim2; +LPTIM_HandleTypeDef hlptim3; +LPTIM_HandleTypeDef hlptim4; +LPTIM_HandleTypeDef hlptim5; + +SPI_HandleTypeDef hspi5; + +TIM_HandleTypeDef htim4; +TIM_HandleTypeDef htim14; +TIM_HandleTypeDef htim16; +TIM_HandleTypeDef htim17; + +UART_HandleTypeDef huart4; +UART_HandleTypeDef huart3; + +WWDG_HandleTypeDef hwwdg1; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +void PeriphCommonClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_IPCC_Init(void); +static void MX_SPI5_Init(void); +static void MX_TIM4_Init(void); +static void MX_TIM14_Init(void); +static void MX_TIM16_Init(void); +static void MX_TIM17_Init(void); +static void MX_UART4_Init(void); +static void MX_ADC2_Init(void); +static void MX_DAC1_Init(void); +static void MX_LPTIM1_Init(void); +static void MX_LPTIM2_Init(void); +static void MX_LPTIM3_Init(void); +static void MX_LPTIM4_Init(void); +static void MX_LPTIM5_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_WWDG1_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + if(IS_ENGINEERING_BOOT_MODE()) + { + /* Configure the system clock */ + SystemClock_Config(); + } + + if(IS_ENGINEERING_BOOT_MODE()) + { + /* Configure the peripherals common clocks */ + PeriphCommonClock_Config(); + } + + /* IPCC initialisation */ + MX_IPCC_Init(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_SPI5_Init(); + MX_TIM4_Init(); + MX_TIM14_Init(); + MX_TIM16_Init(); + MX_TIM17_Init(); + MX_UART4_Init(); + MX_ADC2_Init(); + MX_DAC1_Init(); + MX_LPTIM1_Init(); + MX_LPTIM2_Init(); + MX_LPTIM3_Init(); + MX_LPTIM4_Init(); + MX_LPTIM5_Init(); + MX_USART3_UART_Init(); + MX_WWDG1_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIG; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE; + RCC_OscInitStruct.PLL2.PLLM = 3; + RCC_OscInitStruct.PLL2.PLLN = 66; + RCC_OscInitStruct.PLL2.PLLP = 2; + RCC_OscInitStruct.PLL2.PLLQ = 1; + RCC_OscInitStruct.PLL2.PLLR = 1; + RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400; + RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE; + RCC_OscInitStruct.PLL3.PLLM = 2; + RCC_OscInitStruct.PLL3.PLLN = 34; + RCC_OscInitStruct.PLL3.PLLP = 2; + RCC_OscInitStruct.PLL3.PLLQ = 17; + RCC_OscInitStruct.PLL3.PLLR = 37; + RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1; + RCC_OscInitStruct.PLL3.PLLFRACV = 6660; + RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL; + RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** RCC Clock Config + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4 + |RCC_CLOCKTYPE_PCLK5; + RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2; + RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1; + RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3; + RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1; + RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2; + RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4; + RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Set the HSE division factor for RTC clock + */ + __HAL_RCC_RTC_HSEDIV(24); +} + +/** + * @brief Peripherals Common Clock Configuration + * @retval None + */ +void PeriphCommonClock_Config(void) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Initializes the common periph clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER; + PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC2 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC2_Init(void) +{ + + /* USER CODE BEGIN ADC2_Init 0 */ + + /* USER CODE END ADC2_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC2_Init 1 */ + + /* USER CODE END ADC2_Init 1 */ + /** Common config + */ + hadc2.Instance = ADC2; + hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; + hadc2.Init.Resolution = ADC_RESOLUTION_16B; + hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc2.Init.LowPowerAutoWait = DISABLE; + hadc2.Init.ContinuousConvMode = DISABLE; + hadc2.Init.NbrOfConversion = 1; + hadc2.Init.DiscontinuousConvMode = DISABLE; + hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; + hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; + hadc2.Init.OversamplingMode = DISABLE; + if (HAL_ADC_Init(&hadc2) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_6; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC2_Init 2 */ + + /* USER CODE END ADC2_Init 2 */ + +} + +/** + * @brief DAC1 Initialization Function + * @param None + * @retval None + */ +static void MX_DAC1_Init(void) +{ + + /* USER CODE BEGIN DAC1_Init 0 */ + + /* USER CODE END DAC1_Init 0 */ + + DAC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN DAC1_Init 1 */ + + /* USER CODE END DAC1_Init 1 */ + /** DAC Initialization + */ + hdac1.Instance = DAC1; + if (HAL_DAC_Init(&hdac1) != HAL_OK) + { + Error_Handler(); + } + /** DAC channel OUT1 config + */ + sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; + sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; + sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; + if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DAC1_Init 2 */ + + /* USER CODE END DAC1_Init 2 */ + +} + +/** + * @brief IPCC Initialization Function + * @param None + * @retval None + */ +static void MX_IPCC_Init(void) +{ + + /* USER CODE BEGIN IPCC_Init 0 */ + + /* USER CODE END IPCC_Init 0 */ + + /* USER CODE BEGIN IPCC_Init 1 */ + + /* USER CODE END IPCC_Init 1 */ + hipcc.Instance = IPCC; + if (HAL_IPCC_Init(&hipcc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN IPCC_Init 2 */ + + /* USER CODE END IPCC_Init 2 */ + +} + +/** + * @brief LPTIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM1_Init(void) +{ + + /* USER CODE BEGIN LPTIM1_Init 0 */ + + /* USER CODE END LPTIM1_Init 0 */ + + /* USER CODE BEGIN LPTIM1_Init 1 */ + + /* USER CODE END LPTIM1_Init 1 */ + hlptim1.Instance = LPTIM1; + hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; + if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM1_Init 2 */ + + /* USER CODE END LPTIM1_Init 2 */ + +} + +/** + * @brief LPTIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM2_Init(void) +{ + + /* USER CODE BEGIN LPTIM2_Init 0 */ + + /* USER CODE END LPTIM2_Init 0 */ + + /* USER CODE BEGIN LPTIM2_Init 1 */ + + /* USER CODE END LPTIM2_Init 1 */ + hlptim2.Instance = LPTIM2; + hlptim2.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim2.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim2.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim2.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim2.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim2.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + hlptim2.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + hlptim2.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; + if (HAL_LPTIM_Init(&hlptim2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM2_Init 2 */ + + /* USER CODE END LPTIM2_Init 2 */ + +} + +/** + * @brief LPTIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM3_Init(void) +{ + + /* USER CODE BEGIN LPTIM3_Init 0 */ + + /* USER CODE END LPTIM3_Init 0 */ + + /* USER CODE BEGIN LPTIM3_Init 1 */ + + /* USER CODE END LPTIM3_Init 1 */ + hlptim3.Instance = LPTIM3; + hlptim3.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim3.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim3.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim3.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim3.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim3.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + if (HAL_LPTIM_Init(&hlptim3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM3_Init 2 */ + + /* USER CODE END LPTIM3_Init 2 */ + +} + +/** + * @brief LPTIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM4_Init(void) +{ + + /* USER CODE BEGIN LPTIM4_Init 0 */ + + /* USER CODE END LPTIM4_Init 0 */ + + /* USER CODE BEGIN LPTIM4_Init 1 */ + + /* USER CODE END LPTIM4_Init 1 */ + hlptim4.Instance = LPTIM4; + hlptim4.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim4.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim4.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim4.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim4.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim4.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + if (HAL_LPTIM_Init(&hlptim4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM4_Init 2 */ + + /* USER CODE END LPTIM4_Init 2 */ + +} + +/** + * @brief LPTIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_LPTIM5_Init(void) +{ + + /* USER CODE BEGIN LPTIM5_Init 0 */ + + /* USER CODE END LPTIM5_Init 0 */ + + /* USER CODE BEGIN LPTIM5_Init 1 */ + + /* USER CODE END LPTIM5_Init 1 */ + hlptim5.Instance = LPTIM5; + hlptim5.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim5.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim5.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim5.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim5.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim5.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + if (HAL_LPTIM_Init(&hlptim5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPTIM5_Init 2 */ + + /* USER CODE END LPTIM5_Init 2 */ + +} + +/** + * @brief SPI5 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI5_Init(void) +{ + + /* USER CODE BEGIN SPI5_Init 0 */ + + /* USER CODE END SPI5_Init 0 */ + + /* USER CODE BEGIN SPI5_Init 1 */ + + /* USER CODE END SPI5_Init 1 */ + /* SPI5 parameter configuration*/ + hspi5.Instance = SPI5; + hspi5.Init.Mode = SPI_MODE_MASTER; + hspi5.Init.Direction = SPI_DIRECTION_2LINES_TXONLY; + hspi5.Init.DataSize = SPI_DATASIZE_4BIT; + hspi5.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi5.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi5.Init.NSS = SPI_NSS_SOFT; + hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; + hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi5.Init.TIMode = SPI_TIMODE_DISABLE; + hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi5.Init.CRCPolynomial = 0x0; + hspi5.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + hspi5.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; + hspi5.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; + hspi5.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + hspi5.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + hspi5.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; + hspi5.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; + hspi5.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; + hspi5.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; + hspi5.Init.IOSwap = SPI_IO_SWAP_DISABLE; + if (HAL_SPI_Init(&hspi5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI5_Init 2 */ + + /* USER CODE END SPI5_Init 2 */ + +} + +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 0; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + +} + +/** + * @brief TIM14 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM14_Init(void) +{ + + /* USER CODE BEGIN TIM14_Init 0 */ + + /* USER CODE END TIM14_Init 0 */ + + /* USER CODE BEGIN TIM14_Init 1 */ + + /* USER CODE END TIM14_Init 1 */ + htim14.Instance = TIM14; + htim14.Init.Prescaler = 0; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 0; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM14_Init 2 */ + + /* USER CODE END TIM14_Init 2 */ + +} + +/** + * @brief TIM16 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM16_Init(void) +{ + + /* USER CODE BEGIN TIM16_Init 0 */ + + /* USER CODE END TIM16_Init 0 */ + + /* USER CODE BEGIN TIM16_Init 1 */ + + /* USER CODE END TIM16_Init 1 */ + htim16.Instance = TIM16; + htim16.Init.Prescaler = 0; + htim16.Init.CounterMode = TIM_COUNTERMODE_UP; + htim16.Init.Period = 0; + htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim16.Init.RepetitionCounter = 0; + htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim16) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM16_Init 2 */ + + /* USER CODE END TIM16_Init 2 */ + +} + +/** + * @brief TIM17 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM17_Init(void) +{ + + /* USER CODE BEGIN TIM17_Init 0 */ + + /* USER CODE END TIM17_Init 0 */ + + /* USER CODE BEGIN TIM17_Init 1 */ + + /* USER CODE END TIM17_Init 1 */ + htim17.Instance = TIM17; + htim17.Init.Prescaler = 0; + htim17.Init.CounterMode = TIM_COUNTERMODE_UP; + htim17.Init.Period = 0; + htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim17.Init.RepetitionCounter = 0; + htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim17) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM17_Init 2 */ + + /* USER CODE END TIM17_Init 2 */ + +} + +/** + * @brief UART4 Initialization Function + * @param None + * @retval None + */ +static void MX_UART4_Init(void) +{ + + /* USER CODE BEGIN UART4_Init 0 */ + + /* USER CODE END UART4_Init 0 */ + + /* USER CODE BEGIN UART4_Init 1 */ + + /* USER CODE END UART4_Init 1 */ + huart4.Instance = UART4; + huart4.Init.BaudRate = 115200; + huart4.Init.WordLength = UART_WORDLENGTH_8B; + huart4.Init.StopBits = UART_STOPBITS_1; + huart4.Init.Parity = UART_PARITY_NONE; + huart4.Init.Mode = UART_MODE_TX_RX; + huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart4.Init.OverSampling = UART_OVERSAMPLING_16; + huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart4) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART4_Init 2 */ + + /* USER CODE END UART4_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief WWDG1 Initialization Function + * @param None + * @retval None + */ +static void MX_WWDG1_Init(void) +{ + + /* USER CODE BEGIN WWDG1_Init 0 */ + + /* USER CODE END WWDG1_Init 0 */ + + /* USER CODE BEGIN WWDG1_Init 1 */ + + /* USER CODE END WWDG1_Init 1 */ + hwwdg1.Instance = WWDG1; + hwwdg1.Init.Prescaler = WWDG_PRESCALER_8; + hwwdg1.Init.Window = 64; + hwwdg1.Init.Counter = 64; + hwwdg1.Init.EWIMode = WWDG_EWI_DISABLE; + if (HAL_WWDG_Init(&hwwdg1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN WWDG1_Init 2 */ + + /* USER CODE END WWDG1_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c new file mode 100644 index 0000000000000000000000000000000000000000..efb81996fad1a5c6a2ad8d9eb6324aed43d28ca4 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -0,0 +1,987 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32mp1xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ +#include "stpmic.h" +#include "rtconfig.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_HSEM_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + if(IS_ENGINEERING_BOOT_MODE()) + { +#if defined(BSP_USING_ADC) || defined(BSP_USING_DAC) + /* Configure PMIC */ + BSP_PMIC_Init(); + BSP_PMIC_InitRegulators(); + + __HAL_RCC_VREF_CLK_ENABLE(); + HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE); + HAL_SYSCFG_EnableVREFBUF(); +#endif + } + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hadc->Instance==ADC2) + { + /* USER CODE BEGIN ADC2_MspInit 0 */ + + /* USER CODE END ADC2_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PER; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_ADC12_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 + */ + GPIO_InitStruct.Pin = GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC2_MspInit 1 */ + /* USER CODE END ADC2_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC2) + { + /* USER CODE BEGIN ADC2_MspDeInit 0 */ + + /* USER CODE END ADC2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC12_CLK_DISABLE(); + + /**ADC2 GPIO Configuration + PF14 ------> ADC2_INP6 + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_14); + + /* USER CODE BEGIN ADC2_MspDeInit 1 */ + + /* USER CODE END ADC2_MspDeInit 1 */ + } + +} + +/** +* @brief DAC MSP Initialization +* This function configures the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hdac->Instance==DAC1) + { + /* USER CODE BEGIN DAC1_MspInit 0 */ + + /* USER CODE END DAC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DAC12_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN DAC1_MspInit 1 */ + + /* USER CODE END DAC1_MspInit 1 */ + } + +} + +/** +* @brief DAC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + if(hdac->Instance==DAC1) + { + /* USER CODE BEGIN DAC1_MspDeInit 0 */ + + /* USER CODE END DAC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DAC12_CLK_DISABLE(); + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); + + /* USER CODE BEGIN DAC1_MspDeInit 1 */ + + /* USER CODE END DAC1_MspDeInit 1 */ + } + +} + +/** +* @brief IPCC MSP Initialization +* This function configures the hardware resources used in this example +* @param hipcc: IPCC handle pointer +* @retval None +*/ +void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc) +{ + if(hipcc->Instance==IPCC) + { + /* USER CODE BEGIN IPCC_MspInit 0 */ + + /* USER CODE END IPCC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_IPCC_CLK_ENABLE(); + /* IPCC interrupt Init */ + HAL_NVIC_SetPriority(IPCC_RX1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(IPCC_RX1_IRQn); + HAL_NVIC_SetPriority(IPCC_TX1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(IPCC_TX1_IRQn); + /* USER CODE BEGIN IPCC_MspInit 1 */ + + /* USER CODE END IPCC_MspInit 1 */ + } + +} + +/** +* @brief IPCC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hipcc: IPCC handle pointer +* @retval None +*/ +void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef* hipcc) +{ + if(hipcc->Instance==IPCC) + { + /* USER CODE BEGIN IPCC_MspDeInit 0 */ + + /* USER CODE END IPCC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_IPCC_CLK_DISABLE(); + + /* IPCC interrupt DeInit */ + HAL_NVIC_DisableIRQ(IPCC_RX1_IRQn); + HAL_NVIC_DisableIRQ(IPCC_TX1_IRQn); + /* USER CODE BEGIN IPCC_MspDeInit 1 */ + + /* USER CODE END IPCC_MspDeInit 1 */ + } + +} + +/** +* @brief LPTIM MSP Initialization +* This function configures the hardware resources used in this example +* @param hlptim: LPTIM handle pointer +* @retval None +*/ +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hlptim->Instance==LPTIM1) + { + /* USER CODE BEGIN LPTIM1_MspInit 0 */ + + /* USER CODE END LPTIM1_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; + PeriphClkInit.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + /* LPTIM1 interrupt Init */ + HAL_NVIC_SetPriority(LPTIM1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPTIM1_IRQn); + /* USER CODE BEGIN LPTIM1_MspInit 1 */ + + /* USER CODE END LPTIM1_MspInit 1 */ + } + else if(hlptim->Instance==LPTIM2) + { + /* USER CODE BEGIN LPTIM2_MspInit 0 */ + + /* USER CODE END LPTIM2_MspInit 0 */ + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; + PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_LPTIM2_CLK_ENABLE(); + /* LPTIM2 interrupt Init */ + HAL_NVIC_SetPriority(LPTIM2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPTIM2_IRQn); + /* USER CODE BEGIN LPTIM2_MspInit 1 */ + + /* USER CODE END LPTIM2_MspInit 1 */ + } + else if(hlptim->Instance==LPTIM3) + { + /* USER CODE BEGIN LPTIM3_MspInit 0 */ + + /* USER CODE END LPTIM3_MspInit 0 */ + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM23; + PeriphClkInit.Lptim23ClockSelection = RCC_LPTIM23CLKSOURCE_PCLK3; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_LPTIM3_CLK_ENABLE(); + /* LPTIM3 interrupt Init */ + HAL_NVIC_SetPriority(LPTIM3_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPTIM3_IRQn); + /* USER CODE BEGIN LPTIM3_MspInit 1 */ + + /* USER CODE END LPTIM3_MspInit 1 */ + } + else if(hlptim->Instance==LPTIM4) + { + /* USER CODE BEGIN LPTIM4_MspInit 0 */ + + /* USER CODE END LPTIM4_MspInit 0 */ + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; + PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_LPTIM4_CLK_ENABLE(); + /* LPTIM4 interrupt Init */ + HAL_NVIC_SetPriority(LPTIM4_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPTIM4_IRQn); + /* USER CODE BEGIN LPTIM4_MspInit 1 */ + + /* USER CODE END LPTIM4_MspInit 1 */ + } + else if(hlptim->Instance==LPTIM5) + { + /* USER CODE BEGIN LPTIM5_MspInit 0 */ + + /* USER CODE END LPTIM5_MspInit 0 */ + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM45; + PeriphClkInit.Lptim45ClockSelection = RCC_LPTIM45CLKSOURCE_PCLK3; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_LPTIM5_CLK_ENABLE(); + /* LPTIM5 interrupt Init */ + HAL_NVIC_SetPriority(LPTIM5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPTIM5_IRQn); + /* USER CODE BEGIN LPTIM5_MspInit 1 */ + + /* USER CODE END LPTIM5_MspInit 1 */ + } + +} + +/** +* @brief LPTIM MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hlptim: LPTIM handle pointer +* @retval None +*/ +void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef* hlptim) +{ + if(hlptim->Instance==LPTIM1) + { + /* USER CODE BEGIN LPTIM1_MspDeInit 0 */ + + /* USER CODE END LPTIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPTIM1_CLK_DISABLE(); + + /* LPTIM1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(LPTIM1_IRQn); + /* USER CODE BEGIN LPTIM1_MspDeInit 1 */ + + /* USER CODE END LPTIM1_MspDeInit 1 */ + } + else if(hlptim->Instance==LPTIM2) + { + /* USER CODE BEGIN LPTIM2_MspDeInit 0 */ + + /* USER CODE END LPTIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPTIM2_CLK_DISABLE(); + + /* LPTIM2 interrupt DeInit */ + HAL_NVIC_DisableIRQ(LPTIM2_IRQn); + /* USER CODE BEGIN LPTIM2_MspDeInit 1 */ + + /* USER CODE END LPTIM2_MspDeInit 1 */ + } + else if(hlptim->Instance==LPTIM3) + { + /* USER CODE BEGIN LPTIM3_MspDeInit 0 */ + + /* USER CODE END LPTIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPTIM3_CLK_DISABLE(); + + /* LPTIM3 interrupt DeInit */ + HAL_NVIC_DisableIRQ(LPTIM3_IRQn); + /* USER CODE BEGIN LPTIM3_MspDeInit 1 */ + + /* USER CODE END LPTIM3_MspDeInit 1 */ + } + else if(hlptim->Instance==LPTIM4) + { + /* USER CODE BEGIN LPTIM4_MspDeInit 0 */ + + /* USER CODE END LPTIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPTIM4_CLK_DISABLE(); + + /* LPTIM4 interrupt DeInit */ + HAL_NVIC_DisableIRQ(LPTIM4_IRQn); + /* USER CODE BEGIN LPTIM4_MspDeInit 1 */ + + /* USER CODE END LPTIM4_MspDeInit 1 */ + } + else if(hlptim->Instance==LPTIM5) + { + /* USER CODE BEGIN LPTIM5_MspDeInit 0 */ + + /* USER CODE END LPTIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPTIM5_CLK_DISABLE(); + + /* LPTIM5 interrupt DeInit */ + HAL_NVIC_DisableIRQ(LPTIM5_IRQn); + /* USER CODE BEGIN LPTIM5_MspDeInit 1 */ + + /* USER CODE END LPTIM5_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hspi->Instance==SPI5) + { + /* USER CODE BEGIN SPI5_MspInit 0 */ + + /* USER CODE END SPI5_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI45; + PeriphClkInit.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_SPI5_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**SPI5 GPIO Configuration + PF9 ------> SPI5_MOSI + PF7 ------> SPI5_SCK + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI5_MspInit 1 */ + + /* USER CODE END SPI5_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI5) + { + /* USER CODE BEGIN SPI5_MspDeInit 0 */ + + /* USER CODE END SPI5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI5_CLK_DISABLE(); + + /**SPI5 GPIO Configuration + PF9 ------> SPI5_MOSI + PF7 ------> SPI5_SCK + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_9|GPIO_PIN_7); + + /* USER CODE BEGIN SPI5_MspDeInit 1 */ + + /* USER CODE END SPI5_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + else if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspInit 0 */ + + /* USER CODE END TIM16_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM16_CLK_ENABLE(); + /* USER CODE BEGIN TIM16_MspInit 1 */ + + /* USER CODE END TIM16_MspInit 1 */ + } + else if(htim_base->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspInit 0 */ + + /* USER CODE END TIM17_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM17_CLK_ENABLE(); + /* USER CODE BEGIN TIM17_MspInit 1 */ + + /* USER CODE END TIM17_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PD13 ------> TIM4_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM16) + { + /* USER CODE BEGIN TIM16_MspDeInit 0 */ + + /* USER CODE END TIM16_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM16_CLK_DISABLE(); + /* USER CODE BEGIN TIM16_MspDeInit 1 */ + + /* USER CODE END TIM16_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM17) + { + /* USER CODE BEGIN TIM17_MspDeInit 0 */ + + /* USER CODE END TIM17_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM17_CLK_DISABLE(); + /* USER CODE BEGIN TIM17_MspDeInit 1 */ + + /* USER CODE END TIM17_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(huart->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspInit 0 */ + + /* USER CODE END UART4_MspInit 0 */ + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART24; + PeriphClkInit.Uart24ClockSelection = RCC_UART24CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_UART4_CLK_ENABLE(); + + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**UART4 GPIO Configuration + PG11 ------> UART4_TX + PB2 ------> UART4_RX + */ + GPIO_InitStruct.Pin = STLINK_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_UART4; + HAL_GPIO_Init(STLINK_RX_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = STLINK_TX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + HAL_GPIO_Init(STLINK_TX_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN UART4_MspInit 1 */ + + /* USER CODE END UART4_MspInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + if(IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART35; + PeriphClkInit.Uart35ClockSelection = RCC_UART35CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB12 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF8_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspDeInit 0 */ + + /* USER CODE END UART4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART4_CLK_DISABLE(); + + /**UART4 GPIO Configuration + PG11 ------> UART4_TX + PB2 ------> UART4_RX + */ + HAL_GPIO_DeInit(STLINK_RX_GPIO_Port, STLINK_RX_Pin); + + HAL_GPIO_DeInit(STLINK_TX_GPIO_Port, STLINK_TX_Pin); + + /* USER CODE BEGIN UART4_MspDeInit 1 */ + + /* USER CODE END UART4_MspDeInit 1 */ + } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB12 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_12); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/** +* @brief WWDG MSP Initialization +* This function configures the hardware resources used in this example +* @param hwwdg: WWDG handle pointer +* @retval None +*/ +void HAL_WWDG_MspInit(WWDG_HandleTypeDef* hwwdg) +{ + if(hwwdg->Instance==WWDG1) + { + /* USER CODE BEGIN WWDG1_MspInit 0 */ + + /* USER CODE END WWDG1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_WWDG1_CLK_ENABLE(); + /* WWDG1 interrupt Init */ + HAL_NVIC_SetPriority(WWDG1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(WWDG1_IRQn); + /* USER CODE BEGIN WWDG1_MspInit 1 */ + + /* USER CODE END WWDG1_MspInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ +/** + * @brief Initializes I2C MSP. + * @param hI2c : I2C handler + * @retval None + */ +void HAL_I2C_MspInit(I2C_HandleTypeDef *hI2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + if(hI2c->Instance == I2C4) + { + if(IS_ENGINEERING_BOOT_MODE()) + { + /*** Configure the I2C peripheral clock ***/ + PeriphClkInit.I2c46ClockSelection = RCC_I2C46CLKSOURCE_HSI; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C46; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + + /* Enable GPIO clock */ + __HAL_RCC_GPIOZ_CLK_ENABLE(); + + /* Configure I2C Tx/RX as alternate function */ + GPIO_InitStruct.Pin = GPIO_PIN_4 | GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF6_I2C4; + HAL_GPIO_Init(GPIOZ, &GPIO_InitStruct); + + /* Enable I2C clock */ + __HAL_RCC_I2C4_CLK_ENABLE(); + /* Force the I2C peripheral clock reset */ + __HAL_RCC_I2C4_FORCE_RESET(); + /* Release the I2C peripheral clock reset */ + __HAL_RCC_I2C4_RELEASE_RESET(); + + HAL_NVIC_SetPriority(I2C4_ER_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(I2C4_ER_IRQn); + HAL_NVIC_SetPriority(I2C4_EV_IRQn, 0, 2); + HAL_NVIC_EnableIRQ(I2C4_EV_IRQn); + } +} + +/** + * @brief DeInitializes I2C MSP. + * @param hI2c : I2C handler + * @retval None + */ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hI2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + if(hI2c->Instance == I2C4) + { + /* Configure I2C Tx, Rx as alternate function */ + GPIO_InitStruct.Pin = GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_DeInit(GPIOZ, GPIO_InitStruct.Pin); + + /* Disable I2C clock */ + __HAL_RCC_I2C4_CLK_DISABLE(); + + /* Disable NVIC for I2C */ + HAL_NVIC_DisableIRQ(I2C4_ER_IRQn); + HAL_NVIC_DisableIRQ(I2C4_EV_IRQn); + } +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_it.c b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_it.c new file mode 100644 index 0000000000000000000000000000000000000000..18c094f48dc181c3f7351e5309a18379cc085bf9 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/CM4/Src/stm32mp1xx_it.c @@ -0,0 +1,321 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32mp1xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32mp1xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern IPCC_HandleTypeDef hipcc; +extern LPTIM_HandleTypeDef hlptim1; +extern LPTIM_HandleTypeDef hlptim2; +extern LPTIM_HandleTypeDef hlptim3; +extern LPTIM_HandleTypeDef hlptim4; +extern LPTIM_HandleTypeDef hlptim5; +extern WWDG_HandleTypeDef hwwdg1; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32MP1xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32mp1xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles Window watchdog interrupt. + */ +void WWDG1_IRQHandler(void) +{ + /* USER CODE BEGIN WWDG1_IRQn 0 */ + + /* USER CODE END WWDG1_IRQn 0 */ + HAL_WWDG_IRQHandler(&hwwdg1); + /* USER CODE BEGIN WWDG1_IRQn 1 */ + + /* USER CODE END WWDG1_IRQn 1 */ +} + +/** + * @brief This function handles LPTIM1 global interrupt. + */ +void LPTIM1_IRQHandler(void) +{ + /* USER CODE BEGIN LPTIM1_IRQn 0 */ + + /* USER CODE END LPTIM1_IRQn 0 */ + HAL_LPTIM_IRQHandler(&hlptim1); + /* USER CODE BEGIN LPTIM1_IRQn 1 */ + + /* USER CODE END LPTIM1_IRQn 1 */ +} + +/** + * @brief This function handles IPCC RX1 occupied interrupt. + */ +void IPCC_RX1_IRQHandler(void) +{ + /* USER CODE BEGIN IPCC_RX1_IRQn 0 */ + + /* USER CODE END IPCC_RX1_IRQn 0 */ + HAL_IPCC_RX_IRQHandler(&hipcc); + /* USER CODE BEGIN IPCC_RX1_IRQn 1 */ + + /* USER CODE END IPCC_RX1_IRQn 1 */ +} + +/** + * @brief This function handles IPCC TX1 free interrupt. + */ +void IPCC_TX1_IRQHandler(void) +{ + /* USER CODE BEGIN IPCC_TX1_IRQn 0 */ + + /* USER CODE END IPCC_TX1_IRQn 0 */ + HAL_IPCC_TX_IRQHandler(&hipcc); + /* USER CODE BEGIN IPCC_TX1_IRQn 1 */ + + /* USER CODE END IPCC_TX1_IRQn 1 */ +} + +/** + * @brief This function handles LPTIM2 global interrupt. + */ +void LPTIM2_IRQHandler(void) +{ + /* USER CODE BEGIN LPTIM2_IRQn 0 */ + + /* USER CODE END LPTIM2_IRQn 0 */ + HAL_LPTIM_IRQHandler(&hlptim2); + /* USER CODE BEGIN LPTIM2_IRQn 1 */ + + /* USER CODE END LPTIM2_IRQn 1 */ +} + +/** + * @brief This function handles LPTIM3 global interrupt. + */ +void LPTIM3_IRQHandler(void) +{ + /* USER CODE BEGIN LPTIM3_IRQn 0 */ + + /* USER CODE END LPTIM3_IRQn 0 */ + HAL_LPTIM_IRQHandler(&hlptim3); + /* USER CODE BEGIN LPTIM3_IRQn 1 */ + + /* USER CODE END LPTIM3_IRQn 1 */ +} + +/** + * @brief This function handles LPTIM4 global interrupt. + */ +void LPTIM4_IRQHandler(void) +{ + /* USER CODE BEGIN LPTIM4_IRQn 0 */ + + /* USER CODE END LPTIM4_IRQn 0 */ + HAL_LPTIM_IRQHandler(&hlptim4); + /* USER CODE BEGIN LPTIM4_IRQn 1 */ + + /* USER CODE END LPTIM4_IRQn 1 */ +} + +/** + * @brief This function handles LPTIM5 global interrupt. + */ +void LPTIM5_IRQHandler(void) +{ + /* USER CODE BEGIN LPTIM5_IRQn 0 */ + + /* USER CODE END LPTIM5_IRQn 0 */ + HAL_LPTIM_IRQHandler(&hlptim5); + /* USER CODE BEGIN LPTIM5_IRQn 1 */ + + /* USER CODE END LPTIM5_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/Common/System/system_stm32mp1xx.c b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/Common/System/system_stm32mp1xx.c new file mode 100644 index 0000000000000000000000000000000000000000..6e606791bf5087ab6b0f41dce0f59be2ae03819b --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/Common/System/system_stm32mp1xx.c @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file system_stm32mp1xx.c + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32mp1xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock frequency, it can + * be used by the user application to setup + * the SysTick timer or configure other + * parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32mp1xx_system + * @{ + */ + +/** @addtogroup STM32MP1xx_System_Private_Includes + * @{ + */ + +#include "stm32mp1xx_hal.h" + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Private_Defines + * @{ + */ + + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM mounted + on EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) each time HAL_RCC_ClockConfig() is called to configure the system clock + frequency + Note: If you use this function to configure the system clock; + then there is no need to call the first functions listed above, + since SystemCoreClock variable is updated automatically. + */ + uint32_t SystemCoreClock = HSI_VALUE; +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Private_Functions + * @{ + */ + + /** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if defined (CORE_CM4) + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Configure the Vector Table location add offset address ------------------*/ +#if defined (VECT_TAB_SRAM) + SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif + /* Disable all interrupts and events */ + CLEAR_REG(EXTI_C2->IMR1); + CLEAR_REG(EXTI_C2->IMR2); + CLEAR_REG(EXTI_C2->IMR3); + CLEAR_REG(EXTI_C2->EMR1); + CLEAR_REG(EXTI_C2->EMR2); + CLEAR_REG(EXTI_C2->EMR3); +#else +#error Please #define CORE_CM4 +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock frequency (Hz), + * it can be used by the user application to setup the SysTick timer or + * configure other parameters. + * + * @note Each time the core clock changes, this function must be called to + * update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the + * HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the + * HSE_VALUE(**) + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the + * CSI_VALUE(***) + * + * - If SYSCLK source is PLL3_P, SystemCoreClock will contain the + * HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***) + * multiplied/divided by the PLL3 factors. + * + * (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file + * (default value 64 MHz) but the real value may vary depending + * on the variations in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file + * (default value 24 MHz), user has to ensure that HSE_VALUE is + * same as the real frequency of the crystal used. Otherwise, this + * function may have wrong result. + * + * (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file + * (default value 4 MHz)but the real value may vary depending + * on the variations in voltage and temperature. + * + * - The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllsource, pll3m, pll3fracen; + float fracn1, pll3vco; + + switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)); + break; + + case 0x01: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x02: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case 0x03: /* PLL3_P used as system clock source */ + pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC); + pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U; + pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U; + fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U)); + pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF)); + + if (pll3m != 0U) + { + switch (pllsource) + { + case 0x00: /* HSI used as PLL clock source */ + pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m); + break; + + case 0x01: /* HSE used as PLL clock source */ + pll3vco *= (float)(HSE_VALUE / pll3m); + break; + + case 0x02: /* CSI used as PLL clock source */ + pll3vco *= (float)(CSI_VALUE / pll3m); + break; + + case 0x03: /* No clock source for PLL */ + pll3vco = 0; + break; + } + SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U))); + } + else + { + SystemCoreClock = 0U; + } + break; + } + + /* Compute mcu_ck */ + SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV); +} + + +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32mp15xx.s before jump to main. + * This function configures the external SRAM mounted on Eval boards + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + +} +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/STM32MP157-DK1.ioc b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/STM32MP157-DK1.ioc new file mode 100644 index 0000000000000000000000000000000000000000..2a094a9c12ff1a1ae9ac0f94adfe709064c275c6 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/CubeMX_Config/STM32MP157-DK1.ioc @@ -0,0 +1,857 @@ +#MicroXplorer Configuration settings - do not modify +ADC2.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_6 +ADC2.ClockPrescaler=ADC_CLOCK_ASYNC_DIV2 +ADC2.IPParameters=Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,NbrOfConversionFlag,Resolution,ClockPrescaler +ADC2.NbrOfConversionFlag=1 +ADC2.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC2.Rank-2\#ChannelRegularConversion=1 +ADC2.Resolution=ADC_RESOLUTION_16B +ADC2.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +BootLoader.IPs=RCC,DDR +BootROM.IPs=RCC +CortexA7NS.IPs=DDR\:I,RCC\:I,RTC\:I,BSEC,ETZPC,GIC,TAMP\:I,DMA\:I,PWR,SPI2\:I,I2S2\:I,IPCC\:I,TIM3\:I,VREFBUF\:I,SAI4\:I,HSEM\:I,RNG1,DMA1\:I,MDMA_A7NS\:I +CortexA7S.IPs=BSEC\:I,ETZPC\:I,GIC\:I,RCC,PWR\:I,RNG1\:I,RTC,DDR,HSEM,TAMP,MDMA_A7S\:I +CortexM4.IPs=IPCC,HSEM,RCC,NVIC\:I,ETZPC,FREERTOS\:I,DMA,PWR,SYS\:I,TIM4\:I,TIM14\:I,TIM16\:I,TIM17\:I,SPI5\:I,UART4\:I,UART5\:I,USART2\:I,ADC1\:I,ADC2\:I,USART3\:I,DAC1\:I,WWDG1\:I,LPTIM1\:I,LPTIM2\:I,LPTIM3\:I,LPTIM4\:I,LPTIM5\:I,DMA2\:I +DDR.ADDRMAP1=0x00070707 +DDR.ADDRMAP3=0x1F000000 +DDR.ADDRMAP5=0x06060606 +DDR.ADDRMAP6=0x0F060606 +DDR.DDR_Frequency=533.0 +DDR.DFITMG0=0x02060105 +DDR.IPParameters=DDR_Frequency,RL,addrmap_col_b9,addrmap_col_b10,addrmap_col_b11,addrmap_bank_b0,addrmap_bank_b1,addrmap_bank_b2,addrmap_row_b0,addrmap_row_b1,addrmap_row_b2_10,addrmap_row_b11,addrmap_row_b12,addrmap_row_b13,addrmap_row_b14,addrmap_row_b15,MSTR,DFITMG0,SCHED,ADDRMAP1,ADDRMAP3,ADDRMAP5,ADDRMAP6 +DDR.MSTR=0x00041401 +DDR.RL=8 +DDR.SCHED=0x00000C01 +DDR.addrmap_bank_b0=7 +DDR.addrmap_bank_b1=7 +DDR.addrmap_bank_b2=7 +DDR.addrmap_col_b10=31 +DDR.addrmap_col_b11=31 +DDR.addrmap_col_b9=31 +DDR.addrmap_row_b0=6 +DDR.addrmap_row_b1=6 +DDR.addrmap_row_b11=6 +DDR.addrmap_row_b12=6 +DDR.addrmap_row_b13=6 +DDR.addrmap_row_b14=6 +DDR.addrmap_row_b15=15 +DDR.addrmap_row_b2_10=6 +DDR_A0.GPIOParameters=GPIO_Label +DDR_A0.GPIO_Label=DDR_A0 [MT41K256M16TW_A0] +DDR_A0.Locked=true +DDR_A0.Mode=DDR3 +DDR_A0.Signal=DDR_A0 +DDR_A1.GPIOParameters=GPIO_Label +DDR_A1.GPIO_Label=DDR_A1 [MT41K256M16TW_A1] +DDR_A1.Locked=true +DDR_A1.Mode=DDR3 +DDR_A1.Signal=DDR_A1 +DDR_A10.GPIOParameters=GPIO_Label +DDR_A10.GPIO_Label=DDR_A10 [MT41K256M16TW_A10] +DDR_A10.Locked=true +DDR_A10.Mode=DDR3 +DDR_A10.Signal=DDR_A10 +DDR_A11.GPIOParameters=GPIO_Label +DDR_A11.GPIO_Label=DDR_A11 [MT41K256M16TW_A11] +DDR_A11.Locked=true +DDR_A11.Mode=DDR3 +DDR_A11.Signal=DDR_A11 +DDR_A12.GPIOParameters=GPIO_Label +DDR_A12.GPIO_Label=DDR_A12 [MT41K256M16TW_A12] +DDR_A12.Locked=true +DDR_A12.Mode=4Gb_16bits +DDR_A12.Signal=DDR_A12 +DDR_A13.GPIOParameters=GPIO_Label +DDR_A13.GPIO_Label=DDR_A13 [MT41K256M16TW_A13] +DDR_A13.Locked=true +DDR_A13.Mode=4Gb_16bits +DDR_A13.Signal=DDR_A13 +DDR_A14.GPIOParameters=GPIO_Label +DDR_A14.GPIO_Label=DDR_A14 [MT41K256M16TW_A14] +DDR_A14.Locked=true +DDR_A14.Mode=4Gb_16bits +DDR_A14.Signal=DDR_A14 +DDR_A2.GPIOParameters=GPIO_Label +DDR_A2.GPIO_Label=DDR_A2 [MT41K256M16TW_A2] +DDR_A2.Locked=true +DDR_A2.Mode=DDR3 +DDR_A2.Signal=DDR_A2 +DDR_A3.GPIOParameters=GPIO_Label +DDR_A3.GPIO_Label=DDR_A3 [MT41K256M16TW_A3] +DDR_A3.Locked=true +DDR_A3.Mode=DDR3 +DDR_A3.Signal=DDR_A3 +DDR_A4.GPIOParameters=GPIO_Label +DDR_A4.GPIO_Label=DDR_A4 [MT41K256M16TW_A4] +DDR_A4.Locked=true +DDR_A4.Mode=DDR3 +DDR_A4.Signal=DDR_A4 +DDR_A5.GPIOParameters=GPIO_Label +DDR_A5.GPIO_Label=DDR_A5 [MT41K256M16TW_A5] +DDR_A5.Locked=true +DDR_A5.Mode=DDR3 +DDR_A5.Signal=DDR_A5 +DDR_A6.GPIOParameters=GPIO_Label +DDR_A6.GPIO_Label=DDR_A6 [MT41K256M16TW_A6] +DDR_A6.Locked=true +DDR_A6.Mode=DDR3 +DDR_A6.Signal=DDR_A6 +DDR_A7.GPIOParameters=GPIO_Label +DDR_A7.GPIO_Label=DDR_A7 [MT41K256M16TW_A7] +DDR_A7.Locked=true +DDR_A7.Mode=DDR3 +DDR_A7.Signal=DDR_A7 +DDR_A8.GPIOParameters=GPIO_Label +DDR_A8.GPIO_Label=DDR_A8 [MT41K256M16TW_A8] +DDR_A8.Locked=true +DDR_A8.Mode=DDR3 +DDR_A8.Signal=DDR_A8 +DDR_A9.GPIOParameters=GPIO_Label +DDR_A9.GPIO_Label=DDR_A9 [MT41K256M16TW_A9] +DDR_A9.Locked=true +DDR_A9.Mode=DDR3 +DDR_A9.Signal=DDR_A9 +DDR_ATO.GPIOParameters=GPIO_Label +DDR_ATO.GPIO_Label=DDR_ATO +DDR_ATO.Locked=true +DDR_ATO.Mode=DDR3 +DDR_ATO.Signal=DDR_ATO +DDR_BA0.GPIOParameters=GPIO_Label +DDR_BA0.GPIO_Label=DDR_BA0 [MT41K256M16TW_BA0] +DDR_BA0.Locked=true +DDR_BA0.Mode=DDR3 +DDR_BA0.Signal=DDR_BA0 +DDR_BA1.GPIOParameters=GPIO_Label +DDR_BA1.GPIO_Label=DDR_BA1 [MT41K256M16TW_BA1] +DDR_BA1.Locked=true +DDR_BA1.Mode=DDR3 +DDR_BA1.Signal=DDR_BA1 +DDR_BA2.GPIOParameters=GPIO_Label +DDR_BA2.GPIO_Label=DDR_BA2 [MT41K256M16TW_BA2] +DDR_BA2.Locked=true +DDR_BA2.Mode=DDR3 +DDR_BA2.Signal=DDR_BA2 +DDR_CASN.GPIOParameters=GPIO_Label +DDR_CASN.GPIO_Label=DDR_CASN [MT41K256M16TW_CAS\#] +DDR_CASN.Locked=true +DDR_CASN.Mode=DDR3 +DDR_CASN.Signal=DDR_CASN +DDR_CKE.GPIOParameters=GPIO_Label +DDR_CKE.GPIO_Label=DDR_CKE [MT41K256M16TW_CKE] +DDR_CKE.Locked=true +DDR_CKE.Mode=DDR3 +DDR_CKE.Signal=DDR_CKE +DDR_CLKN.GPIOParameters=GPIO_Label +DDR_CLKN.GPIO_Label=DDR_CLK_N [MT41K256M16TW_CK\#] +DDR_CLKN.Locked=true +DDR_CLKN.Mode=DDR3 +DDR_CLKN.Signal=DDR_CLKN +DDR_CLKP.GPIOParameters=GPIO_Label +DDR_CLKP.GPIO_Label=DDR_CLK_P [MT41K256M16TW_CK] +DDR_CLKP.Locked=true +DDR_CLKP.Mode=DDR3 +DDR_CLKP.Signal=DDR_CLKP +DDR_CSN.GPIOParameters=GPIO_Label +DDR_CSN.GPIO_Label=DDR_CSN [MT41K256M16TW_CS\#] +DDR_CSN.Locked=true +DDR_CSN.Mode=DDR3 +DDR_CSN.Signal=DDR_CSN +DDR_DQ0.GPIOParameters=GPIO_Label +DDR_DQ0.GPIO_Label=DDR_DQ0 [MT41K256M16TW_DQU5] +DDR_DQ0.Locked=true +DDR_DQ0.Mode=DDR3 +DDR_DQ0.Signal=DDR_DQ0 +DDR_DQ1.GPIOParameters=GPIO_Label +DDR_DQ1.GPIO_Label=DDR_DQ1 [MT41K256M16TW_DQU1] +DDR_DQ1.Locked=true +DDR_DQ1.Mode=DDR3 +DDR_DQ1.Signal=DDR_DQ1 +DDR_DQ10.GPIOParameters=GPIO_Label +DDR_DQ10.GPIO_Label=DDR_DQ10 [MT41K256M16TW_DQL6] +DDR_DQ10.Locked=true +DDR_DQ10.Mode=DDR3 +DDR_DQ10.Signal=DDR_DQ10 +DDR_DQ11.GPIOParameters=GPIO_Label +DDR_DQ11.GPIO_Label=DDR_DQ11 [MT41K256M16TW_DQL1] +DDR_DQ11.Locked=true +DDR_DQ11.Mode=DDR3 +DDR_DQ11.Signal=DDR_DQ11 +DDR_DQ12.GPIOParameters=GPIO_Label +DDR_DQ12.GPIO_Label=DDR_DQ12 [MT41K256M16TW_DQL5] +DDR_DQ12.Locked=true +DDR_DQ12.Mode=DDR3 +DDR_DQ12.Signal=DDR_DQ12 +DDR_DQ13.GPIOParameters=GPIO_Label +DDR_DQ13.GPIO_Label=DDR_DQ13 [MT41K256M16TW_DQL4] +DDR_DQ13.Locked=true +DDR_DQ13.Mode=DDR3 +DDR_DQ13.Signal=DDR_DQ13 +DDR_DQ14.GPIOParameters=GPIO_Label +DDR_DQ14.GPIO_Label=DDR_DQ14 [MT41K256M16TW_DQL7] +DDR_DQ14.Locked=true +DDR_DQ14.Mode=DDR3 +DDR_DQ14.Signal=DDR_DQ14 +DDR_DQ15.GPIOParameters=GPIO_Label +DDR_DQ15.GPIO_Label=DDR_DQ15 [MT41K256M16TW_DQL3] +DDR_DQ15.Locked=true +DDR_DQ15.Mode=DDR3 +DDR_DQ15.Signal=DDR_DQ15 +DDR_DQ2.GPIOParameters=GPIO_Label +DDR_DQ2.GPIO_Label=DDR_DQ2 [MT41K256M16TW_DQU4] +DDR_DQ2.Locked=true +DDR_DQ2.Mode=DDR3 +DDR_DQ2.Signal=DDR_DQ2 +DDR_DQ3.GPIOParameters=GPIO_Label +DDR_DQ3.GPIO_Label=DDR_DQ3 [MT41K256M16TW_DQU3] +DDR_DQ3.Locked=true +DDR_DQ3.Mode=DDR3 +DDR_DQ3.Signal=DDR_DQ3 +DDR_DQ4.GPIOParameters=GPIO_Label +DDR_DQ4.GPIO_Label=DDR_DQ4 [MT41K256M16TW_DQU6] +DDR_DQ4.Locked=true +DDR_DQ4.Mode=DDR3 +DDR_DQ4.Signal=DDR_DQ4 +DDR_DQ5.GPIOParameters=GPIO_Label +DDR_DQ5.GPIO_Label=DDR_DQ5 [MT41K256M16TW_DQU2] +DDR_DQ5.Locked=true +DDR_DQ5.Mode=DDR3 +DDR_DQ5.Signal=DDR_DQ5 +DDR_DQ6.GPIOParameters=GPIO_Label +DDR_DQ6.GPIO_Label=DDR_DQ6 [MT41K256M16TW_DQU0] +DDR_DQ6.Locked=true +DDR_DQ6.Mode=DDR3 +DDR_DQ6.Signal=DDR_DQ6 +DDR_DQ7.GPIOParameters=GPIO_Label +DDR_DQ7.GPIO_Label=DDR_DQ7 [MT41K256M16TW_DQU7] +DDR_DQ7.Locked=true +DDR_DQ7.Mode=DDR3 +DDR_DQ7.Signal=DDR_DQ7 +DDR_DQ8.GPIOParameters=GPIO_Label +DDR_DQ8.GPIO_Label=DDR_DQ8 [MT41K256M16TW_DQL2] +DDR_DQ8.Locked=true +DDR_DQ8.Mode=DDR3 +DDR_DQ8.Signal=DDR_DQ8 +DDR_DQ9.GPIOParameters=GPIO_Label +DDR_DQ9.GPIO_Label=DDR_DQ9 [MT41K256M16TW_DQL0] +DDR_DQ9.Locked=true +DDR_DQ9.Mode=DDR3 +DDR_DQ9.Signal=DDR_DQ9 +DDR_DQM0.GPIOParameters=GPIO_Label +DDR_DQM0.GPIO_Label=DDR_DQM0 [MT41K256M16TW_DMU] +DDR_DQM0.Locked=true +DDR_DQM0.Mode=DDR3 +DDR_DQM0.Signal=DDR_DQM0 +DDR_DQM1.GPIOParameters=GPIO_Label +DDR_DQM1.GPIO_Label=DDR_DQM1 [MT41K256M16TW_DML] +DDR_DQM1.Locked=true +DDR_DQM1.Mode=DDR3 +DDR_DQM1.Signal=DDR_DQM1 +DDR_DQS0N.GPIOParameters=GPIO_Label +DDR_DQS0N.GPIO_Label=DDR_DQS0_N [MT41K256M16TW_DQSU\#] +DDR_DQS0N.Locked=true +DDR_DQS0N.Mode=DDR3 +DDR_DQS0N.Signal=DDR_DQS0N +DDR_DQS0P.GPIOParameters=GPIO_Label +DDR_DQS0P.GPIO_Label=DDR_DQS0_P [MT41K256M16TW_DQSU] +DDR_DQS0P.Locked=true +DDR_DQS0P.Mode=DDR3 +DDR_DQS0P.Signal=DDR_DQS0P +DDR_DQS1N.GPIOParameters=GPIO_Label +DDR_DQS1N.GPIO_Label=DDR_DQS1_N [MT41K256M16TW_DQSL\#] +DDR_DQS1N.Locked=true +DDR_DQS1N.Mode=DDR3 +DDR_DQS1N.Signal=DDR_DQS1N +DDR_DQS1P.GPIOParameters=GPIO_Label +DDR_DQS1P.GPIO_Label=DDR_DQS1_P [MT41K256M16TW_DQSL] +DDR_DQS1P.Locked=true +DDR_DQS1P.Mode=DDR3 +DDR_DQS1P.Signal=DDR_DQS1P +DDR_DTO0.GPIOParameters=GPIO_Label +DDR_DTO0.GPIO_Label=DDR_DTO0 +DDR_DTO0.Locked=true +DDR_DTO0.Mode=DDR3 +DDR_DTO0.Signal=DDR_DTO0 +DDR_DTO1.GPIOParameters=GPIO_Label +DDR_DTO1.GPIO_Label=DDR_DTO1 +DDR_DTO1.Locked=true +DDR_DTO1.Mode=DDR3 +DDR_DTO1.Signal=DDR_DTO1 +DDR_ODT.GPIOParameters=GPIO_Label +DDR_ODT.GPIO_Label=DDR_ODT [MT41K256M16TW_ODT] +DDR_ODT.Locked=true +DDR_ODT.Mode=DDR3 +DDR_ODT.Signal=DDR_ODT +DDR_RASN.GPIOParameters=GPIO_Label +DDR_RASN.GPIO_Label=DDR_RASN [MT41K256M16TW_RAS\#] +DDR_RASN.Locked=true +DDR_RASN.Mode=DDR3 +DDR_RASN.Signal=DDR_RASN +DDR_RESETN.GPIOParameters=GPIO_Label +DDR_RESETN.GPIO_Label=DDR_RESETN [MT41K256M16TW_RESET\#] +DDR_RESETN.Locked=true +DDR_RESETN.Mode=DDR3 +DDR_RESETN.Signal=DDR_RESETN +DDR_VREF.GPIOParameters=GPIO_Label +DDR_VREF.GPIO_Label=VREF_DDR +DDR_VREF.Locked=true +DDR_VREF.Mode=DDR3 +DDR_VREF.Signal=DDR_VREF +DDR_WEN.GPIOParameters=GPIO_Label +DDR_WEN.GPIO_Label=DDR_WEN_P [MT41K256M16TW_WE\#] +DDR_WEN.Locked=true +DDR_WEN.Mode=DDR3 +DDR_WEN.Signal=DDR_WEN +DDR_ZQ.GPIOParameters=GPIO_Label +DDR_ZQ.GPIO_Label=DDR_ZQ +DDR_ZQ.Locked=true +DDR_ZQ.Mode=DDR3 +DDR_ZQ.Signal=DDR_ZQ +File.Version=6 +GIC.IPCC_RX0_IRQn=true\:false\:High level +GIC.IPCC_TX0_IRQn=true\:false\:High level +GIC.PMUIRQ0_IRQn=true\:false\:High level +GIC.PMUIRQ1_IRQn=true\:false\:High level +GIC.RCC_IRQn=true\:false\:High level +GIC.RTC_WKUP_ALARM_IRQn=true\:false\:High level +GIC.WAKEUP_PIN_IRQn=true\:false\:High level +GPIO.groupedBy=Expand Peripherals +KeepUserPlacement=false +Mcu.Context0=BootROM +Mcu.Context1=BootLoader +Mcu.Context2=CortexA7S +Mcu.Context3=CortexA7NS +Mcu.Context4=CortexM4 +Mcu.ContextNb=5 +Mcu.Family=STM32MP1 +Mcu.IP0=ADC2 +Mcu.IP1=BSEC +Mcu.IP10=LPTIM4 +Mcu.IP11=LPTIM5 +Mcu.IP12=NVIC +Mcu.IP13=PWR +Mcu.IP14=RCC +Mcu.IP15=RTC +Mcu.IP16=SPI5 +Mcu.IP17=SYS +Mcu.IP18=TAMP +Mcu.IP19=TIM4 +Mcu.IP2=DAC1 +Mcu.IP20=TIM14 +Mcu.IP21=TIM16 +Mcu.IP22=TIM17 +Mcu.IP23=UART4 +Mcu.IP24=USART3 +Mcu.IP25=VREFBUF +Mcu.IP26=WWDG1 +Mcu.IP3=DDR +Mcu.IP4=GIC +Mcu.IP5=HSEM +Mcu.IP6=IPCC +Mcu.IP7=LPTIM1 +Mcu.IP8=LPTIM2 +Mcu.IP9=LPTIM3 +Mcu.IPNb=27 +Mcu.Name=STM32MP157AACx +Mcu.Package=TFBGA361 +Mcu.Pin0=PH5 +Mcu.Pin1=PF2 +Mcu.Pin10=DDR_DQ3 +Mcu.Pin100=VP_TAMP_VS_TAMP_Activate +Mcu.Pin101=VP_TIM4_VS_ClockSourceINT +Mcu.Pin102=VP_TIM14_VS_ClockSourceINT +Mcu.Pin103=VP_TIM16_VS_ClockSourceINT +Mcu.Pin104=VP_TIM17_VS_ClockSourceINT +Mcu.Pin105=VP_VREFBUF_VS_VREFBUF +Mcu.Pin106=VP_WWDG1_VS_WWDG +Mcu.Pin107=VP_DMA_VS_DMA1_A7NS +Mcu.Pin108=VP_DMA_VS_DMA2_M4 +Mcu.Pin109=VP_MDMA_VS_MDMA_A7NS_8 +Mcu.Pin11=DDR_DQ0 +Mcu.Pin12=DDR_A13 +Mcu.Pin13=DDR_DQ1 +Mcu.Pin14=DDR_A9 +Mcu.Pin15=DDR_DQ7 +Mcu.Pin16=DDR_DQS0P +Mcu.Pin17=DDR_DQS0N +Mcu.Pin18=PZ6 +Mcu.Pin19=DDR_A5 +Mcu.Pin2=PH4 +Mcu.Pin20=DDR_DQ2 +Mcu.Pin21=DDR_DQ6 +Mcu.Pin22=DDR_DQM0 +Mcu.Pin23=PZ7 +Mcu.Pin24=DDR_A2 +Mcu.Pin25=DDR_DQ4 +Mcu.Pin26=DDR_DQ5 +Mcu.Pin27=PC13 +Mcu.Pin28=DDR_DTO0 +Mcu.Pin29=DDR_A3 +Mcu.Pin3=PD0 +Mcu.Pin30=DDR_ZQ +Mcu.Pin31=PC15-OSC32_OUT +Mcu.Pin32=PC14-OSC32_IN +Mcu.Pin33=DDR_A0 +Mcu.Pin34=DDR_DTO1 +Mcu.Pin35=DDR_ODT +Mcu.Pin36=DDR_BA0 +Mcu.Pin37=DDR_WEN +Mcu.Pin38=DDR_BA2 +Mcu.Pin39=DDR_CSN +Mcu.Pin4=PC6 +Mcu.Pin40=PA13 +Mcu.Pin41=DDR_CASN +Mcu.Pin42=DDR_RASN +Mcu.Pin43=DDR_CLKP +Mcu.Pin44=DDR_CLKN +Mcu.Pin45=PH0-OSC_IN +Mcu.Pin46=PI11 +Mcu.Pin47=DDR_A1 +Mcu.Pin48=DDR_A12 +Mcu.Pin49=DDR_A11 +Mcu.Pin5=PA15 +Mcu.Pin50=DDR_A14 +Mcu.Pin51=DDR_A10 +Mcu.Pin52=PA14 +Mcu.Pin53=DDR_CKE +Mcu.Pin54=DDR_DQ8 +Mcu.Pin55=DDR_DQ10 +Mcu.Pin56=DDR_DQ13 +Mcu.Pin57=DDR_BA1 +Mcu.Pin58=DDR_DQ9 +Mcu.Pin59=DDR_DQS1P +Mcu.Pin6=PB7 +Mcu.Pin60=DDR_DQS1N +Mcu.Pin61=PA4 +Mcu.Pin62=DDR_A4 +Mcu.Pin63=DDR_DQM1 +Mcu.Pin64=PG1 +Mcu.Pin65=PH7 +Mcu.Pin66=DDR_A6 +Mcu.Pin67=DDR_DQ11 +Mcu.Pin68=DDR_DQ14 +Mcu.Pin69=DDR_DQ12 +Mcu.Pin7=PE4 +Mcu.Pin70=PB10 +Mcu.Pin71=PG11 +Mcu.Pin72=PG9 +Mcu.Pin73=PB2 +Mcu.Pin74=PA10 +Mcu.Pin75=DDR_ATO +Mcu.Pin76=DDR_A8 +Mcu.Pin77=DDR_DQ15 +Mcu.Pin78=PF9 +Mcu.Pin79=PD13 +Mcu.Pin8=DDR_RESETN +Mcu.Pin80=PA0 +Mcu.Pin81=PF7 +Mcu.Pin82=PF14 +Mcu.Pin83=PB12 +Mcu.Pin84=PA6 +Mcu.Pin85=PD11 +Mcu.Pin86=DDR_VREF +Mcu.Pin87=VP_BSEC_VS_BSEC +Mcu.Pin88=VP_DDR_DDR3 +Mcu.Pin89=VP_DDR_DDR_16_bits +Mcu.Pin9=DDR_A7 +Mcu.Pin90=VP_DDR_DDR3_16_4Gb +Mcu.Pin91=VP_HSEM_VS_HSEM +Mcu.Pin92=VP_IPCC_VS_IPCC +Mcu.Pin93=VP_LPTIM1_VS_LPTIM_counterModeInternalClock +Mcu.Pin94=VP_LPTIM2_VS_LPTIM_counterModeInternalClock +Mcu.Pin95=VP_LPTIM3_VS_LPTIM_counterModeInternalClock +Mcu.Pin96=VP_LPTIM4_VS_LPTIM_counterModeInternalClock +Mcu.Pin97=VP_LPTIM5_VS_LPTIM_counterModeInternalClock +Mcu.Pin98=VP_RTC_VS_RTC_Activate +Mcu.Pin99=VP_SYS_VS_Systick +Mcu.PinsNb=110 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32MP157AACx +MxCube.Version=5.6.1 +MxDb.Version=DB.5.0.60 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.IPCC_RX1_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.IPCC_TX1_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.LPTIM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.LPTIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.LPTIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.LPTIM4_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.LPTIM5_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.WWDG1_IRQn=true\:0\:0\:false\:false\:true\:true\:true +PA0.Locked=true +PA0.Mode=WakeUp1 +PA0.Signal=PWR_WKUP1 +PA10.GPIOParameters=GPIO_Label +PA10.GPIO_Label=HDMI_NRST [SiI9022ACNU_RESET\#] +PA10.Locked=true +PA10.Signal=GPIO_Output +PA13.GPIOParameters=GPIO_Label +PA13.GPIO_Label=PA13 [LD6_RED] +PA13.Locked=true +PA13.Signal=GPIO_Output +PA14.GPIOParameters=GPIO_Label +PA14.GPIO_Label=PA14 [SW-PUSH-TS-02H-Blue] +PA14.Locked=true +PA14.Signal=GPIO_Input +PA15.GPIOParameters=GPIO_Label +PA15.GPIO_Label=BL_CTRL [STLD40DPUR_EN] +PA15.Locked=true +PA15.Signal=GPIO_Output +PA4.Signal=COMP_DAC11_group +PA6.GPIOParameters=GPIO_Label +PA6.GPIO_Label=ETH_MDINT [RTL8211F_INT] +PA6.Locked=true +PA6.Signal=GPIO_Input +PB10.Locked=true +PB10.Mode=Asynchronous +PB10.Signal=USART3_TX +PB12.Locked=true +PB12.Mode=Asynchronous +PB12.Signal=USART3_RX +PB2.GPIOParameters=GPIO_Label +PB2.GPIO_Label=STLINK_TX [STM32F103CBT6_PA2] +PB2.Locked=true +PB2.Mode=Asynchronous +PB2.Signal=UART4_RX +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=uSD_DETECT [PJS008-2003-1] +PB7.Locked=true +PB7.Signal=GPIO_Input +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=PMIC_WAKEUP [STPMU1A_WAKEUP] +PC13.Locked=true +PC13.Signal=GPIO_Output +PC14-OSC32_IN.Locked=true +PC14-OSC32_IN.Mode=LSE-External-Oscillator +PC14-OSC32_IN.Signal=RCC_OSC32_IN +PC15-OSC32_OUT.Locked=true +PC15-OSC32_OUT.Mode=LSE-External-Oscillator +PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PC6.GPIOParameters=GPIO_Label +PC6.GPIO_Label=TE [FH26W-25S_TE] +PC6.Locked=true +PC6.Signal=GPIO_Output +PD0.GPIOParameters=GPIO_Label +PD0.GPIO_Label=WL_HOST_WAKE [LBEE5KL1DX_WL_HOST_WAKE] +PD0.Locked=true +PD0.Signal=GPIO_Input +PD11.GPIOParameters=GPIO_Label +PD11.GPIO_Label=LED_B [LD8_BLUE] +PD11.Locked=true +PD11.Signal=GPIO_Output +PD13.Signal=S_TIM4_CH2 +PE4.GPIOParameters=GPIO_Label +PE4.GPIO_Label=RSTN [FH26W-25S_RSTN] +PE4.Locked=true +PE4.Signal=GPIO_Output +PF14.Locked=true +PF14.Mode=IN6-Single-Ended +PF14.Signal=ADC2_INP6 +PF2.GPIOParameters=GPIO_Label +PF2.GPIO_Label=INT [FH26W-25S_INT] +PF2.Locked=true +PF2.Signal=GPIO_Input +PF7.Locked=true +PF7.Mode=TX_Only_Simplex_Unidirect_Master +PF7.Signal=SPI5_SCK +PF9.Mode=TX_Only_Simplex_Unidirect_Master +PF9.Signal=SPI5_MOSI +PG1.GPIOParameters=GPIO_Label +PG1.GPIO_Label=HDMI_INT [SiI9022ACNU_INT] +PG1.Locked=true +PG1.Signal=GPIO_Input +PG11.GPIOParameters=GPIO_Label +PG11.GPIO_Label=STLINK_RX [STM32F103CBT6_PA3] +PG11.Locked=true +PG11.Mode=Asynchronous +PG11.Signal=UART4_TX +PG9.GPIOParameters=GPIO_Label +PG9.GPIO_Label=AUDIO_RST [CS42L51-CNZ_RESET] +PG9.Locked=true +PG9.Signal=GPIO_Output +PH0-OSC_IN.Locked=true +PH0-OSC_IN.Mode=HSE-DIG-External-Clock-Source +PH0-OSC_IN.Signal=RCC_OSC_IN +PH4.GPIOParameters=GPIO_Label +PH4.GPIO_Label=WL_REG_ON [LBEE5KL1DX_WL_REG_ON] +PH4.Locked=true +PH4.Signal=GPIO_Output +PH5.GPIOParameters=GPIO_Label +PH5.GPIO_Label=BT_HOST_WAKE [LBEE5KL1DX_BT_HOST_WAKE] +PH5.Locked=true +PH5.Signal=GPIO_Input +PH7.GPIOParameters=GPIO_Label +PH7.GPIO_Label=LED_Y [LD7_ORANGE] +PH7.Locked=true +PH7.Signal=GPIO_Output +PI11.GPIOParameters=GPIO_Label +PI11.GPIO_Label=STUSB1600_IRQOUTn [STUSB1600_ALERT\#] +PI11.Locked=true +PI11.Signal=GPIO_Input +PZ6.GPIOParameters=GPIO_Label +PZ6.GPIO_Label=BT_REG_ON [LBEE5KL1DX_BT_REG_ON] +PZ6.Locked=true +PZ6.Signal=GPIO_Output +PZ7.GPIOParameters=GPIO_Label +PZ7.GPIO_Label=BT_DEV_WAKE [LBEE5KL1DX_BT_DEV_WAKE] +PZ7.Locked=true +PZ7.Signal=GPIO_Output +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32MP157AACx +ProjectManager.DeviceTreeLocation=D\:\\3_work\\GitRepositories\\rt-thread\\bsp\\stm32\\stm32mp157a-st-discovery\\board\\CubeMX_Config\\STM32MP157-DK1\\CA7\\DeviceTree\\ +ProjectManager.FirmwarePackage=STM32Cube FW_MP1 V1.2.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STM32MP157-DK1.ioc +ProjectManager.ProjectName=STM32MP157-DK1 +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=EWARM V8.32 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_IPCC_Init-IPCC-false-HAL-true,4-MX_SPI5_Init-SPI5-false-HAL-true,5-MX_TIM4_Init-TIM4-false-HAL-true,6-MX_TIM14_Init-TIM14-false-HAL-true,7-MX_TIM16_Init-TIM16-false-HAL-true,8-MX_TIM17_Init-TIM17-false-HAL-true,9-MX_UART4_Init-UART4-false-HAL-true,10-MX_ADC2_Init-ADC2-false-HAL-true,11-MX_DAC1_Init-DAC1-false-HAL-true,12-MX_LPTIM1_Init-LPTIM1-false-HAL-true,13-MX_LPTIM2_Init-LPTIM2-false-HAL-true,14-MX_LPTIM3_Init-LPTIM3-false-HAL-true,15-MX_LPTIM4_Init-LPTIM4-false-HAL-true,16-MX_LPTIM5_Init-LPTIM5-false-HAL-true,17-MX_USART3_UART_Init-USART3-false-HAL-true,18-MX_WWDG1_Init-WWDG1-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_PER +RCC.ADCFreq_Value=24000000 +RCC.AHB1234Freq_Value=208877929.6875 +RCC.APB1DIV=RCC_APB1_DIV2 +RCC.APB1Freq_Value=104438964.84375 +RCC.APB2DIV=RCC_APB2_DIV2 +RCC.APB2Freq_Value=104438964.84375 +RCC.APB3DIV=RCC_APB3_DIV2 +RCC.APB3Freq_Value=104438964.84375 +RCC.APB4DIV=RCC_APB4_DIV2 +RCC.APB4Freq_Value=133250000 +RCC.APB5DIV=RCC_APB5_DIV4 +RCC.APB5DIVClockFreq_Value=66625000 +RCC.AXICLKFreq_VALUE=266500000 +RCC.AXICLKSource=RCC_AXISSOURCE_PLL2 +RCC.AXIDIVFreq_Value=266500000 +RCC.CECFreq_Value=32768 +RCC.CKPERCLKFreq_VALUE=24000000 +RCC.CKPERCLKSource=RCC_CKPERCLKSOURCE_HSE +RCC.CSI_VALUE=4000000 +RCC.CortexFreq_Value=208877929.6875 +RCC.DACCLKFreq_VALUE=32000 +RCC.DDRCFreq_Value=533000000 +RCC.DDRPERFMFreq_Value=533000000 +RCC.DDRPHYFreq_Value=533000000 +RCC.DFSDFAFreq_Value=74250000 +RCC.DFSDMFreq_Value=208877929.6875 +RCC.DIVM1=3 +RCC.DIVM2=3 +RCC.DIVM3=2 +RCC.DIVM4=4 +RCC.DIVN1=81 +RCC.DIVN2=66 +RCC.DIVN3=34 +RCC.DIVN4=99 +RCC.DIVP1Freq_Value=650000000 +RCC.DIVP2Freq_Value=266500000 +RCC.DIVP3Freq_Value=208877929.6875 +RCC.DIVP4=6 +RCC.DIVP4Freq_Value=99000000 +RCC.DIVQ1Freq_Value=325000000 +RCC.DIVQ2=1 +RCC.DIVQ2Freq_Value=533000000 +RCC.DIVQ3=17 +RCC.DIVQ3Freq_Value=24573874.08088235 +RCC.DIVQ4=8 +RCC.DIVQ4Freq_Value=74250000 +RCC.DIVR1Freq_Value=325000000 +RCC.DIVR2=1 +RCC.DIVR2Freq_Value=533000000 +RCC.DIVR3=37 +RCC.DIVR3Freq_Value=11290698.902027028 +RCC.DIVR4=8 +RCC.DIVR4Freq_Value=74250000 +RCC.DSIFreq_Value=60000000 +RCC.DSIPixelFreq_Value=74250000 +RCC.DSITXEscFreq_Value=15000000 +RCC.DSI_VALUE=60000000 +RCC.ETHFreq_Value=99000000 +RCC.FCLKFreq_Value=196000000 +RCC.FDCANFreq_Value=24000000 +RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_ACLK +RCC.FMCFreq_Value=266500000 +RCC.FamilyName=M +RCC.HSE_VALUE=24000000 +RCC.HSIDivClkFreq_Value=64000000 +RCC.HSI_VALUE=64000000 +RCC.Hclk5DIVFreq_Value=266500000 +RCC.Hclk6DIVFreq_Value=266500000 +RCC.I2C12CLockSelection=RCC_I2C12CLKSOURCE_HSI +RCC.I2C12Freq_Value=64000000 +RCC.I2C35CLockSelection=RCC_I2C35CLKSOURCE_PCLK1 +RCC.I2C35Freq_Value=104438964.84375 +RCC.I2C46CLockSelection=RCC_I2C46CLKSOURCE_HSI +RCC.I2C46Freq_Value=64000000 +RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB1234Freq_Value,APB1DIV,APB1Freq_Value,APB2DIV,APB2Freq_Value,APB3DIV,APB3Freq_Value,APB4DIV,APB4Freq_Value,APB5DIV,APB5DIVClockFreq_Value,AXICLKFreq_VALUE,AXICLKSource,AXIDIVFreq_Value,CECFreq_Value,CKPERCLKFreq_VALUE,CKPERCLKSource,CSI_VALUE,CortexFreq_Value,DACCLKFreq_VALUE,DDRCFreq_Value,DDRPERFMFreq_Value,DDRPHYFreq_Value,DFSDFAFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVM4,DIVN1,DIVN2,DIVN3,DIVN4,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVP4,DIVP4Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVQ4,DIVQ4Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,DIVR4,DIVR4Freq_Value,DSIFreq_Value,DSIPixelFreq_Value,DSITXEscFreq_Value,DSI_VALUE,ETHFreq_Value,FCLKFreq_Value,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HSE_VALUE,HSIDivClkFreq_Value,HSI_VALUE,Hclk5DIVFreq_Value,Hclk6DIVFreq_Value,I2C12CLockSelection,I2C12Freq_Value,I2C35CLockSelection,I2C35Freq_Value,I2C46CLockSelection,I2C46Freq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM23CLockSelection,LPTIM23Freq_Value,LPTIM45CLockSelection,LPTIM45Freq_Value,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,MCUCLKFreq_VALUE,MCUCLKSource,MCUClockFreq_Value,MCUDIVCLKFreq_Value,MPUCLKFreq_VALUE,MPUCLKSource,PLL12Source,PLL1FRACV,PLL1UserDefinedConfig,PLL2FRACV,PLL3FRACV,PLL3Source,PLL4FRACV,PLL4PDSIFreq_Value,PLL4Source,PLLDSIFreq_Value,PLLDSIVCOFreq_Value,PUBLFreq_Value,QSPICLockSelection,QSPIFreq_Value,RCC_RTC_Clock_Source_FROM_HSE,RNG1CLockSelection,RNG1Freq_Value,RNG2Freq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2CLockSelection,SAI2Freq_Value,SAI3Freq_Value,SAI4Freq_Value,SDMMC12CLockSelection,SDMMC12Freq_Value,SDMMC3CLockSelection,SDMMC3Freq_Value,SPDIFRXFreq_Value,SPI1CLockSelection,SPI1Freq_Value,SPI23CLockSelection,SPI23Freq_Value,SPI45CLockSelection,SPI45Freq_Value,SPI6CLockSelection,SPI6Freq_Value,STGENCLockSelection,STGENFreq_Value,Tim1OutputFreq_Value,Tim2OutputFreq_Value,UART78CLockSelection,UART78Freq_Value,USART1CLockSelection,USART1Freq_Value,USART24CLockSelection,USART24Freq_Value,USART35CLockSelection,USART35Freq_Value,USART6CLockSelection,USART6Freq_Value,USBOCLKSource,USBOHSFreq_Value,USBPHYCLKSource,USBPHYFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCO4OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInput4Freq_Value +RCC.LPTIM1CLockSelection=RCC_LPTIM1CLKSOURCE_PCLK1 +RCC.LPTIM1Freq_Value=104438964.84375 +RCC.LPTIM23CLockSelection=RCC_LPTIM23CLKSOURCE_PCLK3 +RCC.LPTIM23Freq_Value=104438964.84375 +RCC.LPTIM45CLockSelection=RCC_LPTIM45CLKSOURCE_PCLK3 +RCC.LPTIM45Freq_Value=104438964.84375 +RCC.LSI_VALUE=32000 +RCC.LTDCFreq_Value=74250000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=650000000 +RCC.MCUCLKFreq_VALUE=208877929.6875 +RCC.MCUCLKSource=RCC_MCUSSOURCE_PLL3 +RCC.MCUClockFreq_Value=208877929.6875 +RCC.MCUDIVCLKFreq_Value=208877929.6875 +RCC.MPUCLKFreq_VALUE=650000000 +RCC.MPUCLKSource=RCC_MPUSOURCE_PLL1 +RCC.PLL12Source=RCC_PLL12SOURCE_HSE +RCC.PLL1FRACV=0x800 +RCC.PLL1UserDefinedConfig=false +RCC.PLL2FRACV=0x1400 +RCC.PLL3FRACV=6660 +RCC.PLL3Source=RCC_PLL3SOURCE_HSE +RCC.PLL4FRACV=0 +RCC.PLL4PDSIFreq_Value=99000000 +RCC.PLL4Source=RCC_PLL4SOURCE_HSE +RCC.PLLDSIFreq_Value=480000000 +RCC.PLLDSIVCOFreq_Value=960000000 +RCC.PUBLFreq_Value=533000000 +RCC.QSPICLockSelection=RCC_QSPICLKSOURCE_ACLK +RCC.QSPIFreq_Value=266500000 +RCC.RCC_RTC_Clock_Source_FROM_HSE=24 +RCC.RNG1CLockSelection=RCC_RNG1CLKSOURCE_LSI +RCC.RNG1Freq_Value=32000 +RCC.RNG2Freq_Value=4000000 +RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE +RCC.RTCFreq_Value=32768 +RCC.SAI1Freq_Value=74250000 +RCC.SAI2CLockSelection=RCC_SAI2CLKSOURCE_PLL3_Q +RCC.SAI2Freq_Value=24573874.08088235 +RCC.SAI3Freq_Value=74250000 +RCC.SAI4Freq_Value=74250000 +RCC.SDMMC12CLockSelection=RCC_SDMMC12CLKSOURCE_PLL4 +RCC.SDMMC12Freq_Value=99000000 +RCC.SDMMC3CLockSelection=RCC_SDMMC3CLKSOURCE_HCLK2 +RCC.SDMMC3Freq_Value=208877929.6875 +RCC.SPDIFRXFreq_Value=99000000 +RCC.SPI1CLockSelection=RCC_SPI1CLKSOURCE_PLL3_Q +RCC.SPI1Freq_Value=24573874.08088235 +RCC.SPI23CLockSelection=RCC_SPI23CLKSOURCE_PLL3_Q +RCC.SPI23Freq_Value=24573874.08088235 +RCC.SPI45CLockSelection=RCC_SPI45CLKSOURCE_PCLK2 +RCC.SPI45Freq_Value=104438964.84375 +RCC.SPI6CLockSelection=RCC_SPI6CLKSOURCE_PCLK5 +RCC.SPI6Freq_Value=66625000 +RCC.STGENCLockSelection=RCC_STGENCLKSOURCE_HSE +RCC.STGENFreq_Value=24000000 +RCC.Tim1OutputFreq_Value=208877929.6875 +RCC.Tim2OutputFreq_Value=208877929.6875 +RCC.UART78CLockSelection=RCC_UART78CLKSOURCE_PCLK1 +RCC.UART78Freq_Value=104438964.84375 +RCC.USART1CLockSelection=RCC_USART1CLKSOURCE_PCLK5 +RCC.USART1Freq_Value=66625000 +RCC.USART24CLockSelection=RCC_UART24CLKSOURCE_HSI +RCC.USART24Freq_Value=64000000 +RCC.USART35CLockSelection=RCC_UART35CLKSOURCE_PCLK1 +RCC.USART35Freq_Value=104438964.84375 +RCC.USART6CLockSelection=RCC_USART6CLKSOURCE_PCLK2 +RCC.USART6Freq_Value=104438964.84375 +RCC.USBOCLKSource=RCC_USBOCLKSOURCE_PHY +RCC.USBOHSFreq_Value=48000000 +RCC.USBPHYCLKSource=RCC_USBPHYCLKSOURCE_HSE +RCC.USBPHYFreq_Value=24000000 +RCC.VCO1OutputFreq_Value=1300000000 +RCC.VCO2OutputFreq_Value=1066000000 +RCC.VCO3OutputFreq_Value=417755859.375 +RCC.VCO4OutputFreq_Value=594000000 +RCC.VCOInput1Freq_Value=8000000 +RCC.VCOInput2Freq_Value=8000000 +RCC.VCOInput3Freq_Value=12000000 +RCC.VCOInput4Freq_Value=6000000 +SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1 +SH.COMP_DAC11_group.ConfNb=1 +SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2 +SH.S_TIM4_CH2.ConfNb=1 +SPI5.CalculateBaudRate=26.10974 MBits/s +SPI5.Direction=SPI_DIRECTION_2LINES_TXONLY +SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI5.Mode=SPI_MODE_MASTER +SPI5.VirtualType=VM_MASTER +TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM4.IPParameters=Channel-PWM Generation2 CH2 +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_BSEC_VS_BSEC.Mode=BSEC_Activate +VP_BSEC_VS_BSEC.Signal=BSEC_VS_BSEC +VP_DDR_DDR3.Mode=DDR3 +VP_DDR_DDR3.Signal=DDR_DDR3 +VP_DDR_DDR3_16_4Gb.Mode=4Gb_16bits +VP_DDR_DDR3_16_4Gb.Signal=DDR_DDR3_16_4Gb +VP_DDR_DDR_16_bits.Mode=16bits +VP_DDR_DDR_16_bits.Signal=DDR_DDR_16_bits +VP_DMA_VS_DMA1_A7NS.Mode=CortexA7NS +VP_DMA_VS_DMA1_A7NS.Signal=DMA_VS_DMA1_A7NS +VP_DMA_VS_DMA2_M4.Mode=CortexM4 +VP_DMA_VS_DMA2_M4.Signal=DMA_VS_DMA2_M4 +VP_HSEM_VS_HSEM.Mode=HSEM_Activate +VP_HSEM_VS_HSEM.Signal=HSEM_VS_HSEM +VP_IPCC_VS_IPCC.Mode=IPCC_Activate +VP_IPCC_VS_IPCC.Signal=IPCC_VS_IPCC +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_LPTIM1_VS_LPTIM_counterModeInternalClock.Signal=LPTIM1_VS_LPTIM_counterModeInternalClock +VP_LPTIM2_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_LPTIM2_VS_LPTIM_counterModeInternalClock.Signal=LPTIM2_VS_LPTIM_counterModeInternalClock +VP_LPTIM3_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_LPTIM3_VS_LPTIM_counterModeInternalClock.Signal=LPTIM3_VS_LPTIM_counterModeInternalClock +VP_LPTIM4_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_LPTIM4_VS_LPTIM_counterModeInternalClock.Signal=LPTIM4_VS_LPTIM_counterModeInternalClock +VP_LPTIM5_VS_LPTIM_counterModeInternalClock.Mode=Counts__internal_clock_event_00 +VP_LPTIM5_VS_LPTIM_counterModeInternalClock.Signal=LPTIM5_VS_LPTIM_counterModeInternalClock +VP_MDMA_VS_MDMA_A7NS_8.Mode=8\:8 +VP_MDMA_VS_MDMA_A7NS_8.Signal=MDMA_VS_MDMA_A7NS_8 +VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled +VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TAMP_VS_TAMP_Activate.Mode=TAMP_Enabled +VP_TAMP_VS_TAMP_Activate.Signal=TAMP_VS_TAMP_Activate +VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT +VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT +VP_VREFBUF_VS_VREFBUF.Mode=VREFBUF_Activate +VP_VREFBUF_VS_VREFBUF.Signal=VREFBUF_VS_VREFBUF +VP_WWDG1_VS_WWDG.Mode=WWDG_Activate +VP_WWDG1_VS_WWDG.Signal=WWDG1_VS_WWDG +WWDG1.IPParameters=Prescaler +WWDG1.Prescaler=WWDG_PRESCALER_8 +board=STM32MP157A-DK1 +boardIOC=true diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..bdcc20f611724c7d41dc404ffcd27affc70bda71 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig @@ -0,0 +1,177 @@ +menu "Hardware Drivers Config" + +config SOC_STM32MP157A + bool + select SOC_SERIES_STM32MP1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_STLINK_TO_USART + bool "Enable STLINK TO USART (uart4)" + select BSP_USING_UART + select BSP_USING_UART4 + default y + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_WWDG + bool "Enable WWDG" + select RT_USING_WWDG + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + select RT_USING_SERIAL + default y + if BSP_USING_UART + config BSP_USING_UART3 + bool "Enable UART3" + default y + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default y + + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + + config BSP_USING_TIM16 + bool "Enable TIM16" + default n + + config BSP_USING_TIM17 + bool "Enable TIM17" + default n + + endif + menuconfig BSP_USING_LPTIM + bool "Enable lptimer" + default n + select RT_USING_LPTIMER + if BSP_USING_LPTIM + config BSP_USING_LPTIM1 + bool "Enable LPTIM1" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable pwm" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM4 + bool "Enable timer4 output pwm" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4_CH2 + bool "Enable PWM4 channel2" + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "Enable DAC1" + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + if BSP_USING_I2C1 + comment "Notice: PD7 --> 55; PG15 --> 111" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 1 176 + default 55 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 111 + + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + select RT_USING_SPI + default n + if BSP_USING_SPI + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n + + config BSP_SPI5_TX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + endif + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/SConscript b/bsp/stm32/stm32mp157a-st-ev1/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..2d4657da929d2c3ba32d73646cb69dd611c16f43 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/SConscript @@ -0,0 +1,47 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Common/System/system_stm32mp1xx.c +CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +''') + +if GetDepend(['BSP_USING_ADC']): + src += Glob('ports/drv_hard_i2c.c') + src += Glob('ports/stpmic.c') + +if GetDepend(['BSP_USING_DAC']): + src += Glob('ports/drv_hard_i2c.c') + src += Glob('ports/stpmic.c') + +if GetDepend(['BSP_USING_WWDG']): + src += Glob('ports/drv_wwdg.c') + +if GetDepend(['BSP_USING_LPTIM']): + src += Glob('ports/drv_lptim.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/CM4/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/startup_stm32mp15xx.s'] + +CPPDEFINES = ['CORE_CM4', 'STM32MP157Axx', 'USE_HAL_DRIVER'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.c b/bsp/stm32/stm32mp157a-st-ev1/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..0a7bda208aae2553ef8b8e6108facdd15a4fab48 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.c @@ -0,0 +1,189 @@ +/* +* Copyright (c) 2006-2018, RT-Thread Development Team +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2018-11-06 SummerGift first version +* 2019-04-09 WillianChan add stm32f469-st-disco bsp +* 2020-06-20 thread-liu add stm32mp157-dk1 bsp +*/ + +#include "board.h" + +/** +* @brief System Clock Configuration +* @retval None +*/ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /**Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIG; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1; + + /**PLL1 Config + */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 3; + RCC_OscInitStruct.PLL.PLLN = 81; + RCC_OscInitStruct.PLL.PLLP = 1; + RCC_OscInitStruct.PLL.PLLQ = 1; + RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLFRACV = 0x800; + RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL; + RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; + RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; + + /**PLL2 Config + */ + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE; + RCC_OscInitStruct.PLL2.PLLM = 3; + RCC_OscInitStruct.PLL2.PLLN = 66; + RCC_OscInitStruct.PLL2.PLLP = 2; + RCC_OscInitStruct.PLL2.PLLQ = 1; + RCC_OscInitStruct.PLL2.PLLR = 1; + RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400; + RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL; + RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; + RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; + + /**PLL3 Config + */ + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE; + RCC_OscInitStruct.PLL3.PLLM = 2; + RCC_OscInitStruct.PLL3.PLLN = 34; + RCC_OscInitStruct.PLL3.PLLP = 2; + RCC_OscInitStruct.PLL3.PLLQ = 17; + RCC_OscInitStruct.PLL3.PLLR = 37; + RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1; + RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04; + RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL; + RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; + RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; + + /**PLL4 Config + */ + RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE; + RCC_OscInitStruct.PLL4.PLLM = 4; + RCC_OscInitStruct.PLL4.PLLN = 99; + RCC_OscInitStruct.PLL4.PLLP = 6; + RCC_OscInitStruct.PLL4.PLLQ = 8; + RCC_OscInitStruct.PLL4.PLLR = 8; + RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0; + RCC_OscInitStruct.PLL4.PLLFRACV = 0; + RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER; + RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED; + RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**RCC Clock Config + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4 + |RCC_CLOCKTYPE_PCLK5|RCC_CLOCKTYPE_MPU; + RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1; + RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2; + RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2; + RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1; + RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3; + RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1; + RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2; + RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4; + RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /**Set the HSE division factor for RTC clock + */ + __HAL_RCC_RTC_HSEDIV(24); +} + + +/** +* @brief Peripherals Common Clock Configuration +* @retval None +*/ +void PeriphCommonClock_Config(void) { + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Initializes the common periph clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER; + PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +} + +extern void rt_hw_systick_init(void); +extern int rt_hw_usart_init(void); +void rt_hw_board_init() +{ + /* HAL_Init() function is called at the beginning of the program */ + HAL_Init(); + + /* enable interrupt */ + __set_PRIMASK(0); + /* Configure the system clock */ + if (IS_ENGINEERING_BOOT_MODE()) { + /* Configure the system clock */ + SystemClock_Config(); + } + /* disable interrupt */ + __set_PRIMASK(1); + + rt_hw_systick_init(); + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Pin driver initialization is open by default */ +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/board.h b/bsp/stm32/stm32mp157a-st-ev1/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..b23b83ee30489012ee501e9208203ae609857164 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + * 2019-04-09 WillianChan add stm32f469-st-disco bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "stm32mp1xx.h" +#include "stm32mp1xx_hal.h" +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000) +#define STM32_FLASH_SIZE (256 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE (128) +#define STM32_SRAM_END ((uint32_t)0x10040000 + (STM32_SRAM_SIZE * 1024)) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end__; +#define HEAP_BEGIN (0x10040000 + 64 * 1024) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +extern void _Error_Handler(char *s, int num); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..9aa4aad24e577a197f903f38d13c2c70a73ade12 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x1003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10050000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1005FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +/* Create region for OPENAMP */ +/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/ +define symbol __OPENAMP_region_start__ = 0x10040000; +define symbol __OPENAMP_region_size__ = 0x8000; +export symbol __OPENAMP_region_start__; +export symbol __OPENAMP_region_size__; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..b2ae4c15ec7ac235203b49dd4c4c4cc813285593 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x10000000, LENGTH = 256k /* 256KB flash */ + RAM (rw) : ORIGIN = 0x10040000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..40d9679d172d016b0e15d7fd83ba6b37e3af90e5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/linker_scripts/link.sct @@ -0,0 +1,27 @@ +; ************************************************************* +; *** Scatter-Loading Description *** +; ************************************************************* + +LR_VECTORS 0x00000000 0x00000400 { ; load region size_region + .isr_vector +0 { + startup*.o (RESET, +First) + } +} + +LR_IROM1 0x10000000 0x00040000 { ; load region size_region + ER_IROM1 0x10000000 0x00040000 { ; load address = execution address + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x10050000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } + + +;; ***** Create region for OPENAMP ***** +;; *** These 4 lines can be commented if OPENAMP is not used ***** +; .resource_table +0 ALIGN 4 { ; resource table +; *(.resource_table) +; } __OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_hard_i2c.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_hard_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..f4bc430a110b0c8d62e09c066bf7d562c985e0dc --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_hard_i2c.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-18 thread-liu the first version + */ + +#include +#include "drv_hard_i2c.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.hardi2c" +#include + +I2C_HandleTypeDef hI2c4; + +int32_t BSP_I2C4_Init(void) +{ + int32_t status = RT_EOK; + + if (HAL_I2C_GetState(&hI2c4) == HAL_I2C_STATE_RESET) + { + if (MX_I2C4_Init(&hI2c4) != HAL_OK) + { + status = -RT_EBUSY; + } + /* Init the I2C Msp */ + if (HAL_I2C_Init(&hI2c4) != HAL_OK) + { + LOG_D("I2C4 Init Error!\n"); + status = -RT_EBUSY; + } + } + return status; +} + +int32_t BSP_I2C4_DeInit(void) +{ + int32_t status = RT_EOK; + + HAL_I2C_MspDeInit(&hI2c4); + + /* Init the I2C */ + if (HAL_I2C_DeInit(&hI2c4) != HAL_OK) + { + status = -RT_EEMPTY; + } + + return status; +} + +HAL_StatusTypeDef MX_I2C4_Init(I2C_HandleTypeDef *hI2c) +{ + hI2c4.Instance = I2C4; + hI2c->Init.Timing = I2C4_TIMING; + hI2c->Init.OwnAddress1 = STPMU1_I2C_ADDRESS; + hI2c->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hI2c->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hI2c->Init.OwnAddress2 = 0; + hI2c->Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hI2c->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hI2c->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + + return HAL_I2C_Init(hI2c); +} + +int32_t BSP_I2C4_WriteReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) +{ + return I2C4_WriteReg(DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length); +} + +int32_t BSP_I2C4_ReadReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) +{ + return I2C4_ReadReg(DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length); +} + +int32_t BSP_I2C4_WriteReg16(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) +{ + return I2C4_WriteReg(DevAddr, Reg, I2C_MEMADD_SIZE_16BIT, pData, Length); +} + +int32_t BSP_I2C4_ReadReg16(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) +{ + return I2C4_ReadReg(DevAddr, Reg, I2C_MEMADD_SIZE_16BIT, pData, Length); +} + +int32_t BSP_I2C4_IsReady(uint16_t DevAddr, uint32_t Trials) +{ + int32_t status = RT_EOK; + + if(HAL_I2C_IsDeviceReady(&hI2c4, DevAddr, Trials, 1000) != HAL_OK) + { + status = -RT_EBUSY; + } + + return status; +} + +static int32_t I2C4_WriteReg(uint16_t DevAddr, uint16_t Reg, uint16_t MemAddSize, uint8_t *pData, uint16_t Length) +{ + int32_t status = -RT_EIO; + + if(HAL_I2C_Mem_Write(&hI2c4, DevAddr, Reg, MemAddSize, pData, Length, 10000) == HAL_OK) + { + status = RT_EOK; + } + + return status; +} + +static int32_t I2C4_ReadReg(uint16_t DevAddr, uint16_t Reg, uint16_t MemAddSize, uint8_t *pData, uint16_t Length) +{ + int32_t status = -RT_EIO; + + if (HAL_I2C_Mem_Read(&hI2c4, DevAddr, Reg, MemAddSize, pData, Length, 10000) == HAL_OK) + { + status = RT_EOK; + } + + return status; +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_hard_i2c.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_hard_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..e3ec157d0c23817e77cd2beebf31170b4e60f4d5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_hard_i2c.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-18 thread-liu the first version + */ + +#ifndef __DRV_HARD_I2C_H__ +#define __DRV_HARD_I2C_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STPMU1_I2C_ADDRESS ((0x33 & 0x7F) << 1) + +#ifndef I2C_SPEED +#define I2C_SPEED ((uint32_t)100000) +#endif /* I2C_SPEED */ + +#ifndef I2C4_TIMING +#define I2C4_TIMING ((uint32_t)0x10805E89) +#endif + +static int32_t I2C4_WriteReg(uint16_t DevAddr, uint16_t MemAddSize, uint16_t Reg, uint8_t *pData, uint16_t Length); +static int32_t I2C4_ReadReg(uint16_t DevAddr, uint16_t MemAddSize, uint16_t Reg, uint8_t *pData, uint16_t Length); + +int32_t BSP_I2C4_Init(void); +int32_t BSP_I2C4_DeInit(void); +int32_t BSP_I2C4_WriteReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length); +int32_t BSP_I2C4_ReadReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length); +int32_t BSP_I2C4_WriteReg16(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length); +int32_t BSP_I2C4_ReadReg16(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length); +int32_t BSP_I2C4_IsReady(uint16_t DevAddr, uint32_t Trials); + +HAL_StatusTypeDef MX_I2C4_Init(I2C_HandleTypeDef *hI2c); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c new file mode 100644 index 0000000000000000000000000000000000000000..2b8d63b0ae8a5a1a3f158e6748c89df010b04f0a --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_lptim.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-19 thread-liu first version + */ + +#include + +#ifdef BSP_USING_LPTIM +#include "drv_config.h" +#include +#include + +//#define DRV_DEBUG +#define LOG_TAG "drv.lptimer" +#include + +LPTIM_HandleTypeDef hlptim1; + +void LPTIM1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_LPTIM_IRQHandler(&hlptim1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + if(hlptim->Instance == LPTIM1) + { + rt_kprintf("hello rt-thread!\n"); + } +} + +static int lptim_control(uint8_t pre_value) +{ + if(pre_value > 7) + { + pre_value = 7; + } + hlptim1.Instance->CFGR &= ~(7 << 9); /* clear PRESC[2:0] */ + hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0] */ + + return RT_EOK; +} + +/** + * This function initialize the lptim + */ +static int lptim_init(void) +{ + hlptim1.Instance = LPTIM1; + hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; + hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING; + hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION; + hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; + if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) + { + LOG_D("LPTIM Init Error!\n"); + return -RT_ERROR; + } + /* ### Start counting in interrupt mode ############################# */ + if (HAL_LPTIM_Counter_Start_IT(&hlptim1, 5000) != HAL_OK) + { + LOG_D("LPTIM Start Counting Error!\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static int lptim_deinit() +{ + if (HAL_LPTIM_DeInit(&hlptim1) != HAL_OK) + { + LOG_D("LPTIM Deinit Error!\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static int lptim_sample(int argc, char *argv[]) +{ + if (argc > 1) + { + if (!strcmp(argv[1], "run")) + { + lptim_init(); + } + else if (!strcmp(argv[1], "stop")) + { + lptim_deinit(); + } + else if (!strcmp(argv[1], "set")) + { + if (argc > 2) + { + lptim_control(atoi(argv[2])); + } + } + } + else + { + rt_kprintf("Usage:\n"); + rt_kprintf("lptim_sample run - open lptim, shell will printf 'hello rt-thread'\n"); + rt_kprintf("lptim_sample set - set the lptim prescaler, lptim_sample set [0 - 7]\n"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(lptim_sample, low power timer sample); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c new file mode 100644 index 0000000000000000000000000000000000000000..58c5c3f3032823984e2feb5e7b43ec2452e14367 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/drv_wwdg.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-18 thread-liu the first version + */ + +#include + +#if defined(BSP_USING_WWDG) +#include "drv_config.h" +#include +#include + +//#define DRV_DEBUG +#define LOG_TAG "drv.wwg" +#include + +#define LED5_PIN GET_PIN(A, 14) + +WWDG_HandleTypeDef hwwdg1; + +void WWDG1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_WWDG_IRQHandler(&hwwdg1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) +{ + static unsigned char led_value = 0x00; + + led_value = !led_value; + + if(hwwdg->Instance==WWDG1) + { + HAL_WWDG_Refresh(&hwwdg1); + rt_pin_write(LED5_PIN, led_value); + } +} + +static void wwdg_init() +{ + rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT); + + hwwdg1.Instance = WWDG1; + hwwdg1.Init.Prescaler = WWDG_PRESCALER_8; + hwwdg1.Init.Window = 0X5F; + hwwdg1.Init.Counter = 0x7F; + hwwdg1.Init.EWIMode = WWDG_EWI_ENABLE; + + if (HAL_WWDG_Init(&hwwdg1) != HAL_OK) + { + Error_Handler(); + } +} + +static void wwdg_control(uint8_t pre_value) +{ + if(pre_value > 7) + { + pre_value = 7; + } + hwwdg1.Instance->CFR &= ~(7 << 11); /* clear WDGTB[2:0] */ + hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */ +} + +static int wwdg_sample(int argc, char *argv[]) +{ + if (argc > 1) + { + if (!strcmp(argv[1], "run")) + { + wwdg_init(); + } + else if (!strcmp(argv[1], "set")) + { + if (argc > 2) + { + wwdg_control(atoi(argv[2])); + } + } + } + else + { + rt_kprintf("Usage:\n"); + rt_kprintf("wwdg_sample run - open wwdg, when feed wwdg in wwdg irq, the LD5 will blink\n"); + rt_kprintf("wwdg_sample set - set the wwdg prescaler, wwdg_sample set [0 - 7]\n"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(wwdg_sample, window watch dog sample); + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/stpmic.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/stpmic.c new file mode 100644 index 0000000000000000000000000000000000000000..42a252e679e9b25a7a5251723d57bd266166a2f5 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/stpmic.c @@ -0,0 +1,1225 @@ +/** + ****************************************************************************** + * @file stpmic.c + * @author MCD Application Team + * @brief This sample code provides hardware semaphore using HSEM for + * synchronization and mutual exclusion between heterogeneous processors + * and those not operating under a single, shared operating system. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include +#include +#include +#include "drv_hard_i2c.h" + +/* Definition of PMIC <=> stm32mp1 Signals */ +#define PMIC_INTn_PIN GPIO_PIN_0 +#define PMIC_INTn_PORT GPIOA +#define PMIC_INTn_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define PMIC_INTn_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +#define BSP_PMIC_PWRCTRL_PIN_Assert() HAL_GPIO_WritePin(PMIC_PWRCTRL_PORT, PMIC_PWRCTRL_PIN, GPIO_PIN_RESET); +#define BSP_PMIC_PWRCTRL_PIN_Pull() HAL_GPIO_WritePin(PMIC_PWRCTRL_PORT, PMIC_PWRCTRL_PIN, GPIO_PIN_SET); + +/** + * @} + */ + + /** @defgroup STM32MP15XX_EVAL_STPMU_Private_Defines Private Defines + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +typedef struct { + PMIC_RegulId_TypeDef id; + uint16_t *voltage_table; + uint8_t voltage_table_size; + uint8_t control_reg; + uint8_t low_power_reg; + uint8_t rank ; + uint8_t nvm_info ; +} regul_struct; + +/* Private define ------------------------------------------------------------*/ +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/* Those define should reflect NVM_USER section + * For ES Eval Configuration this is specified as + * 0xF7, + 0x92, + 0xC0, + 0x02, + 0xFA, + 0x30, + 0x00, + 0x33, + * */ +#define NVM_SECTOR3_REGISTER_0 0xF7 +#define NVM_SECTOR3_REGISTER_1 0x92 +#define NVM_SECTOR3_REGISTER_2 0xC0 +#define NVM_SECTOR3_REGISTER_3 0x02 +#define NVM_SECTOR3_REGISTER_4 0xFA +#define NVM_SECTOR3_REGISTER_5 0x30 +#define NVM_SECTOR3_REGISTER_6 0x00 +#define NVM_SECTOR3_REGISTER_7 0x33 + +/* nvm_vinok_hyst: VINOK hysteresis voltage + 00: 200mV + 01: 300mV + 10: 400mV + 11: 500mV + * + * nvm_vinok: VINOK threshold voltage + 00: 3.1v + 01: 3.3v + 10: 3.5v + 11: 4.5v + Otp_ldo4_forced : + 0: LDO4 ranks following OTP_RANK_LDO4<1:0> + if VBUS_OTG or SWOUT is turn ON condition + 1: LDO4 follows normal ranking procedure + + nvm_longkeypress: + 0: Turn OFF on long key press inactive + 1: Turn OFF on long key press active + + nvm_autoturnon: + 0: PMIC doesn’t start automatically on VIN rising + 1: PMIC starts automatically on VIN rising + + nvm_cc_keepoff : + 0: short circuit does not turn OFF PMIC + 1: short circuit turn OFF PMIC and keep it OFF till CC_flag is reset + + * + */ +#define OTP_VINOK_HYST ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) // nvm_vinok_hyst +#define OTP_VINOK ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) // nvm_vinok +#define OTP_LDO4_FORCED ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) // Otp_ldo4_forced +#define OTP_LONGKEYPRESSED ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2) // nvm_longkeypress +#define OTP_AUTOTURNON ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1) // nvm_autoturnon +#define OTP_CC_KEEPOFF ((NVM_SECTOR3_REGISTER_0 & 0x01)) // nvm_cc_keepoff + +/* + * nvm_rank_buck4: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + nvm_rank_buck3: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + nvm_rank_buck2: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + nvm_rank_buck1: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + * + */ +#define OTP_RANK_BUCK4 ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) // nvm_rank_buck4 +#define OTP_RANK_BUCK3 ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) // nvm_rank_buck3 +#define OTP_RANK_BUCK2 ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) // nvm_rank_buck2 +#define OTP_RANK_BUCK1 ((NVM_SECTOR3_REGISTER_1 & 0x03)) // nvm_rank_buck1 + + +/* + * nvm_rank_ldo4: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + nvm_rank_ldo3: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + nvm_rank_ldo2: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + nvm_rank_ldo1: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + * + */ +#define OTP_RANK_LDO4 ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) // nvm_rank_ldo4 +#define OTP_RANK_LDO3 ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) // nvm_rank_ldo3 +#define OTP_RANK_LDO2 ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) // nvm_rank_ldo2 +#define OTP_RANK_LDO1 ((NVM_SECTOR3_REGISTER_2 & 0x03)) // nvm_rank_ldo1 + +/* + * nvm_clamp_output_buck: Clamp output value to 1.3V max + 0: output_buck4<5:0> not clamped + 1: output_buck4<5:0> to b011100(1.3V) + + nvm_bypass_mode_ldo3: LDO3 forced bypass mode + 0: LDO3 not in bypass mode + 1: LDO3 in bypass mode + + nvm_rank_vrefddr: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + + nvm_rank_ldo6: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + +nvm_rank_ldo5: + 00: rank0 + 01: rank1 + 10: rank2 + 11: rank3 + * + */ +#define OTP_CLAMP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) // nvm_clamp_output_buck4 +#define OTP_BYPASS_MODE_LDO3 ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) // nvm_bypass_mode_ldo3 +#define OTP_RANK_VREFDDR ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) // nvm_rank_vrefddr +#define OTP_RANK_LDO6 ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) // nvm_rank_ldo6 +#define OTP_RANK_LDO5 ((NVM_SECTOR3_REGISTER_3 & 0x03)) // nvm_rank_ldo5 + +/* + * nvm_output_buck4: Buck4 default output selection + 00: 1.15V + 01: 1.2V + 10: 1.8V + 11: 3.3V + nvm_output_buck3: Buck3 default output selection + 00: 1.2V + 01: 1.8V + 10: 3.0V + 11: 3.3V + nvm_output_buck2: Buck2 default output selection + 00: 1.1V + 01: 1.2V + 10: 1.35V + 11: 1.5V + nvm_output_buck1: Buck1 default output selection + 00: 1.1V + 01: 1.15V + 10: 1.2V + 11: 1.25V + * + */ +#define OTP_OUTPUT_BUCK4 ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) // nvm_output_buck4 +#define OTP_OUTPUT_BUCK3 ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) // nvm_output_buck3 +#define OTP_OUTPUT_BUCK2 ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) // nvm_output_buck2 +#define OTP_OUTPUT_BUCK1 ((NVM_SECTOR3_REGISTER_4 & 0x03)) // nvm_output_buck1 + +/* + * [7] OTP_SWOFF_BY_BOOST_OVP: + 0 -> SWOUT will not turnoff bu boost OVP + 1 -> SWOUT will be turnoff by BOOST OVP + + [6] reserved + + [5:4] nvm_output_ldo3: LDO3 default output selection + 00: 1.8V + 01: 2.5V + 10: 3.3V + 11: output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog) + + [3:2] nvm_output_ldo2: LDO2 default output selection + 00: 1.8V + 01: 2.5V + 10: 2.9V + 11: 3.3V + + [1:0] nvm_output_ldo1: LDO1 default output selection + 00: 1.8V + 01: 2.5V + 10: 2.9V + 11: 3.3V + + * + */ +#define OTP_SWOFF_BY_BOOST_OVP ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) // OTP_SWOFF_BY_BOOST_OVP +#define OTP_OUTPUT_LDO3 ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) // nvm_output_ldo3 +#define OTP_OUTPUT_LDO2 ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) // nvm_output_ldo2 +#define OTP_OUTPUT_LDO1 ((NVM_SECTOR3_REGISTER_5 & 0x03)) // nvm_output_ldo1 + +/* + * [7:4] reserved + * + [3:2] nvm_output_ldo6: LDO6 default output selection + 00: 1.0V + 01: 1.2V + 10: 1.8V + 11: 3.3V + + [1:0] nvm_output_ldo5: LDO5 default output selection + 00: 1.8V + 01: 2.5V + 10: 2.9V + 11 : 3.3V + * + */ + +#define OTP_OUTPUT_LDO6 ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) // nvm_output_ldo6 +#define OTP_OUTPUT_LDO5 ((NVM_SECTOR3_REGISTER_6 & 0x03)) // nvm_output_ldo5 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* I2C handler declaration */ +I2C_HandleTypeDef I2cHandle; +extern I2C_HandleTypeDef hI2c4; + +uint16_t buck1_voltage_table[] = { + 600, + 625, + 650, + 675, + 700, + 725, + 750, + 775, + 800, + 825, + 850, + 875, + 900, + 925, + 950, + 975, + 1000, + 1025, + 1050, + 1075, + 1100, + 1125, + 1150, + 1175, + 1200, + 1225, + 1250, + 1275, + 1300, + 1325, + 1350, + 1350,// 31 1,35stm32mp15xx_eval_stpmu1.c +}; + +uint16_t buck2_voltage_table[] = { + 1000, // 1 + 1000, // + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1050, // 1,05 + 1050, // 1,05 + 1100, // 1,1 + 1100, // 1,1 + 1150, // 1,15 + 1150, // 1,15 + 1200, // 1,2 + 1200, // 1,2 + 1250, // 1,25 + 1250, // 1,25 + 1300, // 1,3 + 1300, // 1,3 + 1350, // 1,35 + 1350, // 1,35 + 1400, // 1,4 + 1400, // 1,4 + 1450, // 1,45 + 1450, // 1,45 + 1500, // 1,5 +}; + +uint16_t buck3_voltage_table[] = { + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1000, // 1 + 1100, // 1,1 + 1100, // 1,1 + 1100, // 1,1 + 1100, // 1,1 + 1200, // 1,2 + 1200, // 1,2 + 1200, // 1,2 + 1200, // 1,2 + 1300, // 1,3 + 1300, // 1,3 + 1300, // 1,3 + 1300, // 1,3 + 1400, // 1,4 + 1400, // 1,4 + 1400, // 1,4 + 1400, // 1,4 + 1500, // 1,5 + 1600, // 1,6 + 1700, // 1,7 + 1800, // 1,8 + 1900, // 1,9 + 2000, // 2 + 2100, // 2,1 + 2200, // 2,2 + 2300, // 2,3 + 2400, // 2,4 + 2500, // 2,5 + 2600, // 2,6 + 2700, // 2,7 + 2800, // 2,8 + 2900, // 2,9 + 3000, // 3 + 3100, // 3,1 + 3200, // 3,2 + 3300, // 3,3 + 3400, // 3,4 +}; + +uint16_t buck4_voltage_table[] = { + 600, + 625, + 650, + 675, + 700, + 725, + 750, + 775, + 800, + 825, + 850, + 875, + 900, + 925, + 950, + 975, + 1000, + 1025, + 1050, + 1075, + 1100, + 1125, + 1150, + 1175, + 1200, + 1225, + 1250, + 1275, + 1300, + 1300, + 1350, + 1350,// 31 1,35 + 1400,// 32 1,40 + 1400,// 33 1,40 + 1450,// 34 1,45 + 1450,// 35 1,45 + 1500,// 36 1,5 + 1600,// 37 1,6 + 1700,// 38 1,7 + 1800,// 39 1,8 + 1900,// 40 1,9 + 2000,// 41 2,0 + 2100,// 42 2,1 + 2200,// 43 2,2 + 2300,// 44 2,3 + 2400,// 45 2,4 + 2500,// 46 2,5 + 2600,// 47 2,6 + 2700,// 48 2,7 + 2800,// 49 2,8 + 2900,// 50 2,9 + 3000,// 51 3,0 + 3100,// 52 3,1 + 3200,// 53 3,2 + 3300,// 54 3,3 + 3400,// 55 3,4 + 3500,// 56 3,5 + 3600,// 57 3,6 + 3700,// 58 3,7 + 3800,// 59 3,8 + 3900,// 60 3,9 +}; + +uint16_t ldo1_voltage_table[] = { + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1800, // 1,8 + 1900, // 1,9 + 2000, // 2 + 2100, // 2,1 + 2200, // 2,2 + 2300, // 2,3 + 2400, // 2,4 + 2500, // 2,5 + 2600, // 2,6 + 2700, // 2,7 + 2800, // 2,8 + 2900, // 2,9 + 3000, // 3 + 3100, // 3,1 + 3200, // 3,2 + 3300, // 3,3 +}; + +uint16_t ldo2_voltage_table[] = { + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1800, // 1,8 + 1900, // 1,9 + 2000, // 2 + 2100, // 2,1 + 2200, // 2,2 + 2300, // 2,3 + 2400, // 2,4 + 2500, // 2,5 + 2600, // 2,6 + 2700, // 2,7 + 2800, // 2,8 + 2900, // 2,9 + 3000, // 3 + 3100, // 3,1 + 3200, // 3,2 + 3300, // 3,3 +}; + +uint16_t ldo3_voltage_table[] = { + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1800, // 1,8 + 1900, // 1,9 + 2000, // 2 + 2100, // 2,1 + 2200, // 2,2 + 2300, // 2,3 + 2400, // 2,4 + 2500, // 2,5 + 2600, // 2,6 + 2700, // 2,7 + 2800, // 2,8 + 2900, // 2,9 + 3000, // 3 + 3100, // 3,1 + 3200, // 3,2 + 3300, // 3,3 + 3300, // 3,3 + 3300, // 3,3 + 3300, // 3,3 + 3300, // 3,3 + 3300, // 3,3 + 3300, // 3,3 + 0xFFFF, // VREFDDR +}; + + +uint16_t ldo5_voltage_table[] = { + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1700, // 1,7 + 1800, // 1,8 + 1900, // 1,9 + 2000, // 2 + 2100, // 2,1 + 2200, // 2,2 + 2300, // 2,3 + 2400, // 2,4 + 2500, // 2,5 + 2600, // 2,6 + 2700, // 2,7 + 2800, // 2,8 + 2900, // 2,9 + 3000, // 3 + 3100, // 3,1 + 3200, // 3,2 + 3300, // 3,3 + 3400, // 3,4 + 3500, // 3,5 + 3600, // 3,6 + 3700, // 3,7 + 3800, // 3,8 + 3900, // 3,9 +}; + +uint16_t ldo6_voltage_table[] = { + 900, // 0,9 + 1000, // 1,0 + 1100, // 1,1 + 1200, // 1,2 + 1300, // 1,3 + 1400, // 1,4 + 1500, // 1,5 + 1600, // 1,6 + 1700, // 1,7 + 1800, // 1,8 + 1900, // 1,9 + 2000, // 2 + 2100, // 2,1 + 2200, // 2,2 + 2300, // 2,3 + 2400, // 2,4 + 2500, // 2,5 + 2600, // 2,6 + 2700, // 2,7 + 2800, // 2,8 + 2900, // 2,9 + 3000, // 3 + 3100, // 3,1 + 3200, // 3,2 + 3300, // 3,3 +}; + + +uint16_t ldo4_voltage_table[] = { + 3300, // 3,3 +}; + +uint16_t vref_ddr_voltage_table[] = { + 3300, // 3,3 +}; + +/* + Table of Regulators in PMIC SoC +*/ + + + +regul_struct regulators_table[] = { + { + .id = STPMU1_BUCK1, + .voltage_table = buck1_voltage_table, + .voltage_table_size = ARRAY_SIZE(buck1_voltage_table), + .control_reg = BUCK1_CONTROL_REG, + .low_power_reg = BUCK1_PWRCTRL_REG, + .rank = OTP_RANK_BUCK1, + }, + { + .id = STPMU1_BUCK2, + .voltage_table = buck2_voltage_table, + .voltage_table_size = ARRAY_SIZE(buck2_voltage_table), + .control_reg = BUCK2_CONTROL_REG, + .low_power_reg = BUCK2_PWRCTRL_REG, + .rank = OTP_RANK_BUCK2, + }, + { + .id = STPMU1_BUCK3, + .voltage_table = buck3_voltage_table, + .voltage_table_size = ARRAY_SIZE(buck3_voltage_table), + .control_reg = BUCK3_CONTROL_REG, + .low_power_reg = BUCK3_PWRCTRL_REG, + .rank = OTP_RANK_BUCK3, + }, + { + .id = STPMU1_BUCK4, + .voltage_table = buck4_voltage_table, + .voltage_table_size = ARRAY_SIZE(buck4_voltage_table), + .control_reg = BUCK4_CONTROL_REG, + .low_power_reg = BUCK4_PWRCTRL_REG, + .rank = OTP_RANK_BUCK4, + }, + { + .id = STPMU1_LDO1, + .voltage_table = ldo1_voltage_table, + .voltage_table_size = ARRAY_SIZE(ldo1_voltage_table), + .control_reg = LDO1_CONTROL_REG, + .low_power_reg = LDO1_PWRCTRL_REG, + .rank = OTP_RANK_LDO1, + }, + { + .id = STPMU1_LDO2, + .voltage_table = ldo2_voltage_table, + .voltage_table_size = ARRAY_SIZE(ldo2_voltage_table), + .control_reg = LDO2_CONTROL_REG, + .low_power_reg = LDO2_PWRCTRL_REG, + .rank = OTP_RANK_LDO2, + }, + + { + .id = STPMU1_LDO3, + .voltage_table = ldo3_voltage_table, + .voltage_table_size = ARRAY_SIZE(ldo3_voltage_table), + .control_reg = LDO3_CONTROL_REG, + .low_power_reg = LDO3_PWRCTRL_REG, + .rank = OTP_RANK_LDO3, + }, + { + .id = STPMU1_LDO4, + .voltage_table = ldo4_voltage_table, + .voltage_table_size = ARRAY_SIZE(ldo4_voltage_table), + .control_reg = LDO4_CONTROL_REG, + .low_power_reg = LDO4_PWRCTRL_REG, + .rank = OTP_RANK_LDO4, + }, + { + .id = STPMU1_LDO5, + .voltage_table = ldo5_voltage_table , + .voltage_table_size = ARRAY_SIZE(ldo5_voltage_table), + .control_reg = LDO5_CONTROL_REG, + .low_power_reg = LDO5_PWRCTRL_REG, + .rank = OTP_RANK_LDO5, + }, + { + .id = STPMU1_LDO6, + .voltage_table = ldo6_voltage_table , + .voltage_table_size = ARRAY_SIZE(ldo6_voltage_table), + .control_reg = LDO6_CONTROL_REG, + .low_power_reg = LDO6_PWRCTRL_REG, + .rank = OTP_RANK_LDO6, + }, + { + .id = STPMU1_VREFDDR, + .voltage_table = vref_ddr_voltage_table , + .voltage_table_size = ARRAY_SIZE(vref_ddr_voltage_table), + .control_reg = VREF_DDR_CONTROL_REG, + .low_power_reg = VREF_DDR_PWRCTRL_REG, + .rank = OTP_RANK_VREFDDR, + }, +}; + +#define MAX_REGUL ARRAY_SIZE(regulators_table) + + +/* Private function prototypes -----------------------------------------------*/ +void STPMU1_IrqHandler(void); +void STPMU1_INTn_Callback(PMIC_IRQn IRQn); +static void My_Error_Handler(void); +static regul_struct *STPMU1_Get_Regulator_Data(PMIC_RegulId_TypeDef id); +static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t milivolts); + +/* Private functions ---------------------------------------------------------*/ + +static regul_struct *STPMU1_Get_Regulator_Data(PMIC_RegulId_TypeDef id) +{ + uint8_t i ; + + for (i = 0 ; i < MAX_REGUL ; i++ ) + { + if (id == regulators_table[i].id) + return ®ulators_table[i]; + } + /* id not found */ + My_Error_Handler(); + return NULL; +} + +static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t milivolts) +{ + regul_struct *regul = STPMU1_Get_Regulator_Data(id); + uint8_t i; + for ( i = 0 ; i < regul->voltage_table_size ; i++) + { + if ( regul->voltage_table[i] == milivolts ) { + //printf("idx:%d for %dmV\n\r", (int)i, (int)milivolts); + return i; + } + } + /* voltage not found */ + My_Error_Handler(); + return 0; +} + +void STPMU1_Enable_Interrupt(PMIC_IRQn IRQn) +{ + uint8_t irq_reg , irq_reg_value ; + + if (IRQn >= IRQ_NR) + return ; + + /* IRQ register is IRQ Number divided by 8 */ + irq_reg = IRQn >> 3 ; + + /* value to be set in IRQ register corresponds to BIT(7-N) where N is the Interrupt id modulo 8 */ + irq_reg_value = 1 << ( 7 - ( IRQn%8 ) ); + + /* Clear previous event stored in latch */ + STPMU1_Register_Write(ITCLEARLATCH1_REG+irq_reg, irq_reg_value ); + + /* Clear relevant mask to enable interrupt */ + STPMU1_Register_Write(ITCLEARMASK1_REG+irq_reg, irq_reg_value ); + +} + +extern void STPMU1_Disable_Interrupt(PMIC_IRQn IRQn) +{ + uint8_t irq_reg , irq_reg_value ; + + if (IRQn >= IRQ_NR) + return ; + + /* IRQ register is IRQ Number divided by 8 */ + irq_reg = IRQn >> 3 ; + + /* value to be set in IRQ register corresponds to BIT(7-N) where N is the Interrupt id modulo 8 */ + irq_reg_value = 1 << ( 7 - ( IRQn%8 ) ); + + /* Clear previous event stored in latch */ + STPMU1_Register_Write(ITCLEARLATCH1_REG+irq_reg, irq_reg_value ); + + /* Set relevant mask to disable interrupt */ + STPMU1_Register_Write(ITSETMASK1_REG+irq_reg, irq_reg_value ); +} + + +void STPMU1_IrqHandler(void) +{ + uint8_t irq_reg,mask,latch_events,i; + + for (irq_reg = 0 ; irq_reg < STM32_PMIC_NUM_IRQ_REGS ; irq_reg++) + { + /* Get latch events & active mask from register */ + mask = STPMU1_Register_Read(ITMASK1_REG+irq_reg); + latch_events = STPMU1_Register_Read(ITLATCH1_REG+irq_reg) & ~mask ; + + /* Go through all bits for each register */ + for (i = 0 ; i < 8 ; i++ ) + { + if ( latch_events & ( 1 << i ) ) + { + /* Callback with parameter computes as "PMIC Interrupt" enum */ + STPMU1_INTn_Callback( (PMIC_IRQn )(irq_reg*8 + (7-i))); + } + } + /* Clear events in appropriate register for the event with mask set */ + STPMU1_Register_Write(ITCLEARLATCH1_REG+irq_reg, latch_events ); + } +} + + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +static void My_Error_Handler(void) +{ + while(1) + { + HAL_Delay(500); + } +} + + +void STPMU1_Sw_Reset(void) +{ + /* Write 1 in bit 0 of MAIN_CONTROL Register */ + STPMU1_Register_Update(MAIN_CONTROL_REG, SET , SOFTWARE_SWITCH_OFF_ENABLED ); +} + +void STPMU1_Regulator_Enable(PMIC_RegulId_TypeDef id) +{ + regul_struct *regul = STPMU1_Get_Regulator_Data(id); + + STPMU1_Register_Update(regul->control_reg,BIT(0),BIT(0)); +} + +void STPMU1_Regulator_Disable(PMIC_RegulId_TypeDef id) +{ + regul_struct *regul = STPMU1_Get_Regulator_Data(id); + + STPMU1_Register_Update(regul->control_reg,0,BIT(0)); +} + +uint8_t STPMU1_Is_Regulator_Enabled(PMIC_RegulId_TypeDef id) +{ + uint8_t val ; + + regul_struct *regul = STPMU1_Get_Regulator_Data(id); + + val = STPMU1_Register_Read(regul->control_reg); + + return (val&0x1); +} + +void STPMU1_Regulator_Voltage_Set(PMIC_RegulId_TypeDef id,uint16_t milivolts) +{ + uint8_t voltage_index = STPMU1_Voltage_Find_Index(id,milivolts); + regul_struct *regul = STPMU1_Get_Regulator_Data(id); + STPMU1_Register_Update(regul->control_reg, voltage_index<<2 , 0xFC ); +} + +/* register direct access */ +uint8_t STPMU1_Register_Read(uint8_t register_id) +{ + uint32_t status = RT_EOK; + uint8_t Value = 0; + + status = BSP_I2C4_ReadReg(STPMU1_I2C_ADDRESS, (uint16_t)register_id, &Value, 1); + + /* Check the communication status */ + if(status != RT_EOK) + { + My_Error_Handler(); + } + return Value; +} + +void STPMU1_Register_Write(uint8_t register_id, uint8_t value) +{ + uint32_t status = RT_EOK; + + status = BSP_I2C4_WriteReg(STPMU1_I2C_ADDRESS, (uint16_t)register_id, &value, 1); + + /* Check the communication status */ + if(status != RT_EOK) + { + My_Error_Handler(); + } + + /* verify register content */ + if ((register_id!=WATCHDOG_CONTROL_REG) && (register_id<=0x40)) + { + uint8_t readval = STPMU1_Register_Read(register_id); + if (readval != value) + { + My_Error_Handler(); + } + } +} + +void STPMU1_Register_Update(uint8_t register_id, uint8_t value, uint8_t mask) +{ + uint8_t initial_value ; + + initial_value = STPMU1_Register_Read(register_id); + + /* Clear bits to update */ + initial_value &= ~mask; + + /* Update appropriate bits*/ + initial_value |= ( value & mask ); + + /* Send new value on I2C Bus */ + STPMU1_Register_Write(register_id, initial_value); + + return ; +} + +/* + * + * PMIC init + * pmic provides power supply on this board + * it is configured to turn off some power supply in standby mode + * + */ +static uint32_t BSP_PMIC_MspInit(I2C_HandleTypeDef *hi2c) +{ + uint32_t status = RT_EOK; + GPIO_InitTypeDef GPIO_InitStruct; + + /*##-1- Configure the I2C clock source, GPIO and Interrupt #*/ + BSP_I2C4_Init(); + + /*##-2- Configure PMIC GPIOs Interface ########################################*/ + + /* INTn - Interrupt Line - Active Low (Falling Edge) */ + PMIC_INTn_CLK_ENABLE(); + GPIO_InitStruct.Pin = PMIC_INTn_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = 0 ; + HAL_GPIO_Init(PMIC_INTn_PORT, &GPIO_InitStruct); + + /* Enable and set INTn EXTI Interrupt */ +#if defined(CORE_CA7) + IRQ_SetPriority(EXTI0_IRQn, 0); + IRQ_Enable(EXTI0_IRQn); +#elif defined(CORE_CM4) + HAL_NVIC_SetPriority(EXTI0_IRQn, 0x03, 0x00); + HAL_NVIC_EnableIRQ(EXTI0_IRQn); +#endif + + return status; +} + +static uint32_t BSP_PMIC_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + uint32_t status = RT_EOK; + /*##-1- Reset I2C Clock / Disable peripherals and GPIO Clocks###############*/ + status = BSP_I2C4_DeInit(); + + /*##-2- Disable PMIC clk ###########################################*/ + PMIC_INTn_CLK_DISABLE(); + + /*##-3- Disable the NVIC for PMIC ##########################################*/ +#if defined(CORE_CA7) + IRQ_Disable(EXTI0_IRQn); +#elif defined(CORE_CM4) + HAL_NVIC_DisableIRQ(EXTI0_IRQn); +#endif + HAL_GPIO_DeInit(PMIC_INTn_PORT,PMIC_INTn_PIN); + + return status; +} + +uint32_t BSP_PMIC_Is_Device_Ready(void) +{ + int32_t status = RT_EOK; + + /* Write the TxBuffer1 at @0, then read @0 when device ready */ + if (BSP_I2C4_IsReady(STPMU1_I2C_ADDRESS, 1) != RT_EOK) + { + status = -RT_EBUSY; + } + return status ; +} + +/* Use Xls I2C COnfiguration Tools with I2C Clock config + output clocks requirement */ +#define I2C_TIMING 0x10805E89 + +uint32_t BSP_PMIC_Init(void) +{ + int32_t status = RT_EOK; + PMIC_IRQn irq; + + /*##-1- Configure the I2C peripheral ######################################*/ + BSP_PMIC_MspInit(&hI2c4); + + status = BSP_PMIC_Is_Device_Ready(); + if (status != RT_EOK ) + { + return status; + } + + if (STPMU1_Register_Read(VERSION_STATUS_REG) != 0x00) + { + status = -RT_EIO; + return status; + } + + STPMU1_Enable_Interrupt(IT_PONKEY_R); + STPMU1_Enable_Interrupt(IT_PONKEY_F); + /* enable all irqs */ + for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) + { + STPMU1_Enable_Interrupt(irq); + } + + return RT_EOK; +} + +uint32_t BSP_PMIC_DeInit(void) +{ + uint32_t status = RT_EOK; + if(HAL_I2C_GetState(&hI2c4) != HAL_I2C_STATE_RESET) + { + /* Deinit the I2C */ + BSP_PMIC_MspDeInit(&hI2c4); + } + return status; +} + +/* + * + * following are configurations for this board + * same configuration than linux + * + * BSP_PMIC_InitRegulators set the regulators for boot + * BSP_PMIC_PrepareLpStop set the low power registers for LPSTOP mode + * should be called by user before entering is CSTOP + * BSP_PMIC_PrepareLpStop set the low power registers for STANDBY mode + * should be called by user before entering is STANDBY + * + * + */ +/* following are configurations */ +uint32_t BSP_PMIC_InitRegulators(void) +{ + uint32_t status = RT_EOK; + + STPMU1_Register_Write(MAIN_CONTROL_REG, 0x04); + STPMU1_Register_Write(VIN_CONTROL_REG, 0xc0); + STPMU1_Register_Write(USB_CONTROL_REG, 0x30); + + STPMU1_Register_Write(MASK_RESET_BUCK_REG, 0x04); + STPMU1_Register_Write(MASK_RESET_LDO_REG, 0x00); + STPMU1_Register_Write(MASK_RANK_BUCK_REG, 0x00); + STPMU1_Register_Write(MASK_RANK_LDO_REG, 0x00); + STPMU1_Register_Write(BUCK_PULL_DOWN_REG, 0x00); + STPMU1_Register_Write(LDO14_PULL_DOWN_REG, 0x00); + STPMU1_Register_Write(LDO56_PULL_DOWN_REG, 0x00); + STPMU1_Register_Write(BUCK_ICC_TURNOFF_REG, 0x30); + STPMU1_Register_Write(LDO_ICC_TURNOFF_REG, 0x3b); + + /* vddcore */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK1, 1200); + STPMU1_Regulator_Enable(STPMU1_BUCK1); + + /* vddddr */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK2, 1350); + STPMU1_Regulator_Enable(STPMU1_BUCK2); + + /* vdd */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK3, 3300); + STPMU1_Regulator_Enable(STPMU1_BUCK3); + + /* 3v3 */ + STPMU1_Regulator_Voltage_Set(STPMU1_BUCK4, 3300); + STPMU1_Regulator_Enable(STPMU1_BUCK4); + + /* vdda */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO1, 2900); + STPMU1_Regulator_Enable(STPMU1_LDO1); + + /* 2v8 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO2, 2800); + STPMU1_Regulator_Enable(STPMU1_LDO2); + + /* vtt_ddr lod3 mode buck2/2 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO3, 0xFFFF); + STPMU1_Regulator_Enable(STPMU1_LDO3); + + /* vdd_usb */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO4, 3300); + STPMU1_Regulator_Enable(STPMU1_LDO4); + + /* vdd_sd */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO5, 2900); + STPMU1_Regulator_Enable(STPMU1_LDO5); + + /* 1v8 */ + STPMU1_Regulator_Voltage_Set(STPMU1_LDO6, 1800); + STPMU1_Regulator_Enable(STPMU1_LDO6); + + STPMU1_Regulator_Enable(STPMU1_VREFDDR); + + return status; +} + +uint32_t BSP_PMIC_SwitchOff(void) +{ + uint32_t status = RT_EOK; + + STPMU1_Register_Write(MAIN_CONTROL_REG, 0x01); + return status; +} + +__weak void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn) +{ + switch (IRQn) + { + case IT_PONKEY_F: + rt_kprintf("IT_PONKEY_F"); + break; + + case IT_PONKEY_R: + rt_kprintf("IT_PONKEY_R"); + break; + + case IT_WAKEUP_F: + rt_kprintf("IT_WAKEUP_F"); + break; + + case IT_WAKEUP_R: + rt_kprintf("IT_WAKEUP_R"); + break; + + case IT_VBUS_OTG_F: + rt_kprintf("IT_VBUS_OTG_F"); + break; + + case IT_SWOUT_F: + rt_kprintf("IT_SWOUT_F"); + break; + + case IT_TWARN_R: + rt_kprintf("IT_TWARN_R"); + break; + + case IT_TWARN_F: + rt_kprintf("IT_TWARN_F"); + break; + + default: + rt_kprintf("%d",IRQn); + break; + } + rt_kprintf(" Interrupt received\n\r"); +} + +void STPMU1_INTn_Callback(PMIC_IRQn IRQn) +{ + BSP_PMIC_INTn_Callback(IRQn); +} + +void BSP_PMIC_INTn_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(PMIC_INTn_PIN); + + STPMU1_IrqHandler(); +} + +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hI2c4) +{ + while(1); +} diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/stpmic.h b/bsp/stm32/stm32mp157a-st-ev1/board/ports/stpmic.h new file mode 100644 index 0000000000000000000000000000000000000000..4b5e47b892e70fddd92476e75aa0999b27759813 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/stpmic.h @@ -0,0 +1,315 @@ +/** + ****************************************************************************** + * @file stm32mp15xx__stpmic1.h + * @author MCD Application Team + * @brief stpmu driver functions used for ST internal validation + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + * + ****************************************************************************** + */ + +#ifndef __STPMIC_H__ +#define __STPMIC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +/* Exported types ------------------------------------------------------------*/ +typedef enum +{ + STPMU1_BUCK1=1, + STPMU1_BUCK2, + STPMU1_BUCK3, + STPMU1_BUCK4, + STPMU1_LDO1, + STPMU1_LDO2, + STPMU1_LDO3, + STPMU1_LDO4, + STPMU1_LDO5, + STPMU1_LDO6, + STPMU1_VREFDDR, +}PMIC_RegulId_TypeDef; + +/* IRQ definitions */ +typedef enum { + +/* Interrupt Register 1 (0x50 for latch) */ +IT_SWOUT_R, +IT_SWOUT_F, +IT_VBUS_OTG_R, +IT_VBUS_OTG_F, +IT_WAKEUP_R, +IT_WAKEUP_F, +IT_PONKEY_R, +IT_PONKEY_F, + +/* Interrupt Register 2 (0x51 for latch) */ +IT_OVP_BOOST, +IT_OCP_BOOST, +IT_OCP_SWOUT, +IT_OCP_OTG, +IT_CURLIM_BUCK4, +IT_CURLIM_BUCK3, +IT_CURLIM_BUCK2, +IT_CURLIM_BUCK1, + +/* Interrupt Register 3 (0x52 for latch) */ +IT_SHORT_SWOUT, +IT_SHORT_SWOTG, +IT_CURLIM_LDO6, +IT_CURLIM_LDO5, +IT_CURLIM_LDO4, +IT_CURLIM_LDO3, +IT_CURLIM_LDO2, +IT_CURLIM_LDO1, + +/* Interrupt Register 3 (0x52 for latch) */ +IT_SWIN_R, +IT_SWIN_F, +IT_RESERVED_1, +IT_RESERVED_2, +IT_VINLOW_R, +IT_VINLOW_F, +IT_TWARN_R, +IT_TWARN_F, + +IRQ_NR, +} PMIC_IRQn; + +/** + * @} + */ + +/** @defgroup STM32MP15XX_EVAL_STPMU_Exported_Constants Exported Constants + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +#define BIT(_x) (1<<(_x)) +#define STM32_PMIC_NUM_IRQ_REGS 4 + +#define TURN_ON_REG 0x1 +#define TURN_OFF_REG 0x2 +#define ICC_LDO_TURN_OFF_REG 0x3 +#define ICC_BUCK_TURN_OFF_REG 0x4 +#define RESET_STATUS_REG 0x5 +#define VERSION_STATUS_REG 0x6 +#define MAIN_CONTROL_REG 0x10 +#define PADS_PULL_REG 0x11 +#define BUCK_PULL_DOWN_REG 0x12 +#define LDO14_PULL_DOWN_REG 0x13 +#define LDO56_PULL_DOWN_REG 0x14 +#define VIN_CONTROL_REG 0x15 +#define PONKEY_TIMER_REG 0x16 +#define MASK_RANK_BUCK_REG 0x17 +#define MASK_RESET_BUCK_REG 0x18 +#define MASK_RANK_LDO_REG 0x19 +#define MASK_RESET_LDO_REG 0x1A +#define WATCHDOG_CONTROL_REG 0x1B +#define WATCHDOG_TIMER_REG 0x1C +#define BUCK_ICC_TURNOFF_REG 0x1D +#define LDO_ICC_TURNOFF_REG 0x1E +#define BUCK_APM_CONTROL_REG 0x1F +#define BUCK1_CONTROL_REG 0x20 +#define BUCK2_CONTROL_REG 0x21 +#define BUCK3_CONTROL_REG 0x22 +#define BUCK4_CONTROL_REG 0x23 +#define VREF_DDR_CONTROL_REG 0x24 +#define LDO1_CONTROL_REG 0x25 +#define LDO2_CONTROL_REG 0x26 +#define LDO3_CONTROL_REG 0x27 +#define LDO4_CONTROL_REG 0x28 +#define LDO5_CONTROL_REG 0x29 +#define LDO6_CONTROL_REG 0x2A +#define BUCK1_PWRCTRL_REG 0x30 +#define BUCK2_PWRCTRL_REG 0x31 +#define BUCK3_PWRCTRL_REG 0x32 +#define BUCK4_PWRCTRL_REG 0x33 +#define VREF_DDR_PWRCTRL_REG 0x34 +#define LDO1_PWRCTRL_REG 0x35 +#define LDO2_PWRCTRL_REG 0x36 +#define LDO3_PWRCTRL_REG 0x37 +#define LDO4_PWRCTRL_REG 0x38 +#define LDO5_PWRCTRL_REG 0x39 +#define LDO6_PWRCTRL_REG 0x3A +#define FREQUENCY_SPREADING_REG 0x3B +#define USB_CONTROL_REG 0x40 +#define ITLATCH1_REG 0x50 +#define ITLATCH2_REG 0x51 +#define ITLATCH3_REG 0x52 +#define ITLATCH4_REG 0x53 +#define ITSETLATCH1_REG 0x60 +#define ITSETLATCH2_REG 0x61 +#define ITSETLATCH3_REG 0x62 +#define ITSETLATCH4_REG 0x63 +#define ITCLEARLATCH1_REG 0x70 +#define ITCLEARLATCH2_REG 0x71 +#define ITCLEARLATCH3_REG 0x72 +#define ITCLEARLATCH4_REG 0x73 +#define ITMASK1_REG 0x80 +#define ITMASK2_REG 0x81 +#define ITMASK3_REG 0x82 +#define ITMASK4_REG 0x83 +#define ITSETMASK1_REG 0x90 +#define ITSETMASK2_REG 0x91 +#define ITSETMASK3_REG 0x92 +#define ITSETMASK4_REG 0x93 +#define ITCLEARMASK1_REG 0xA0 +#define ITCLEARMASK2_REG 0xA1 +#define ITCLEARMASK3_REG 0xA2 +#define ITCLEARMASK4_REG 0xA3 +#define ITSOURCE1_REG 0xB0 +#define ITSOURCE2_REG 0xB1 +#define ITSOURCE3_REG 0xB2 +#define ITSOURCE4_REG 0xB3 +#define LDO_VOLTAGE_MASK 0x7C +#define BUCK_VOLTAGE_MASK 0xFC +#define LDO_BUCK_VOLTAGE_SHIFT 2 + +#define LDO_ENABLE_MASK 0x01 +#define BUCK_ENABLE_MASK 0x01 +#define BUCK_HPLP_ENABLE_MASK 0x02 +#define LDO_HPLP_ENABLE_MASK 0x02 +#define LDO_BUCK_HPLP_SHIFT 1 + +#define LDO_BUCK_RANK_MASK 0x01 +#define LDO_BUCK_RESET_MASK 0x01 +#define LDO_BUCK_PULL_DOWN_MASK 0x03 + + +/* Main PMIC Control Register + * MAIN_CONTROL_REG + * Address : 0x10 + * */ +#define ICC_EVENT_ENABLED BIT(4) +#define PWRCTRL_POLARITY_HIGH BIT(3) +#define PWRCTRL_PIN_VALID BIT(2) +#define RESTART_REQUEST_ENABLED BIT(1) +#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) + +/* Main PMIC PADS Control Register + * PADS_PULL_REG + * Address : 0x11 + * */ +#define WAKEUP_DETECTOR_DISABLED BIT(4) +#define PWRCTRL_PD_ACTIVE BIT(3) +#define PWRCTRL_PU_ACTIVE BIT(2) +#define WAKEUP_PD_ACTIVE BIT(1) +#define PONKEY_PU_ACTIVE BIT(0) + + +/* Main PMIC VINLOW Control Register + * VIN_CONTROL_REGC DMSC + * Address : 0x15 + * */ +#define SWIN_DETECTOR_ENABLED BIT(7) +#define SWOUT_DETECTOR_ENABLED BIT(6) +#define VINLOW_HYST_MASK 0x3 +#define VINLOW_HYST_SHIFT 4 +#define VINLOW_THRESHOLD_MASK 0x7 +#define VINLOW_THRESHOLD_SHIFT 1 +#define VINLOW_ENABLED 0x01 +#define VINLOW_CTRL_REG_MASK 0xFF + + +/* USB Control Register + * Address : 0x40 + * */ +#define BOOST_OVP_DISABLED BIT(7) +#define VBUS_OTG_DETECTION_DISABLED BIT(6) +// Discharge not implemented +#define OCP_LIMIT_HIGH BIT(3) +#define SWIN_SWOUT_ENABLED BIT(2) +#define USBSW_OTG_SWITCH_ENABLED BIT(1) + + +/* IRQ masks */ +/* Interrupt Mask for Register 1 (0x50 for latch) */ +#define IT_SWOUT_R_MASK BIT(7) +#define IT_SWOUT_F_MASK BIT(6) +#define IT_VBUS_OTG_R_MASK BIT(5) +#define IT_VBUS_OTG_F_MASK BIT(4) +#define IT_WAKEUP_R_MASK BIT(3) +#define IT_WAKEUP_F_MASK BIT(2) +#define IT_PONKEY_R_MASK BIT(1) +#define IT_PONKEY_F_MASK BIT(0) + +/* Interrupt Mask for Register 2 (0x51 for latch) */ +#define IT_OVP_BOOST_MASK BIT(7) +#define IT_OCP_BOOST_MASK BIT(6) +#define IT_OCP_SWOUT_MASK BIT(5) +#define IT_OCP_OTG_MASK BIT(4) +#define IT_CURLIM_BUCK4_MASK BIT(3) +#define IT_CURLIM_BUCK3_MASK BIT(2) +#define IT_CURLIM_BUCK2_MASK BIT(1) +#define IT_CURLIM_BUCK1_MASK BIT(0) + +/* Interrupt Mask for Register 3 (0x52 for latch) */ +#define IT_SHORT_SWOUT_MASK BIT(7) +#define IT_SHORT_SWOTG_MASK BIT(6) +#define IT_CURLIM_LDO6_MASK BIT(5) +#define IT_CURLIM_LDO5_MASK BIT(4) +#define IT_CURLIM_LDO4_MASK BIT(3) +#define IT_CURLIM_LDO3_MASK BIT(2) +#define IT_CURLIM_LDO2_MASK BIT(1) +#define IT_CURLIM_LDO1_MASK BIT(0) + +/* Interrupt Mask for Register 4 (0x53 for latch) */ +#define IT_SWIN_R_MASK BIT(7) +#define IT_SWIN_F_MASK BIT(6) +/* Reserved 1 */ +/* Reserved 2 */ +#define IT_VINLOW_R_MASK BIT(3) +#define IT_VINLOW_F_MASK BIT(2) +#define IT_TWARN_R_MASK BIT(1) +#define IT_TWARN_F_MASK BIT(0) + +#define PMIC_VERSION_ID 0x10 + +#define NVM_SECTOR3_REGISTER_7 0x33 +//#define STPMU1_I2C_ADDRESS ((NVM_SECTOR3_REGISTER_7 & 0x7F) << 1 ) + +/** + * @} + */ + +/** @defgroup STM32MP15XX_EVAL_STPMU_Exported_Functions Exported Functions + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ +uint8_t STPMU1_Register_Read(uint8_t register_id); +void STPMU1_Register_Write(uint8_t register_id, uint8_t value); +void STPMU1_Register_Update(uint8_t register_id, uint8_t value, uint8_t mask); +void STPMU1_Enable_Interrupt(PMIC_IRQn IRQn); +void STPMU1_Disable_Interrupt(PMIC_IRQn IRQn); +void STPMU1_Regulator_Enable(PMIC_RegulId_TypeDef id); +void STPMU1_Regulator_Disable(PMIC_RegulId_TypeDef id); +uint8_t STPMU1_Is_Regulator_Enabled(PMIC_RegulId_TypeDef id); +void STPMU1_Regulator_Voltage_Set(PMIC_RegulId_TypeDef id,uint16_t milivolts); +uint32_t BSP_PMIC_Init(void); +uint32_t BSP_PMIC_DeInit(void); +uint32_t BSP_PMIC_Is_Device_Ready(void); +uint32_t BSP_PMIC_InitRegulators (void); +__weak void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/figures/board.png b/bsp/stm32/stm32mp157a-st-ev1/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..887ef13d1123c10b32d9005144117ea5e6648bd8 Binary files /dev/null and b/bsp/stm32/stm32mp157a-st-ev1/figures/board.png differ diff --git a/bsp/stm32/stm32mp157a-st-ev1/figures/boot.png b/bsp/stm32/stm32mp157a-st-ev1/figures/boot.png new file mode 100644 index 0000000000000000000000000000000000000000..17fcb76fc68b090dc6cf613040cb85d5d8dcabf6 Binary files /dev/null and b/bsp/stm32/stm32mp157a-st-ev1/figures/boot.png differ diff --git a/bsp/stm32/stm32mp157a-st-ev1/makefile.targets b/bsp/stm32/stm32mp157a-st-ev1/makefile.targets new file mode 100644 index 0000000000000000000000000000000000000000..a00129bd90590dcf655a0e6c5ac8f530e7b5c383 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/makefile.targets @@ -0,0 +1,4 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' \ No newline at end of file diff --git a/bsp/stm32/stm32mp157a-st-ev1/project.ewd b/bsp/stm32/stm32mp157a-st-ev1/project.ewd new file mode 100644 index 0000000000000000000000000000000000000000..ee078b5a148c08e8d546bf45c90310053d9ae3cf --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/project.ewd @@ -0,0 +1,2966 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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..\..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + STM32_HAL + + + stm32mp1xx_hal.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal.c + + + stm32mp1xx_hal_hsem.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_hsem.c + + + stm32mp1xx_hal_exti.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_exti.c + + + stm32mp1xx_hal_ipcc.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_ipcc.c + + + stm32mp1xx_hal_cortex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_cortex.c + + + stm32mp1xx_hal_dma.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_dma.c + + + stm32mp1xx_hal_dma_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_dma_ex.c + + + stm32mp1xx_hal_mdma.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_mdma.c + + + stm32mp1xx_hal_pwr.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_pwr.c + + + stm32mp1xx_hal_pwr_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_pwr_ex.c + + + stm32mp1xx_hal_rcc.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_rcc.c + + + stm32mp1xx_hal_rcc_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_rcc_ex.c + + + stm32mp1xx_hal_gpio.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_gpio.c + + + stm32mp1xx_hal_adc.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_adc.c + + + stm32mp1xx_hal_adc_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_adc_ex.c + + + stm32mp1xx_hal_dac.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_dac.c + + + stm32mp1xx_hal_dac_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_dac_ex.c + + + stm32mp1xx_hal_i2c.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_i2c.c + + + stm32mp1xx_hal_i2c_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_i2c_ex.c + + + stm32mp1xx_hal_spi.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_spi.c + + + stm32mp1xx_hal_tim.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_tim.c + + + stm32mp1xx_hal_tim_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_tim_ex.c + + + stm32mp1xx_hal_uart.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_uart.c + + + stm32mp1xx_hal_uart_ex.c + 1 + ..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_uart_ex.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.h b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..65772b7eac35fb971e9debba6ceea7ae99b836eb --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.h @@ -0,0 +1,175 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32MP1 + +/* Hardware Drivers Config */ + +#define SOC_STM32MP157A + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_STLINK_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART4 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..b1cad1d512dc8b7682bbe8e0402812c9801a84e8 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.ewp b/bsp/stm32/stm32mp157a-st-ev1/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..6d6c615d16e243dda5021ec03d0a6f2710564720 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/template.ewp @@ -0,0 +1,2106 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.eww b/bsp/stm32/stm32mp157a-st-ev1/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..c62178f07a5e15c70d24add2b6f369e079d7a335 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.uvopt b/bsp/stm32/stm32mp157a-st-ev1/template.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..ed90c9e187e8063cc4d07cc09e28620f73aeac3f --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/template.uvopt @@ -0,0 +1,167 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U -O207 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + JL2CM3 + -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx b/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..e3a94d45ec46ef7c2eca71b4f388ff96197a76b7 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/template.uvoptx @@ -0,0 +1,192 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FC1000 -FD10020000 + + + 0 + ST-LINKIII-KEIL_SWO + -U066BFF343339415043223048 -O206 -SF10000 -C0 -A2 -I0 -HNlocalhost -HP7184 -P1 -N00("") -D00(00000000) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10050000 -FC1000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 0 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx b/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..67a2556f75a9ada9f3a9d9abfad201342a29d444 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-ev1/template.uvprojx @@ -0,0 +1,411 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32MP157AAAx:Cortex-M4 + STMicroelectronics + Keil.STM32MP1xx_DFP.1.3.0 + http://www.keil.com/pack/ + IRAM(0x10020000,0x00020000) IRAM2(0x10040000,0x00020000) IROM(0x10000000,0x00020000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) + + + UL2CM3(-S0 -C0 -P0 -FD10020000 -FC1000) + 0 + $$Device:STM32MP157AAAx$Drivers\CMSIS\Device\ST\STM32MP1xx\Include\stm32mp157axx_cm4.h + + + + + + + + + + $$Device:STM32MP157AAAx$SVD\STM32MP157x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10020000 + 0x20000 + + + 1 + 0x10000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10050000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/components/dfs/src/dfs_fs.c b/components/dfs/src/dfs_fs.c index 476e47fc06e59387fd285a27d00e74e810c93a4c..c21b914727cda5eb811069225bad2e13d2d0210a 100644 --- a/components/dfs/src/dfs_fs.c +++ b/components/dfs/src/dfs_fs.c @@ -129,7 +129,7 @@ const char *dfs_filesystem_get_mounted_path(struct rt_device *device) for (iter = &filesystem_table[0]; iter < &filesystem_table[DFS_FILESYSTEMS_MAX]; iter++) { - /* fint the mounted device */ + /* find the mounted device */ if (iter->ops == NULL) continue; else if (iter->dev_id == device) { @@ -321,7 +321,7 @@ int dfs_mount(const char *device_name, if (rt_device_open(fs->dev_id, RT_DEVICE_OFLAG_RDWR) != RT_EOK) { - /* The underlaying device has error, clear the entry. */ + /* The underlying device has error, clear the entry. */ dfs_lock(); memset(fs, 0, sizeof(struct dfs_filesystem)); @@ -568,8 +568,7 @@ int dfs_unmount_device(rt_device_t dev) iter < &filesystem_table[DFS_FILESYSTEMS_MAX]; iter++) { /* check if the PATH is mounted */ - if ((iter->dev_id->parent.name != NULL) - && (strcmp(iter->dev_id->parent.name, dev->parent.name) == 0)) + if (strcmp(iter->dev_id->parent.name, dev->parent.name) == 0) { fs = iter; break; diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 4ebde1512501702199abe6a56d1f752c8d0fa53d..457b8751fe760ab990c6e025cca70a50030b882f 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -95,12 +95,12 @@ if RT_USING_I2C config RT_USING_I2C_BITOPS bool "Use GPIO to simulate I2C" default y -endif -if RT_USING_I2C_BITOPS - config RT_I2C_BITOPS_DEBUG - bool "Use simulate I2C debug message" - default n + if RT_USING_I2C_BITOPS + config RT_I2C_BITOPS_DEBUG + bool "Use simulate I2C debug message" + default n + endif endif config RT_USING_PIN diff --git a/components/drivers/include/drivers/usb_common.h b/components/drivers/include/drivers/usb_common.h index c26d83391e89fceaf1b33fc3d0296b36e4582486..4d85a85e35003d195cf93ae6f5a79318a6ec1555 100644 --- a/components/drivers/include/drivers/usb_common.h +++ b/components/drivers/include/drivers/usb_common.h @@ -435,15 +435,15 @@ typedef struct usb_os_proerty * usb_os_proerty_t; // 5 A big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) // 6 A NULL-terminated Unicode string that contains a symbolic link (REG_LINK) // 7 Multiple NULL-terminated Unicode strings (REG_MULTI_SZ) -#define USB_OS_PROERTY_TYPE_REG_SZ 0x01UL -#define USB_OS_PROERTY_TYPE_REG_EXPAND_SZ 0x02UL -#define USB_OS_PROERTY_TYPE_REG_BINARY 0x03UL -#define USB_OS_PROERTY_TYPE_REG_DWORD_LITTLE_ENDIAN 0x04UL -#define USB_OS_PROERTY_TYPE_REG_DWORD_BIG_ENDIAN 0x05UL -#define USB_OS_PROERTY_TYPE_REG_LINK 0x06UL -#define USB_OS_PROERTY_TYPE_REG_MULTI_SZ 0x07UL - -#define USB_OS_PROERTY_DESC(PropertyDataType,PropertyName,PropertyData) \ +#define USB_OS_PROPERTY_TYPE_REG_SZ 0x01UL +#define USB_OS_PROPERTY_TYPE_REG_EXPAND_SZ 0x02UL +#define USB_OS_PROPERTY_TYPE_REG_BINARY 0x03UL +#define USB_OS_PROPERTY_TYPE_REG_DWORD_LITTLE_ENDIAN 0x04UL +#define USB_OS_PROPERTY_TYPE_REG_DWORD_BIG_ENDIAN 0x05UL +#define USB_OS_PROPERTY_TYPE_REG_LINK 0x06UL +#define USB_OS_PROPERTY_TYPE_REG_MULTI_SZ 0x07UL + +#define USB_OS_PROPERTY_DESC(PropertyDataType,PropertyName,PropertyData) \ {\ .dwSize = sizeof(struct usb_os_proerty)-sizeof(const char *)*2\ +sizeof(PropertyName)*2+sizeof(PropertyData)*2,\ diff --git a/components/drivers/rtc/rtc.c b/components/drivers/rtc/rtc.c index e17c0fe7ddf1332c28ab220c590ea37cd8fea71a..682515ce98a3d853e39a00c1b0e55987674d4f6b 100644 --- a/components/drivers/rtc/rtc.c +++ b/components/drivers/rtc/rtc.c @@ -179,7 +179,7 @@ void list_date(void) time_t now; now = time(RT_NULL); - rt_kprintf("%s\n", ctime(&now)); + rt_kprintf("%.*s\n", 25, ctime(&now)); } FINSH_FUNCTION_EXPORT(list_date, show date and time.) @@ -194,7 +194,7 @@ static void date(uint8_t argc, char **argv) time_t now; /* output current time */ now = time(RT_NULL); - rt_kprintf("%s", ctime(&now)); + rt_kprintf("%.*s", 25, ctime(&now)); } else if (argc >= 7) { diff --git a/components/drivers/usb/usbdevice/class/winusb.c b/components/drivers/usb/usbdevice/class/winusb.c index bf4b353d739674249f3fb23b2d9771100a332f1e..729e39f6636ee21f015ea7cf77808d2d5e7aa199 100644 --- a/components/drivers/usb/usbdevice/class/winusb.c +++ b/components/drivers/usb/usbdevice/class/winusb.c @@ -121,7 +121,7 @@ const static char* _ustring[] = ALIGN(4) struct usb_os_proerty winusb_proerty[] = { - USB_OS_PROERTY_DESC(USB_OS_PROERTY_TYPE_REG_SZ,"DeviceInterfaceGUID",RT_WINUSB_GUID), + USB_OS_PROPERTY_DESC(USB_OS_PROPERTY_TYPE_REG_SZ,"DeviceInterfaceGUID",RT_WINUSB_GUID), }; ALIGN(4) diff --git a/components/libc/compilers/armlibc/stubs.c b/components/libc/compilers/armlibc/stubs.c index b6ffb37b0f0938c3118977951c43c6f4841c8285..b4cc13799e8c6b8e07e9dc8abe4198923aa8a0e9 100644 --- a/components/libc/compilers/armlibc/stubs.c +++ b/components/libc/compilers/armlibc/stubs.c @@ -9,6 +9,8 @@ * 2013-11-24 aozima fixed _sys_read()/_sys_write() issues. * 2014-08-03 bernard If using msh, use system() implementation * in msh. + * 2020-08-05 Meco Man fixed _sys_flen() compiling-warning when + * RT_USING_DFS is not defined */ #include @@ -265,16 +267,16 @@ RT_WEAK void _sys_exit(int return_code) */ long _sys_flen(FILEHANDLE fh) { +#ifdef RT_USING_DFS struct stat stat; - + if (fh < STDERR) return -1; -#ifndef RT_USING_DFS - return -1; -#else fstat(fh, &stat); return stat.st_size; +#else + return -1; #endif } diff --git a/include/rtdef.h b/include/rtdef.h index b391ff76851290efe98739c07100bb97e090a1d9..5543b80ab73484eed32f4e2f7149459ba0b8d310 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -32,6 +32,7 @@ * 2019-01-27 Bernard change version number to v4.0.1 * 2019-05-17 Bernard change version number to v4.0.2 * 2019-12-20 Bernard change version number to v4.0.3 + * 2020-08-10 Meco Man add macro for struct rt_device_ops */ #ifndef __RT_DEF_H__ @@ -372,20 +373,20 @@ typedef struct rt_object *rt_object_t; /**< Type for kernel obj */ enum rt_object_class_type { - RT_Object_Class_Null = 0, /**< The object is not used. */ - RT_Object_Class_Thread, /**< The object is a thread. */ - RT_Object_Class_Semaphore, /**< The object is a semaphore. */ - RT_Object_Class_Mutex, /**< The object is a mutex. */ - RT_Object_Class_Event, /**< The object is a event. */ - RT_Object_Class_MailBox, /**< The object is a mail box. */ - RT_Object_Class_MessageQueue, /**< The object is a message queue. */ - RT_Object_Class_MemHeap, /**< The object is a memory heap */ - RT_Object_Class_MemPool, /**< The object is a memory pool. */ - RT_Object_Class_Device, /**< The object is a device */ - RT_Object_Class_Timer, /**< The object is a timer. */ - RT_Object_Class_Module, /**< The object is a module. */ - RT_Object_Class_Unknown, /**< The object is unknown. */ - RT_Object_Class_Static = 0x80 /**< The object is a static object. */ + RT_Object_Class_Null = 0x00, /**< The object is not used. */ + RT_Object_Class_Thread = 0x01, /**< The object is a thread. */ + RT_Object_Class_Semaphore = 0x02, /**< The object is a semaphore. */ + RT_Object_Class_Mutex = 0x03, /**< The object is a mutex. */ + RT_Object_Class_Event = 0x04, /**< The object is a event. */ + RT_Object_Class_MailBox = 0x05, /**< The object is a mail box. */ + RT_Object_Class_MessageQueue = 0x06, /**< The object is a message queue. */ + RT_Object_Class_MemHeap = 0x07, /**< The object is a memory heap. */ + RT_Object_Class_MemPool = 0x08, /**< The object is a memory pool. */ + RT_Object_Class_Device = 0x09, /**< The object is a device. */ + RT_Object_Class_Timer = 0x0a, /**< The object is a timer. */ + RT_Object_Class_Module = 0x0b, /**< The object is a module. */ + RT_Object_Class_Unknown = 0x0c, /**< The object is unknown. */ + RT_Object_Class_Static = 0x80 /**< The object is a static object. */ }; /** @@ -920,6 +921,8 @@ enum rt_device_class_type #define RT_DEVICE_CTRL_RTC_SET_ALARM 0x13 /**< set alarm */ typedef struct rt_device *rt_device_t; + +#ifdef RT_USING_DEVICE_OPS /** * operations set for device object */ @@ -933,6 +936,7 @@ struct rt_device_ops rt_size_t (*write) (rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); rt_err_t (*control)(rt_device_t dev, int cmd, void *args); }; +#endif /** * WaitQueue structure diff --git a/src/ipc.c b/src/ipc.c index 8e8c4db8422cf8820b2352c7ec921a8a0828e260..5646fc7f4062403d6b52e04f860db83769d6f9c4 100644 --- a/src/ipc.c +++ b/src/ipc.c @@ -34,6 +34,8 @@ * 2013-09-14 Grissiom add an option check in rt_event_recv * 2018-10-02 Bernard add 64bit support for mailbox * 2019-09-16 tyx add send wait support for message queue + * 2020-07-29 Meco Man fix thread->event_set/event_info when received an + event without pending */ #include @@ -117,6 +119,9 @@ rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t *list, rt_list_insert_before(list, &(thread->tlist)); } break; + + default: + break; } return RT_EOK; @@ -685,7 +690,9 @@ rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t time) } else { +#ifdef RT_USING_SIGNALS __again: +#endif /* end of RT_USING_SIGNALS */ /* The value of mutex is 1 in initial status. Therefore, if the * value is great than 0, it indicates the mutex is avaible. */ @@ -754,8 +761,10 @@ __again: if (thread->error != RT_EOK) { +#ifdef RT_USING_SIGNALS /* interrupt by signal, try it again */ if (thread->error == -RT_EINTR) goto __again; +#endif /* end of RT_USING_SIGNALS */ /* return error */ return thread->error; @@ -1080,6 +1089,13 @@ rt_err_t rt_event_send(rt_event_t event, rt_uint32_t set) status = RT_EOK; } } + else + { + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + return -RT_EINVAL; + } /* move node to the next */ n = n->next; @@ -1177,7 +1193,11 @@ rt_err_t rt_event_recv(rt_event_t event, /* set received event */ if (recved) *recved = (event->set & set); - + + /* fill thread event info */ + thread->event_set = (event->set & set); + thread->event_info = option; + /* received event */ if (option & RT_EVENT_FLAG_CLEAR) event->set &= ~set; @@ -1186,10 +1206,10 @@ rt_err_t rt_event_recv(rt_event_t event, { /* no waiting */ thread->error = -RT_ETIMEOUT; - + /* enable interrupt */ rt_hw_interrupt_enable(level); - + return -RT_ETIMEOUT; } else diff --git a/src/kservice.c b/src/kservice.c index 1705ce5283bf6a3c5df1f9c252b22f1184b80335..7caf43ce28dec29e93ec9c5af9eaf352dd3ab6ea 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -456,7 +456,10 @@ RTM_EXPORT(rt_strncmp); rt_int32_t rt_strcmp(const char *cs, const char *ct) { while (*cs && *cs == *ct) - cs++, ct++; + { + cs++; + ct++; + } return (*cs - *ct); } @@ -543,7 +546,7 @@ void rt_show_version(void) RTM_EXPORT(rt_show_version); /* private function */ -#define isdigit(c) ((unsigned)((c) - '0') < 10) +#define _ISDIGIT(c) ((unsigned)((c) - '0') < 10) #ifdef RT_PRINTF_LONGLONG rt_inline int divide(long long *n, int base) @@ -588,7 +591,7 @@ rt_inline int divide(long *n, int base) rt_inline int skip_atoi(const char **s) { register int i = 0; - while (isdigit(**s)) + while (_ISDIGIT(**s)) i = i * 10 + *((*s)++) - '0'; return i; @@ -834,7 +837,7 @@ rt_int32_t rt_vsnprintf(char *buf, /* get field width */ field_width = -1; - if (isdigit(*fmt)) field_width = skip_atoi(&fmt); + if (_ISDIGIT(*fmt)) field_width = skip_atoi(&fmt); else if (*fmt == '*') { ++ fmt; @@ -853,7 +856,7 @@ rt_int32_t rt_vsnprintf(char *buf, if (*fmt == '.') { ++ fmt; - if (isdigit(*fmt)) precision = skip_atoi(&fmt); + if (_ISDIGIT(*fmt)) precision = skip_atoi(&fmt); else if (*fmt == '*') { ++ fmt; diff --git a/src/scheduler.c b/src/scheduler.c index 6baaa9627a24eda244d49c1d32491a5e0b864bd3..0c1bf1e506cfa3832bba71f09c197c4a43827ab0 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -33,10 +33,6 @@ #include #include -#ifdef RT_USING_SMP -rt_hw_spinlock_t _rt_critical_lock; -#endif /*RT_USING_SMP*/ - rt_list_t rt_thread_priority_table[RT_THREAD_PRIORITY_MAX]; rt_uint32_t rt_thread_ready_priority_group; #if RT_THREAD_PRIORITY_MAX > 32 @@ -851,7 +847,7 @@ void rt_enter_critical(void) if (!current_thread) { rt_hw_local_irq_enable(level); - return ; + return; } /* @@ -859,12 +855,15 @@ void rt_enter_critical(void) * enough and does not check here */ - /* lock scheduler for all cpus */ - if (current_thread->critical_lock_nest == 0) { - rt_hw_spin_lock(&_rt_critical_lock); + register rt_uint16_t lock_nest = current_thread->cpus_lock_nest; + current_thread->cpus_lock_nest++; + if (lock_nest == 0) + { + current_thread->scheduler_lock_nest ++; + rt_hw_spin_lock(&_cpus_lock); + } } - /* critical for local cpu */ current_thread->critical_lock_nest ++; @@ -910,16 +909,18 @@ void rt_exit_critical(void) if (!current_thread) { rt_hw_local_irq_enable(level); - return ; + return; } current_thread->scheduler_lock_nest --; current_thread->critical_lock_nest --; - if (current_thread->critical_lock_nest == 0) + current_thread->cpus_lock_nest--; + if (current_thread->cpus_lock_nest == 0) { - rt_hw_spin_unlock(&_rt_critical_lock); + current_thread->scheduler_lock_nest --; + rt_hw_spin_unlock(&_cpus_lock); } if (current_thread->scheduler_lock_nest <= 0) diff --git a/src/timer.c b/src/timer.c index 28a5a9e494ced8176f2efb74923feb767a2d3723..4d12c7ec782bd8468cc3f72e8b17a9433547a92a 100644 --- a/src/timer.c +++ b/src/timer.c @@ -500,7 +500,10 @@ rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg) /*timer is stop*/ *(rt_tick_t *)arg = RT_TIMER_FLAG_DEACTIVATED; } - break; + break; + + default: + break; } return RT_EOK;