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    Optimize ctrlblock timing (#620) · c1b37c81
    ljw 提交于
    * CtrlBlock: delay exception flush for 1 cycle
    
    * CtrlBlock: delay load replay for 1 cycle
    
    * roq: delay wb from exu for one clock cycle to meet timing
    
    * CtrlBlock: fix pipeline bug between decode and rename
    Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
    c1b37c81
CtrlBlock.scala 16.3 KB