Disable L2 and L3 in MinimalConfig

src/main/scala/system/SoC.scala

@@ -12,11 +12,11 @@ case class SoCParameters
 (
   cores: List[XSCoreParameters],
   EnableILA: Boolean = false,
-  extIntrs: Int = 150
+  extIntrs: Int = 150,
+  useFakeL3Cache: Boolean = false
 ){
   val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
   // L3 configurations
-  val useFakeL3Cache = false
   val L3InnerBusWidth = 256
   val L3Size = 4 * 1024 * 1024 // 4MB
   val L3BlockSize = 64

src/main/scala/top/ArgParser.scala

@@ -29,7 +29,7 @@ object ArgParser {
     val c = Class.forName(prefix + confString).getConstructor(Integer.TYPE)
     c.newInstance(1.asInstanceOf[Object]).asInstanceOf[Parameters]
   }
-  def parse(args: Array[String]): (Parameters, Array[String]) = {
+  def parse(args: Array[String], fpga: Boolean = true): (Parameters, Array[String]) = {
     val default = new DefaultConfig(1)
     var firrtlOpts = Array[String]()
     @tailrec
@@ -68,6 +68,12 @@ object ArgParser {
           nextOption(config, tail)
       }
     }
-    (nextOption(default, args.toList), firrtlOpts)
+    var config = nextOption(default, args.toList)
+    if(!fpga){
+      config = config.alter((site, here, up) => {
+        case DebugOptionsKey => up(DebugOptionsKey).copy(FPGAPlatform = false)
+      })
+    }
+    (config, firrtlOpts)
   }
 }

src/main/scala/top/Configs.scala

@@ -25,7 +25,6 @@ class MinimalConfig(n: Int = 1) extends Config(
   new DefaultConfig(n).alter((site, here, up) => {
     case SoCParamsKey => up(SoCParamsKey).copy(
       cores = up(SoCParamsKey).cores.map(_.copy(
-        HasL2Cache = false,
         IssQueSize = 8,
         NRPhyRegs = 80,
         LoadQueueSize = 16,
@@ -44,7 +43,17 @@ class MinimalConfig(n: Int = 1) extends Config(
         ),
         EnableBPD = false, // disable TAGE
         EnableLoop = false,
-      ))
+        TlbEntrySize = 4,
+        TlbSPEntrySize = 2,
+        PtwL1EntrySize = 2,
+        PtwL2EntrySize = 2,
+        PtwL3EntrySize = 4,
+        PtwSPEntrySize = 2,
+        useFakeDCache = true,
+        useFakePTW = true,
+        useFakeL1plusCache = true,
+      )),
+      useFakeL3Cache = true
     )
   })
 )
\ No newline at end of file

src/main/scala/xiangshan/Parameters.scala

@@ -14,7 +14,6 @@ case object XSCoreParamsKey extends Field[XSCoreParameters]
 
 case class XSCoreParameters
 (
-  HasL2Cache: Boolean = false,
   HasPrefetch: Boolean = false,
   HartId: Int = 0,
   XLEN: Int = 64,
@@ -93,6 +92,9 @@ case class XSCoreParameters
   PtwL1EntrySize: Int = 16,
   PtwL2EntrySize: Int = 2048, //(256 * 8)
   NumPerfCounters: Int = 16,
+  useFakePTW: Boolean = false,
+  useFakeDCache: Boolean = false,
+  useFakeL1plusCache: Boolean = false
 ){
   val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
   val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg)
@@ -195,7 +197,6 @@ trait HasXSParameter {
   val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
   val TlbEntrySize = coreParams.TlbEntrySize
   val TlbSPEntrySize = coreParams.TlbSPEntrySize
-  val useFakePTW = false
   val PtwL3EntrySize = coreParams.PtwL3EntrySize
   val PtwSPEntrySize = coreParams.PtwSPEntrySize
   val PtwL1EntrySize = coreParams.PtwL1EntrySize
@@ -212,7 +213,6 @@ trait HasXSParameter {
     nMissEntries = 2
   )
 
-  val useFakeL1plusCache = false
   val l1plusCacheParameters = L1plusCacheParameters(
     tagECC = Some("secded"),
     dataECC = Some("secded"),
@@ -220,7 +220,6 @@ trait HasXSParameter {
     nMissEntries = 8
   )
 
-  val useFakeDCache = false
   val dcacheParameters = DCacheParameters(
     tagECC = Some("secded"),
     dataECC = Some("secded"),
@@ -237,6 +236,9 @@ trait HasXSParameter {
   // cache hierarchy configurations
   val l1BusDataWidth = 256
 
+  val useFakeDCache = coreParams.useFakeDCache
+  val useFakePTW = coreParams.useFakePTW
+  val useFakeL1plusCache = coreParams.useFakeL1plusCache
   // L2 configurations
   val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache
   val L1BusWidth = 256

src/test/scala/top/SimTop.scala

@@ -71,7 +71,7 @@ class SimTop(implicit p: Parameters) extends Module {
 object SimTop extends App {
 
   override def main(args: Array[String]): Unit = {
-    val (config, firrtlOpts) = ArgParser.parse(args)
+    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
     // generate verilog
     XiangShanStage.execute(
       firrtlOpts,