- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 27 5月, 2021 1 次提交
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由 Yinan Xu 提交于
* backend,RS: add numEnq parameter to allow multiple enqueue instructions * backend,RS: support multiple issue instructions at each cycle
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- 15 5月, 2021 1 次提交
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由 Yinan Xu 提交于
* test,vcs: call $finish when difftest fails * backend,RS: refactor with more submodules This commit rewrites the reservation station in a more configurable style. The new RS has not finished. - Support only integer instructions - Feedback from load/store instructions is not supported - Fast wakeup for multi-cycle instructions is not supported - Submodules are refined later * RS: use wakeup signals from arbiter.out * RS: support feedback and re-schedule when needed For load and store reservation stations, the instructions that left RS before may be replayed later. * test,vcs: check difftest_state and return on nemu trap instructions * backend,RS: support floating-point operands and delayed regfile read for store RS This commit adds support for floating-point instructions in reservation stations. Beside, currently fp data for store operands come a cycle later than int data. This feature is also supported. Currently the RS should be ready for any circumstances. * rs,status: don't trigger assertions when !status.valid * test,vcs: add +workload option to specify the ram init file * backend,rs: don't enqueue when redirect.valid or flush.valid * backend,rs: support wait bit that instruction waits until store issues This commit adds support for wait bit, which is mainly used in load and store reservation stations to delay instruction issue until the corresponding store instruction issued. * backend,RS: optimize timing This commit optimizes BypassNetwork and PayloadArray timing. - duplicate bypass mask to avoid too many FO4 - use one-hot vec to get read data
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- 12 5月, 2021 2 次提交
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由 Lemover 提交于
* PTW: add ptw multi-processing graph * [WIP] PTW: try to add miss queue, failed for complexity and not very useful * [WIP] PTW: rewrite ptw for multi req support * PTW: remove some assert, fix level init bug * PTW: itlb has highter priority than dtlb * PTW: fix bug that mix cache's resp logic * PTW: fix stupid bug that mix .U and .W * PTW: replay will not be blocked if fsm empty * PTW: miss queue req may return miss queue In the before design, only miss queue req can go into fsm, and would not be blocked. Now, to simplify design, miss queue req are just the same with new req, may blocked, going to fsm or miss queue. * PTW: fix ptw filter iss valid bug * PTW.fsm: fix bug that should not mem.req when sfenceLatch * PTW: fix ptw sfenceLatch's bug * PTW: add some perf counters * PTW: fix bug in filter enq ptr logic * PTW: fix bug of sfence in ptw * test: add current branch to ci-test, tmp * PTW: fix bug of cache's hit logic and fsm's pf * PTW: fix bug of filter's enq and block* signal * PTW: fix bug of filter's pteResp filter * PTW: add some assert of filter's counter * PTW: fix bug of filter's enq logic * PTW: set PTWMSHRSIZE 16 * PTW: fix naive perf counter's bug * PTW: set PTWMSHRSIZE 8 * PTW: set PTWMSHRSIZE 32 * Revert "PTW: set PTWMSHRSIZE 32" This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef. * Revert "test: add current branch to ci-test, tmp" This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.
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由 William Wang 提交于
* Configs: add MinimalFPGAConfig * TODO: change cache parameters * Chore: add parameter print * README: add simulation usage Currently, XiangShan does not support NOOP FPGA. FPGA related instructions are removed * Configs: limit frontend width in MinimalConfig * MinimalConfig: limit L1/L2 cache size * MinimalConfig: limit ptw size, disable L2 * MinimalConfig: limit L3 size * Sbuffer: force trigger write if sbuffer fulls
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- 11 5月, 2021 1 次提交
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由 William Wang 提交于
* LoadQueue: send stFtqIdx via rollback request * It will make it possible for setore set to update its SSIT * StoreSet: setup store set update req * StoreSet: add store set identifier table (SSIT) * StoreSet: add last fetched store table (LFST) * StoreSet: put SSIT into decode stage * StoreSet: put LFST into dispatch1 * Future work: optimize timing * RS: store rs now supports delayed issue * StoreSet: add perf counter * StoreSet: fix SSIT update logic * StoreSet: delay LFST update input for 1 cycle * StoreSet: fix LFST update logic * StoreSet: fix LFST raddr width * StoreSet: do not force store in ss issue in order Classic store set requires store in the same store set issue in seq. However, in current micro-architecture, such restrict will lead to severe perf lost. We choose to disable it until we find another way to fix it. * StoreSet: support ooo store in the same store set * StoreSet: fix store set merge logic * StoreSet: check earlier store when read LFST * If store-load pair is in the same dispatch bundle, loadWaitBit should also be set for load * StoreSet: increase default SSIT flush period * StoreSet: fix LFST read logic * Fix commit c0e541d1 * StoreSet: add StoreSetEnable parameter * RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * Parameters: disable store set by default * WaitTable: wait table will not cause store delay * WaitTable: recover default reset period to 2^17 * Fix dev-stad merge conflict * StoreSet: enable storeset * RS: disable store rs delay logic CI perf shows that current delay logic will cause perf loss. Disable unnecessary delay logic will help. To be more specific, `io.readyVec` caused the problem. It will be updated in future commits. * RS: opt select logic with load delay (ldWait) * StoreSet: disable 2-bit lwt Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 09 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt). Should be easier for RS.
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- 06 5月, 2021 1 次提交
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由 Lemover 提交于
* [WIP] Backend: add mul to fast wake-up * Backend: handle mul wb priority and fix wrong delay * RS: devide fastwakeup and nonBlocked(they were binded)
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- 05 5月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 04 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit fixes the bug when redirect.valid and the last valid instruction is in the last slot. Previously the tailPtr becomes size.U when there're no instructions before headPtr. It works fine when DispatchQueueSize is power2.
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- 01 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit uses Vec for lsrc, psrc, srcState and srcType in MicroOp bundle. This makes uop easier to access.
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- 30 4月, 2021 2 次提交
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由 Yinan Xu 提交于
In this commit, we add support for using DPI-C calls to replace DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to be ignored or bypassed. Configurations are controlled by useFakeDCache, useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache. However, some configurations may not work correctly.
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由 William Wang 提交于
* RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * StoreQueue: add sbuffer enq condition assertion Store data op (std) may still be invalid after store addr op's (sta) commitment, so datavalid needs to be checked before commiting store data to sbuffer Note that at current commit a non-completed std op for a commited store may exist. We should make sure that uop will not be cancelled by a latter branch mispredict. More work to be done! * Roq: add std/sta split writeback logic Now store will commit only if both sta & std have been writebacked Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 29 4月, 2021 2 次提交
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由 wakafa 提交于
* difftest: revise coreid assignment * nemuproxy: compatible for smp difftest * difftest: fix goldenMem initialization problem * difftest: goldenMem update works * difftest: api compatible for modified nemu * difftest: support load check for smp difftest * verification is required later * misc: remove unused xstrap wiring * Remove unused code * difftest: add latch for difftest-loadevent * misc: update inclusivecache * difftest: reset resp for sbuffer & atomic-unit to avoid duplicate update of goldenMem * difftest: dump coreid when difftest failed * difftest: dump corresponding memory of another core when smp difftest failed * Only works for dual-core * difftest: fix interrupt handler * difftest: cleanup code * roq: remove legacy signal for difftest
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由 Lemover 提交于
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- 26 4月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 22 4月, 2021 1 次提交
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由 Yinan Xu 提交于
In this commit, we add performance counters for dispatch and issue stages to track the number of instructions dispatched and issued. Active regfile read ports are counted as ready instruction source registers.
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- 21 4月, 2021 1 次提交
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由 Lemover 提交于
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 16 4月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 05 4月, 2021 1 次提交
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由 ljw 提交于
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- 03 4月, 2021 1 次提交
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由 LinJiawei 提交于
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- 02 4月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 31 3月, 2021 2 次提交
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters * csr: bug fixing for perf-cnt wiring
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters
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- 30 3月, 2021 1 次提交
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由 ljw 提交于
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- 26 3月, 2021 1 次提交
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由 Lemover 提交于
* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue * RS: fix bug that ctrl's flushed enqueue conflicts with next enqueue
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- 25 3月, 2021 2 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers * Ftq: bypass 'commit state' to fix dequeue bug * perf: uptimize perf-cnt in ctrlblock & ftq * perf: fix compilation problem in ftq * perf: remove duplicate perf-cnt * perf: calcu extra walk cycle exceeding frontend flush bubble * Revert "perf: calcu extra walk cycle exceeding frontend flush bubble" This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70. * perf: add perf-cnt for ifu * perf: add perf-cnt for rs * RS: optimize numExist signal * RS: fix some typo * perf: add QueuePerf util to monitor usage info of queues * perf: remove some duprecate perfcnt
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- 24 3月, 2021 2 次提交
- 22 3月, 2021 2 次提交
- 19 3月, 2021 1 次提交
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由 LinJiawei 提交于
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- 14 3月, 2021 1 次提交
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由 Steve Gou 提交于
* add perf counters for btb and ubtb * update btb only on not hit or jalr mispredicts to reduce write stalls
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- 13 3月, 2021 1 次提交
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由 Lemover 提交于
just record the tlb result(access and miss) of first issue by add signal isFirstIssue (isFirstIssue = cntCountQueue(i) === 0.U)
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- 12 3月, 2021 2 次提交
- 11 3月, 2021 2 次提交
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由 Yinan Xu 提交于
In this commit, we add support for a simpler version of move elimination. The original instruction sequences are: move r1, r0 add r2, r1, r3 The optimized sequnces are: move pr1, pr0 add pr2, pr0, pr3 # instead of add pr2, pr1, pr3 In this way, add can be issued once r0 is ready and move seems to be eliminated.
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由 Yinan Xu 提交于
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