- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 12 5月, 2021 1 次提交
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由 William Wang 提交于
* Configs: add MinimalFPGAConfig * TODO: change cache parameters * Chore: add parameter print * README: add simulation usage Currently, XiangShan does not support NOOP FPGA. FPGA related instructions are removed * Configs: limit frontend width in MinimalConfig * MinimalConfig: limit L1/L2 cache size * MinimalConfig: limit ptw size, disable L2 * MinimalConfig: limit L3 size * Sbuffer: force trigger write if sbuffer fulls
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- 11 5月, 2021 1 次提交
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由 William Wang 提交于
* LoadQueue: send stFtqIdx via rollback request * It will make it possible for setore set to update its SSIT * StoreSet: setup store set update req * StoreSet: add store set identifier table (SSIT) * StoreSet: add last fetched store table (LFST) * StoreSet: put SSIT into decode stage * StoreSet: put LFST into dispatch1 * Future work: optimize timing * RS: store rs now supports delayed issue * StoreSet: add perf counter * StoreSet: fix SSIT update logic * StoreSet: delay LFST update input for 1 cycle * StoreSet: fix LFST update logic * StoreSet: fix LFST raddr width * StoreSet: do not force store in ss issue in order Classic store set requires store in the same store set issue in seq. However, in current micro-architecture, such restrict will lead to severe perf lost. We choose to disable it until we find another way to fix it. * StoreSet: support ooo store in the same store set * StoreSet: fix store set merge logic * StoreSet: check earlier store when read LFST * If store-load pair is in the same dispatch bundle, loadWaitBit should also be set for load * StoreSet: increase default SSIT flush period * StoreSet: fix LFST read logic * Fix commit c0e541d1 * StoreSet: add StoreSetEnable parameter * RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * Parameters: disable store set by default * WaitTable: wait table will not cause store delay * WaitTable: recover default reset period to 2^17 * Fix dev-stad merge conflict * StoreSet: enable storeset * RS: disable store rs delay logic CI perf shows that current delay logic will cause perf loss. Disable unnecessary delay logic will help. To be more specific, `io.readyVec` caused the problem. It will be updated in future commits. * RS: opt select logic with load delay (ldWait) * StoreSet: disable 2-bit lwt Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 30 4月, 2021 1 次提交
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由 William Wang 提交于
* RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * StoreQueue: add sbuffer enq condition assertion Store data op (std) may still be invalid after store addr op's (sta) commitment, so datavalid needs to be checked before commiting store data to sbuffer Note that at current commit a non-completed std op for a commited store may exist. We should make sure that uop will not be cancelled by a latter branch mispredict. More work to be done! * Roq: add std/sta split writeback logic Now store will commit only if both sta & std have been writebacked Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 05 4月, 2021 1 次提交
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由 ljw 提交于
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- 31 3月, 2021 1 次提交
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters
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- 25 3月, 2021 2 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers * Ftq: bypass 'commit state' to fix dequeue bug * perf: uptimize perf-cnt in ctrlblock & ftq * perf: fix compilation problem in ftq * perf: remove duplicate perf-cnt * perf: calcu extra walk cycle exceeding frontend flush bubble * Revert "perf: calcu extra walk cycle exceeding frontend flush bubble" This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70. * perf: add perf-cnt for ifu * perf: add perf-cnt for rs * RS: optimize numExist signal * RS: fix some typo * perf: add QueuePerf util to monitor usage info of queues * perf: remove some duprecate perfcnt
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- 08 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 28 2月, 2021 1 次提交
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers
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- 26 2月, 2021 2 次提交
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由 ljw 提交于
* Backend: fix some bugs related to exu write * Roq: revert to perv verision * Fix fp write back bugs
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由 William Wang 提交于
* LSQ: use async vaddrModule * StoreQueue: opt mmio writeback valid timing * LSQ: opt vaddr read ptr gen timing * chore: remove unnecessary script
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- 23 2月, 2021 2 次提交
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由 William Wang 提交于
* Alternative plan: use async vaddr module
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由 LinJiawei 提交于
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- 21 2月, 2021 1 次提交
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由 William Wang 提交于
Former rollback will now cancel later rollback correctly
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- 20 2月, 2021 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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- 05 2月, 2021 1 次提交
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由 William Wang 提交于
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- 02 2月, 2021 3 次提交
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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- 31 1月, 2021 6 次提交
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由 LinJiawei 提交于
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由 William Wang 提交于
* stage 0 (store s1): paddr match & state check * stage 1 (store s2): seq check 1 * stage 2 (store s3): seq check 2, cancel check, fire final req
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由 William Wang 提交于
* It should have no side effect
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
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由 William Wang 提交于
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- 29 1月, 2021 1 次提交
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由 William Wang 提交于
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- 28 1月, 2021 1 次提交
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由 William Wang 提交于
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- 27 1月, 2021 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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- 26 1月, 2021 2 次提交
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由 William Wang 提交于
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由 Yinan Xu 提交于
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- 25 1月, 2021 5 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 Yinan Xu 提交于
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- 24 1月, 2021 1 次提交
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由 William Wang 提交于
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