- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 25 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds a new AXI4 device to generate external interrupts. Previously none of the simulated external devices trigger interrupts. To test external interrupts, we add this device.
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- 09 5月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt). Should be easier for RS.
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- 07 5月, 2021 2 次提交
- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 30 3月, 2021 1 次提交
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由 ljw 提交于
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- 18 3月, 2021 1 次提交
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由 LinJiawei 提交于
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- 07 3月, 2021 1 次提交
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由 Yinan Xu 提交于
* MySoc: verilog top * MySoc: connect mmio * MySoc: fix some bugs * wip * TopMain: remove to top * WIP: add dma port * Update XSTop for FPGA/ASIC platform * Top: add rocket-chip source * Append SRAM to generated verilog Co-authored-by: NLinJiawei <linjiav@outlook.com>
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- 04 3月, 2021 1 次提交
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由 ljw 提交于
* NewSbuffer: allow multi-inflight dcache request to improve performance * NewSbuffer: fix bugs in replace && add more debug print * SbufferTest: update sbuffer test
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- 25 2月, 2021 1 次提交
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由 wangkaifan 提交于
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- 09 2月, 2021 1 次提交
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由 wangkaifan 提交于
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- 07 2月, 2021 1 次提交
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由 jinyue110 提交于
It used to be changed only when hit
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- 04 2月, 2021 2 次提交
- 02 2月, 2021 1 次提交
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由 LinJiawei 提交于
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- 01 2月, 2021 2 次提交
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由 jinyue110 提交于
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由 wangkaifan 提交于
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- 29 1月, 2021 3 次提交
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由 BigWhiteDog 提交于
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由 jinyue110 提交于
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由 jinyue110 提交于
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- 28 1月, 2021 3 次提交
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由 ZhangZifei 提交于
1. divide into three block 2. change io port: broadcastUop -> fastUopsIn selectUop -> fastUopOut extraPorts -> slowPorts etc. the cross sub block io is not wrapped, to it later
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由 wangkaifan 提交于
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由 wangkaifan 提交于
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- 27 1月, 2021 3 次提交
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由 wangkaifan 提交于
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由 wangkaifan 提交于
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由 Allen 提交于
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- 25 1月, 2021 4 次提交
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由 Allen 提交于
and Writeback req.
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由 BigWhiteDog 提交于
those written by store in flight
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由 wangkaifan 提交于
* should be compatible with single core difftest framework
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由 ZhangZifei 提交于
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- 24 1月, 2021 4 次提交
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由 BigWhiteDog 提交于
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由 BigWhiteDog 提交于
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由 zoujr 提交于
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由 Allen 提交于
Now, it can compile.
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- 22 1月, 2021 3 次提交
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由 Lingrui98 提交于
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由 BigWhiteDog 提交于
it may use any source associated with sender
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由 BigWhiteDog 提交于
when stores in flight
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- 21 1月, 2021 2 次提交
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由 BigWhiteDog 提交于
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由 BigWhiteDog 提交于
but it can't run with store test
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