Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* LoadQueueReplay: fix worst case, all oldest instructions are allocated to the same bank, 
and the number of instructions is greater than the number of stages in load unit.
* Remove bank conflict block
* Increase priority for data replay

The deadlock scenario is as follows:

The LoadQueueReplay entry will not be released immediately after the instruction
is replayed from LoadQueueReplay. For example, after instruction a is replayed from
LoadQueueReplay, entry 1 is still valid. If instruction a still needs to be replayed,
Entry 1 will be updated again, otherwise entry 1 can be released.

If only the time of the first enqueue is used to select replay instructions (age matrix),
when there are too many instructions (in LoadQueueReplay) to be replay, some
instructions may not be selected.

Using the pointer ldWbPtr of the oldest instruction, when the saved lqIdx of the
instruction is equal to ldWbPtr and can be replayed, LoadQueueReplay will give
priority to the instruction instead of using the selection result of the age matrix.
To select older instructions, LoadQueueReplay will calculate pointers such as
ldWbPtr, ldWbPtr+1, ldWbPtr+2, ldWbPtr+3..., and if the lqIdx of the instruction
is in these results, it will be selected first.

When the pointer is compared, there will be an n-bit long mask, and LoadQueueReplay
will be from 0 to n-1. When i th bit is valid, select i th instruction.

The stride of the pointer comparison is larger than the number of pipeline stages
of the load unit, and the selected instruction still needs to be replayed after the
first replay (for example, the data is not ready). Worse, in the bit of the mask
generated by pointer comparison, the instructions (lqIdx is ldWbPtr+1, ldWbPtr+2, ...)
after the oldest instruction (lqIdx is equal to ldWbPtr) are in the lower bit and the
oldest instruction is in the higher bit. It cannot select the oldest instruction.

This commit provides MDP adaptation for #2077 

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict when compare SSID

* fix store data wakeup logic
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* icache: Acquire -> Get to L2

* gitmodules: add coupledL2 as submodule

* cpl2: merge coupledL2 into master

* Changes includes:
*   coupledL2 integration
*   modify user&echo fields in i$/d$/ptw
*   set d$ never always-releasedata
*   remove hw perfcnt connection for L2

* bump utility

* icache: remove unused releaseUnit

* config: minimalconfig includes l2

* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem

* bump Utility

* bump coupledL2: fix bugs in dual-core

* bump coupledL2

* icache: set icache as non-coherent node

* bump coupledL2: fix dirty problem in L2 ProbeAckData

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Co-authored-by: Nguohongyu <20373696@buaa.edu.cn>
Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn>

* script: enable chiseldb by default on running emu by xiangshan.py

* script: move db file to wave_home if emu failed

BPU: online history checker

* fix uncache buffer writeback fsm

* fix uncache buffer writeback fsm

* fix uncache buffer writeback control

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay queue
* load rar queue
* load raw queue
* uncache buffer

It will provide larger ooo load window.

NOTE: IPC loss in this commit is caused by MDP problems, for previous MDP
does not fit new LSU architecture. 
MDP update is not included in this commit, IPC loss will be fixed by MDP update later.

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* When replacing happens in loadpipe and mainpipe and there are invalid ways, use invalid ways first instead of way calulated by replacer.
* Update replacement on 2nd miss only when this request is firstly issued.

* dcache: prefer using invalid way when replace

When replacing happens in loadpipe and mainpipe and there are invalid
ways, use these ways first instead of way calulated by replacer

* dcache: fix replacement

If a request is merged by dcache, update replacement only when this
request is firstly issued

* loadpipe: fix compile

* ldu: fix s1_repl_way_en

ITTAGE: fix missing base cond

ICache FDIP migrate

* add a switch for the WPU in dataArray

* dcache: fix cacheop dup logic

* dcache: fix wpu parameter

* constant: fix dead loop

* util: fix constant dynamic switch

* util: fix constant

* bpu: add plru replacer in wrbypass

also remove tag in Tage and ITTage wrbypass

* tage: fix idx width

* bpu: wrbypass cleanup and add comments about shared replacer

* bpu: fix code style

* ICache:send Get instead of Acquire to L2

* ICache:add vaild_array in metaArray

* [WIP]ICache:annotate invalid coherence modules for icache

* ICache:delete invalid coherence modules for icache

* ICache : add fencei logic

* ICache : fix check multi-hit logic

fix ITTAGE update condition

* constant: fix init

* utility: merge xs/master version

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Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>