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risc_axi_v5_top_axi_uartlite_0_0.vds 31.0 KB
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#-----------------------------------------------------------
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Sun Sep 12 15:50:48 2021
# Process ID: 53664
# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1
# Command line: vivado.exe -log risc_axi_v5_top_axi_uartlite_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source risc_axi_v5_top_axi_uartlite_0_0.tcl
# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1/risc_axi_v5_top_axi_uartlite_0_0.vds
# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1\vivado.jou
#-----------------------------------------------------------
source risc_axi_v5_top_axi_uartlite_0_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myipmster_1.0'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/ip_repo/myip_1.0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.1/data/ip'.
Command: synth_design -top risc_axi_v5_top_axi_uartlite_0_0 -part xc7z020clg400-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 51272
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1135.660 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'risc_axi_v5_top_axi_uartlite_0_0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/synth/risc_axi_v5_top_axi_uartlite_0_0.vhd:86]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 50000000 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_BAUDRATE bound to: 115200 - type: integer 
	Parameter C_DATA_BITS bound to: 8 - type: integer 
	Parameter C_USE_PARITY bound to: 0 - type: integer 
	Parameter C_ODD_PARITY bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'axi_uartlite' declared at 'd:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2128' bound to instance 'U0' of component 'axi_uartlite' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/synth/risc_axi_v5_top_axi_uartlite_0_0.vhd:162]
INFO: [Synth 8-638] synthesizing module 'axi_uartlite' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2190]
INFO: [Synth 8-638] synthesizing module 'uartlite_core' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1650]
INFO: [Synth 8-638] synthesizing module 'baudrate' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1453]
INFO: [Synth 8-256] done synthesizing module 'baudrate' (1#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1453]
INFO: [Synth 8-638] synthesizing module 'uartlite_rx' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:927]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'srl_fifo_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (3#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (4#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (5#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f' (6#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
INFO: [Synth 8-256] done synthesizing module 'uartlite_rx' (7#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:927]
INFO: [Synth 8-638] synthesizing module 'uartlite_tx' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
INFO: [Synth 8-256] done synthesizing module 'uartlite_tx' (8#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
INFO: [Synth 8-256] done synthesizing module 'uartlite_core' (9#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1650]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-638] synthesizing module 'address_decoder' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-638] synthesizing module 'pselect_f' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (10#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (11#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (12#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (13#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite' (14#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ipshared/8c9b/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2190]
INFO: [Synth 8-256] done synthesizing module 'risc_axi_v5_top_axi_uartlite_0_0' (15#1) [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/synth/risc_axi_v5_top_axi_uartlite_0_0.vhd:86]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1135.660 ; gain = 0.000
---------------------------------------------------------------------------------
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Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1135.660 ; gain = 0.000
---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1135.660 ; gain = 0.000
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1135.660 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_ooc.xdc] for cell 'U0'
Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_board.xdc] for cell 'U0'
Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0_board.xdc] for cell 'U0'
Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0.xdc] for cell 'U0'
Finished Parsing XDC File [d:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/ip/risc_axi_v5_top_axi_uartlite_0_0/risc_axi_v5_top_axi_uartlite_0_0.xdc] for cell 'U0'
Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1181.832 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 6 instances were transformed.
  FDR => FDRE: 6 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1185.801 ; gain = 3.969
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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Loading part: xc7z020clg400-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file  D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sm_idle |                             0010 |                               00
                 sm_read |                             1000 |                               01
                sm_write |                             0100 |                               10
                 sm_resp |                             0001 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
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Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input    5 Bit       Adders := 1     
	   3 Input    5 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	               16 Bit    Registers := 2     
	                5 Bit    Registers := 3     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 46    
+---Muxes : 
	   2 Input    8 Bit        Muxes := 2     
	   2 Input    5 Bit        Muxes := 1     
	   4 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 6     
	   2 Input    3 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 2     
	   2 Input    1 Bit        Muxes := 113   
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
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Start IO Insertion
---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Static Shift Register Report:
+-------------+--------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name  | RTL Name                                         | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | 
+-------------+--------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_RX_I/data_shift_reg[15] | 16     | 1     | YES          | NO                 | YES               | 1      | 0       | 
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_TX_I/data_shift_reg[15] | 15     | 1     | YES          | NO                 | YES               | 1      | 0       | 
+-------------+--------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+


Dynamic Shift Register Report:
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name                  | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl        | INFERRED_GEN.data_reg[15] | 8      | 8          | 8      | 0       | 0      | 0      | 0      | 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-------+------+
|      |Cell   |Count |
+------+-------+------+
|1     |LUT1   |     1|
|2     |LUT2   |    14|
|3     |LUT3   |     9|
|4     |LUT4   |    26|
|5     |LUT5   |    25|
|6     |LUT6   |    26|
|7     |MUXF7  |     1|
|8     |SRL16E |    18|
|9     |FDR    |     4|
|10    |FDRE   |    87|
|11    |FDSE   |    18|
+------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1185.801 ; gain = 0.000
Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1185.801 ; gain = 50.141
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1185.801 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1185.801 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 4 instances were transformed.
  FDR => FDRE: 4 instances

Synth Design complete, checksum: d896fda9
INFO: [Common 17-83] Releasing license: Synthesis
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1185.801 ; gain = 50.141
INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1/risc_axi_v5_top_axi_uartlite_0_0.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP risc_axi_v5_top_axi_uartlite_0_0, cache-ID = 67c0db73b11fc599
INFO: [Coretcl 2-1174] Renamed 19 cell refs.
INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.runs/risc_axi_v5_top_axi_uartlite_0_0_synth_1/risc_axi_v5_top_axi_uartlite_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file risc_axi_v5_top_axi_uartlite_0_0_utilization_synth.rpt -pb risc_axi_v5_top_axi_uartlite_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Sep 12 15:51:21 2021...