risc_axi_v5_top_wrapper_drc_routed.rpt

Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date         : Mon Sep 13 12:42:10 2021
| Host         : DESKTOP-I91JIJO running 64-bit major release  (build 9200)
| Command      : report_drc -file risc_axi_v5_top_wrapper_drc_routed.rpt -pb risc_axi_v5_top_wrapper_drc_routed.pb -rpx risc_axi_v5_top_wrapper_drc_routed.rpx
| Design       : risc_axi_v5_top_wrapper
| Device       : xc7z020clg400-2
| Speed File   : -2
| Design State : Fully Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 4
+-----------+----------+-------------------------+------------+
| Rule      | Severity | Description             | Violations |
+-----------+----------+-------------------------+------------+
| PDCN-1569 | Warning  | LUT equation term check | 2          |
| RTSTAT-10 | Warning  | No routable loads       | 1          |
| ZPS7-1    | Warning  | PS7 block required      | 1          |
+-----------+----------+-------------------------+------------+

2. REPORT DETAILS
-----------------
PDCN-1569#1 Warning
LUT equation term check  
Used physical LUT pin 'A3' of cell risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_i_1 (pin risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_i_1/I1) is not included in the LUT equation: 'O6=(A5)+((~A5)*(~A1)*A4)'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Related violations: <none>

PDCN-1569#2 Warning
LUT equation term check  
Used physical LUT pin 'A5' of cell risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_i_1 (pin risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_i_1/I1) is not included in the LUT equation: 'O6=(A6)+((~A6)*(~A4)*A3)'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Related violations: <none>

RTSTAT-10#1 Warning
No routable loads  
10 net(s) have no routable loads. The problem bus(es) and/or net(s) are risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/user_valid,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_recv_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/user_valid,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i,
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb
risc_axi_v5_top_i/hdl4se_uart_ctrl_axi_0/inst/uart_send_buf/fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i.
Related violations: <none>

ZPS7-1#1 Warning
PS7 block required  
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>