Skip to content

H
hdl4se

饶先宏 / hdl4se

通知 12
Star 1
Fork 0
H
hdl4se

前往新版Gitcode，体验更适合开发者的 AI 搜索 >>

提交 1bb837b4 编写于 作者: 饶先宏's avatar 饶先宏
浏览文件
操作

202109090547

上级 723963b8
隐藏空白更改
内联 并排
Showing with 7 addition and 7 deletion
examples/hdl4se_riscv/verilog/riscv_core_v4.v
浏览文件 @ 1bb837b4
......@@ -361,7 +361,7 @@ module riscv_core(
end else if (state == `RISCVSTATE_EXEC_INST) begin
write <= 0;
if (opcode == 5'h08) begin
writeaddr <= {newwriteaddr[31:2], 2'b00};
writemask <= 4'h0;
writedata <= rs2;
......@@ -501,10 +501,10 @@ module riscv_core(
state <= `RISCVSTATE_WAIT_LD2;
end
else begin
state <= `RISCVSTATE_READ_INST;
state <= `RISCVSTATE_READ_REGS;
end
end
`RISCVSTATE_WAIT_LD2: state <= `RISCVSTATE_READ_INST;
`RISCVSTATE_WAIT_LD2: state <= `RISCVSTATE_READ_REGS;
`RISCVSTATE_WAIT_ST: begin
state <= `RISCVSTATE_READ_INST;
if (opcode == 5'h08) begin
......@@ -520,10 +520,10 @@ module riscv_core(
`RISCVSTATE_WAIT_MUL: begin
`ifdef USEMUL32
if (muldone)
state <= `RISCVSTATE_READ_INST;
state <= `RISCVSTATE_READ_REGS;
`else
if (divclk == 0)
state <= `RISCVSTATE_READ_INST;
state <= `RISCVSTATE_READ_REGS;
else
divclk <= divclk - 1;
`endif
......@@ -532,10 +532,10 @@ module riscv_core(
`RISCVSTATE_WAIT_DIV: begin
`ifdef USEDIV32
if (divdone)
state <= `RISCVSTATE_READ_INST;
state <= `RISCVSTATE_READ_REGS;
`else
if (divclk == 0)
state <= `RISCVSTATE_READ_INST;
state <= `RISCVSTATE_READ_REGS;
else
divclk <= divclk - 1;
`endif
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或