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提交 259f8d21 编写于 作者: 饶先宏's avatar 饶先宏
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202109150639

上级 c6d66fde
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Showing with 135 addition and 107 deletion
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v
浏览文件 @ 259f8d21
......@@ -359,6 +359,18 @@ module riscv_core_v5(
if (opcode == 5'h00)
readreg <= rd;
reg [31:0] lastWriteAddr;
reg [31:0] lastWriteData;
reg [3:0] lastWriteMask;
reg lastWrite;
always @(posedge wClk) begin
lastWrite <= write;
lastWriteAddr <= writeaddr;
lastWriteData <= writedata;
lastWriteMask <= writemask;
end
wire [31:0] newwriteaddr = rs1 + imm;
//DEFINE_FUNC(riscv_core_gen_write, "nwReset, state, pc, instr, rs1, regrddata, imm") {
always @(nwReset or state or opcode or newwriteaddr or rs2 or func3 or lastaddr or lastv) begin
......@@ -366,117 +378,128 @@ module riscv_core_v5(
writeaddr = 0;
writemask = 0;
writedata = 0;
if (!nwReset) begin
write = 0;
end else if (state == `RISCVSTATE_EXEC_INST) begin
write = 0;
if (opcode == 5'h08) begin
writeaddr = {newwriteaddr[31:2], 2'b00};
writemask = 4'h0;
writedata = rs2;
write = 1'b1;
case (func3)
0:/*sb*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'he;
writedata = rs2;
end
1: begin
writemask = 4'hd;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'hb;
writedata = {rs2[15:0], 16'h0};
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
end
endcase
end
1:/*sh*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'hc;
writedata = rs2;
end
1: begin
writemask = 4'h9;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'h3;
writedata = {rs2[15:0], 16'h0};
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
end
endcase
end
2:/*sw*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'h0;
writedata = rs2;
end
1: begin
writemask = 4'h1;
writedata = {rs2[23:0], 8'h0};
if (state == `RISCVSTATE_EXEC_INST) begin
write = 0;
if (opcode == 5'h08) begin
writeaddr = {newwriteaddr[31:2], 2'b00};
writemask = 4'h0;
writedata = rs2;
write = 1'b1;
case (func3)
0:/*sb*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'he;
writedata = rs2;
end
1: begin
writemask = 4'hd;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'hb;
writedata = {rs2[15:0], 16'h0};
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
end
endcase
end
2: begin
writemask = 4'h3;
writedata = {rs2[15:0], 16'h0};
1:/*sh*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'hc;
writedata = rs2;
end
1: begin
writemask = 4'h9;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'h3;
writedata = {rs2[15:0], 16'h0};
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
end
endcase
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
2:/*sw*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'h0;
writedata = rs2;
end
1: begin
writemask = 4'h1;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'h3;
writedata = {rs2[15:0], 16'h0};
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
end
endcase
end
endcase
end
endcase
end
end else if (state == `RISCVSTATE_WAIT_ST) begin
write = 0;
writeaddr = {lastaddr[31:2], 2'b0} + 4;
if (opcode == 5'h08) begin
case (func3)
1:/*sh*/ begin
case (lastaddr[1:0])
3: begin
writemask = 4'he;
writedata = {24'b0, lastv[31:24]};
write = 1;
end else if (state == `RISCVSTATE_WAIT_ST) begin
if (wWriteReady) begin
write = 0;
writeaddr = {lastaddr[31:2], 2'b0} + 4;
if (opcode == 5'h08) begin
case (func3)
1:/*sh*/ begin
case (lastaddr[1:0])
3: begin
writemask = 4'he;
writedata = {24'b0, lastv[31:24]};
write = 1;
end
endcase
end
2:/*sw*/ begin
case (lastaddr[1:0])
1: begin
writemask = 4'he;
writedata = {24'b0, lastv[31:24]};
write = 1;
end
2: begin
writemask = 4'hc;
writedata = {16'b0, lastv[31:16]};
write = 1;
end
3: begin
writemask = 4'h8;
writedata = {8'b0, lastv[31:8]};
write = 1;
end
endcase
end
endcase
end
endcase
end else begin
write = lastWrite;
writemask = lastWriteMask;
writedata = lastWriteData;
writeaddr = lastWriteAddr;
end
2:/*sw*/ begin
case (lastaddr[1:0])
1: begin
writemask = 4'he;
writedata = {24'b0, lastv[31:24]};
write = 1;
end
2: begin
writemask = 4'hc;
writedata = {16'b0, lastv[31:16]};
write = 1;
end
3: begin
writemask = 4'h8;
writedata = {8'b0, lastv[31:8]};
write = 1;
end
endcase
end else if (state == `RISCVSTATE_WAIT_ST2) begin
if (~wWriteReady) begin
write = lastWrite;
writemask = lastWriteMask;
writedata = lastWriteData;
writeaddr = lastWriteAddr;
end
endcase
end else begin
write = 0;
end
end else begin
write = 0;
end
end
//DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") {
......@@ -524,7 +547,7 @@ module riscv_core_v5(
if (wReadReady) begin
state <= `RISCVSTATE_READ_REGS;
end
`RISCVSTATE_WAIT_ST: begin
`RISCVSTATE_WAIT_ST: if (wWriteReady) begin
state <= `RISCVSTATE_READ_REGS;
if (opcode == 5'h08) begin
if (func3 == 1 && (lastaddr & 3) == 3) begin /* sh */
......@@ -535,7 +558,9 @@ module riscv_core_v5(
end
end
end
`RISCVSTATE_WAIT_ST2: state <= `RISCVSTATE_READ_REGS;
`RISCVSTATE_WAIT_ST2:
if (wWriteReady )
state <= `RISCVSTATE_READ_REGS;
`RISCVSTATE_WAIT_MUL: begin
`ifdef USEMUL32
if (muldone)
......@@ -1084,7 +1109,10 @@ module riscv_core_v5(
wRead = lastRead;
bReadAddr = lastReadAddr;
end
`RISCVSTATE_WAIT_ST2,
`RISCVSTATE_WAIT_ST2: if (wWriteReady) begin
wRead = 1;
bReadAddr = pc;
end
`RISCVSTATE_READ_INST: begin
wRead = 1;
bReadAddr = pc;
......@@ -1125,8 +1153,8 @@ module riscv_core_v5(
bReadAddr = lastReadAddr;
end
end
`RISCVSTATE_WAIT_ST: begin
if (opcode == 5'h08) begin
`RISCVSTATE_WAIT_ST: if (wWriteReady) begin
if (opcode == 5'h08) begin
if (func3 == 1 && lastaddr[1:0] == 3) begin /* sh */
end
......
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