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提交 2f518ba1 编写于 作者: 饶先宏's avatar 饶先宏
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202106272118 BUG!BUG!BUG!加上逻辑上的复杂，导致进度条又开始沉重了。

上级 76460187
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内联 并排
Showing with 1529 addition and 62 deletion
bignumber/src/bignumber.c
浏览文件 @ 2f518ba1
......@@ -49,6 +49,8 @@
#define NOTIMPL printf("bignumber.c %d, %s is not implemented now\n", __LINE__, __FUNCTION__)
#define HDL4SEDEBUG 0
#define CELL_WIDTH 32
#define CELL_MASK 0xffffffff
......@@ -230,7 +232,7 @@ static int bigint_bn_SetUnsigned(HOBJECT object, int isunsigned)
{
sBigInteger* pobj;
pobj = (sBigInteger*)objectThis(object);
pobj->isunsigned = isunsigned;
pobj->isunsigned = isunsigned?1:0;
bigint_bn_SetWidth(object, pobj->width);
return 0;
}
......@@ -763,10 +765,20 @@ static int bigint_bn_CloneSubBits(HOBJECT object, HOBJECT src, int from, int wid
{
if (from < 0 || width <= 0)
return -1;
#if HDL4SEDEBUG
char buf[60];
bigint_bn_GetStr(src, 16, buf, 60);
#endif
bigint_bn_SetUnsigned(object, 1);
bigint_bn_SetWidth(object, width);
bigint_bn_SAR(object, src, from);
bigint_bn_SHR(object, src, from);
#if HDL4SEDEBUG
bigint_bn_GetStr(object, 16, buf, 60);
#endif
bigint_bn_SetWidth(object, width);
#if HDL4SEDEBUG
bigint_bn_GetStr(object, 16, buf, 60);
#endif
return 0;
}
......@@ -784,9 +796,16 @@ static int bigint_bn_Assign(HOBJECT object, HOBJECT src)
static int bigint_bn_AssignSubBits(HOBJECT object, HOBJECT src, int from, int width)
{
int objwidth;
#if HDL4SEDEBUG
char buf[60];
bigint_bn_GetStr(src, 16, buf, 60);
#endif
objwidth = bigint_bn_GetWidth(object);
bigint_bn_CloneSubBits(object, src, from, width);
bigint_bn_SetWidth(object, objwidth);
#if HDL4SEDEBUG
bigint_bn_GetStr(object, 16, buf, 60);
#endif
return 0;
}
......@@ -1757,8 +1776,11 @@ static int bigint_bn_SHR(HOBJECT object, HOBJECT src, int bits)
current |= next;
}
pobj->buf[ito++] = (unsigned int)(current & CELL_MASK);
while (ito < pobj->buflen)
pobj->buf[ito++] = 0;
current >>= CELL_WIDTH;
while (ito < pobj->buflen) {
pobj->buf[ito++] = current;
current >>= CELL_WIDTH;
}
return 0;
}
......
examples/terris/src/main.c
浏览文件 @ 2f518ba1
......@@ -34,6 +34,7 @@
#include "stdlib.h"
#include "stdio.h"
#include "string.h"
#include "time.h"
#include "object.h"
#include "bignumber.h"
#include "hdl4secell.h"
......@@ -75,6 +76,7 @@ int main(int argc, char* argv[])
int count, unitcount;
IHDL4SEUnit** sim_unit;
IHDL4SEWaveOutput** vcdfile;
srand((unsigned int)time(NULL));
A_u_t_o_registor_terrisctrl();
A_u_t_o_registor_terrisctrl1();
A_u_t_o_registor_terris_flushtodisp();
......@@ -97,20 +99,18 @@ int main(int argc, char* argv[])
objectCall2(vcdfile, AddSignal, "/top/terrisctrl", "bWriteData");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/bCtrlState", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/wCtrlStateComplete", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/bCtrlState", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/bram_ReadData", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/wCanSetCurrent", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/wCanSetCurrent_3", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/curblockline_mask_2", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/wCanSetCurrent_2", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/wCanSetCurrent", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/line", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/curblockline_mask", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/curblockline_mask_0", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/curblockline_mask_1", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/wCanSetCurrent_1", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/mask0", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/blocksetto/shift0", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/randnum", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/shapedata", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_initclock", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_nextblock", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/setshape", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/newshape", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_shapedata", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_nextblock", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/colorindex", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/colorindex_0", "out");
objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/newblock", "out");
objectCall1(vcdfile, SetTopModule, topmodule);
objectCall0(vcdfile, StartRecord);
#endif
......@@ -122,7 +122,7 @@ int main(int argc, char* argv[])
#endif
objectCall0(sim_unit, Setup);
clocks++;
if (clocks == 4)
if (clocks > 10 + (rand() % 50))
objectCall1(sim, SetReset, 1);
} while (running);
#if VCDOUTPUT
......
examples/terris/verilog/terris_ctrl.v
浏览文件 @ 2f518ba1
......@@ -31,9 +31,201 @@
*/
/* terris_ctrl.v */
module rand(input wClk,
output [15: 0] randnum
);
wire [31:0] wirein_num, wireout_num;
hdl4se_reg #(32) reg_rand(wClk, wirein_num, wireout_num);
assign randnum = wireout_num[15:0];
assign wirein_num = (wireout_num * 32'd214013) + 32'd2531011;
endmodule
module turnleft(input [63:0] inblock,
output[63:0] outblock
);
wire [3:0] b00 = inblock[3:0];
wire [3:0] b01 = inblock[7:4];
wire [3:0] b02 = inblock[11:8];
wire [3:0] b03 = inblock[15:12];
wire [3:0] b10 = inblock[19:16];
wire [3:0] b11 = inblock[23:20];
wire [3:0] b12 = inblock[27:24];
wire [3:0] b13 = inblock[31:28];
wire [3:0] b20 = inblock[35:32];
wire [3:0] b21 = inblock[39:36];
wire [3:0] b22 = inblock[43:40];
wire [3:0] b23 = inblock[47:44];
wire [3:0] b30 = inblock[51:48];
wire [3:0] b31 = inblock[55:52];
wire [3:0] b32 = inblock[59:56];
wire [3:0] b33 = inblock[63:60];
wire [15:0] line0;
wire [15:0] line1;
wire [15:0] line2;
wire [15:0] line3;
hdl4se_bind4 #(4, 4, 4, 4) bindline0(b03, b13, b23, b33, line0);
hdl4se_bind4 #(4, 4, 4, 4) bindline1(b02, b12, b22, b32, line1);
hdl4se_bind4 #(4, 4, 4, 4) bindline2(b01, b11, b21, b31, line2);
hdl4se_bind4 #(4, 4, 4, 4) bindline3(b00, b10, b20, b30, line3);
hdl4se_bind4 #(16, 16, 16, 16) bindline(line0, line1, line2, line3, outblock);
endmodule
module blockshape(input [3:0] sel,
output [15:0] blockshape);
hdl4se_mux16 #(16) mux_blockshape(
sel,
/* 0: {
{0,0,0,0},
{0,1,1,0},
{0,1,1,0},
{0,0,0,0},
},
*/
16'b0000_0110_0110_0000,
/* 1:
{
{1,1,1,0},
{1,1,1,0},
{1,1,1,0},
{0,0,0,0},
},
*/
16'b1110_1110_1110_0000,
/* 2:
{
{0,0,0,0},
{0,1,1,0},
{0,0,1,0},
{0,0,0,0},
},
*/
16'b0000_0110_0010_0000,
/* 3:
{
{0,0,0,0},
{0,1,0,0},
{0,0,1,0},
{0,0,0,0},
},
*/
16'b0000_0100_0010_0000,
/* 4
{
{0,1,0,0},
{0,1,1,0},
{0,0,1,0},
{0,0,0,0},
},
*/
16'b0100_0110_0010_0000,
/* 5:
{
{0,1,0,0},
{0,1,0,0},
{0,1,0,0},
{0,1,0,0},
},
*/
16'b0100_0100_0100_0100,
/* 6:
{
{0,0,1,0},
{0,1,1,0},
{0,1,0,0},
{0,0,0,0},
},
*/
16'b0010_0110_0100_0000,
/* 7:
{
{0,0,0,0},
{0,1,0,0},
{1,1,1,0},
{0,0,0,0},
}
*/
16'b0000_0100_1110_0000,
/* 8:
{
{0,0,0,0},
{0,1,0,0},
{0,0,0,0},
{0,0,0,0},
}
*/
16'b0000_0100_0000_0000,
/* 9:
{
{0,1,1,0},
{0,0,1,0},
{0,0,1,0},
{0,0,0,0},
}
*/
16'b0110_0010_0010_0000,
/* 10:
{
{0,1,1,0},
{0,1,0,0},
{0,1,0,0},
{0,0,0,0},
},
*/
16'b0110_0100_0100_0000,
/* 11:
{
{1,1,1,0},
{1,1,1,0},
{1,1,1,0},
{0,0,0,0},
},
*/
16'b1110_1110_1110_0000,
/* 12:
{
{0,0,0,0},
{0,1,1,0},
{0,0,1,0},
{0,0,0,0},
},
*/
16'b0000_0110_0010_0000,
/* 13:
{
{0,0,0,0},
{0,1,0,0},
{0,0,1,0},
{0,0,0,0},
},
*/
16'b0000_0100_0010_0000,
/* 14
{
{0,1,1,0},
{0,1,0,0},
{0,1,0,0},
{0,1,0,0},
},
*/
16'b0110_0100_0100_0100,
/* 15:
{
{0,1,0,0},
{0,1,1,0},
{0,0,1,0},
{0,0,0,0},
},
*/
16'b0100_0110_0010_0000,
blockshape
);
endmodule
`define MAXSPEED 32'd2000
/* 俄罗斯方块控制器V1 */
(*
HDL4SE="LCOM",
//HDL4SE="LCOM",
CLSID="158fa52-ca8b-4551-9b87-fc7cff466e2a",
softmodule="hdl4se"
*)
......@@ -53,10 +245,31 @@ module teris_ctrl
input [31:0] wResult
);
wire [15:0] randnum;
rand randgen(wClk, randnum);
wire [3:0] shapeindex = randnum[3:0];
wire [15:0] shapedata;
blockshape shape(shapeindex, shapedata);
wire [3:0] colorindex_0 = randnum[3:0];
wire [3:0] colorindex = ( (colorindex_0 == 0) || (colorindex_0 == 1) ) ? (colorindex_0 + 4) : colorindex_0;
wire [15:0] wirein_shapedata, wireout_shapedata;
hdl4se_reg #(16) terris_shape(wClk, wirein_shapedata, wireout_shapedata);
wire clearkey;
wire [31:0] wirein_key, wireout_key;
hdl4se_reg #(31) terris_key(wClk, wirein_key, wireout_key);
wire [31:0] cur_key = (wireout_key == bKeyData) ? 0 : bKeyData;
assign wirein_key = bKeyData;
wire [3:0] wirein_state, wireout_state;
hdl4se_reg #(4) terris_ctrlstate(wClk, wirein_state, wireout_state);
assign bState = wireout_state;
assign wirein_state = nwReset ? nextstate : 7;
wire [31:0] wirein_score, wireout_score;
hdl4se_reg #(32) terris_score(wClk, wirein_score, wireout_score);
assign bScore = wireout_score;
......@@ -67,11 +280,14 @@ module teris_ctrl
wire [31:0] wirein_speed, wireout_speed;
hdl4se_reg #(32) terris_speed(wClk, wirein_speed, wireout_speed);
assign bSpeed = wireout_speed;
assign bSpeed = `MAXSPEED - wireout_speed;
wire [15:0] wirein_curpos, wireout_curpos;
hdl4se_reg #(15) terris_curpos(wClk, wirein_curpos, wireout_curpos);
assign bCurBlockPos = wireout_curpos;
wire [7:0] wirein_curposx, wireout_curposx;
hdl4se_reg #(8) terris_curposx(wClk, wirein_curposx, wireout_curposx);
wire [7:0] wirein_curposy, wireout_curposy;
hdl4se_reg #(8) terris_curposy(wClk, wirein_curposy, wireout_curposy);
wire [7:0] outputy = `YCOUNT + 1 - wireout_curposy;
hdl4se_bind2 #(8, 8) bindpos(wireout_curposx, outputy, bCurBlockPos);
wire [63:0] wirein_curblock, wireout_curblock;
hdl4se_reg #(64) terris_curblock(wClk, wirein_curblock, wireout_curblock);
......@@ -81,17 +297,88 @@ module teris_ctrl
hdl4se_reg #(64) terris_nextblock(wClk, wirein_nextblock, wireout_nextblock);
assign bNextBlock = wireout_nextblock;
hdl4se_mux8 #(32) mux_nextstate(
wire [3:0] stateAfterInit, stateAfterFlushToDisp,
stateAfterCheckKey, stateAfterCheckBlockCanSetTo,
stateAfterBlockWrite, stateAfterCheckLine,
stateAfterCopyLines, nextstate;
assign stateAfterInit = wStateComplete ? `ST_FLUSHTODISP : `ST_INIT;
assign stateAfterFlushToDisp = wStateComplete ? `ST_CHECKKEY : `ST_FLUSHTODISP;
assign stateAfterCheckKey = wStateComplete ? `ST_FLUSHTODISP : `ST_FLUSHTODISP;
assign stateAfterCheckBlockCanSetTo = wStateComplete ? `ST_FLUSHTODISP : `ST_FLUSHTODISP;
assign stateAfterBlockWrite = wStateComplete ? `ST_FLUSHTODISP : `ST_FLUSHTODISP;
assign stateAfterCheckLine = wStateComplete ? `ST_FLUSHTODISP : `ST_FLUSHTODISP;
assign stateAfterCopyLines = wStateComplete ? `ST_FLUSHTODISP : `ST_FLUSHTODISP;
/*
在初始化面板的同时，初始化其他的一些内容：
1 -- 初始化分数级别速度当前块位置等
10 -- 25 初始化nextblock
30 -- 45 初始化currentblock
*/
wire [6:0] wirein_initclock, wireout_initclock;
hdl4se_reg #(7) terris_initclock(wClk, wirein_initclock, wireout_initclock);
assign wirein_initclock = (wireout_state == `ST_INIT) ? (wireout_initclock + 1) : 0;
wire wirein_gennewblock, wireout_gennewblock;
hdl4se_reg #(1) terris_gennewblock(wClk, wirein_gennewblock, wireout_gennewblock);
assign wirein_gennewblock = (wireout_state == `ST_INIT) ? 1 : gennewblock;
wire gennewblock = (wireout_state == `ST_CHECKKEY) && (wireout_curposy > 24);
wire [6:0] wirein_genblock_count, wireout_genblock_count;
hdl4se_reg #(7) terris_genblock_count(wClk, wirein_genblock_count, wireout_genblock_count);
assign wirein_genblock_count = ( (wireout_genblock_count < 7'd50) && (wireout_gennewblock)) ? (wireout_genblock_count + 1) : 0;
assign wirein_score = (wireout_initclock == 1) ? 32'd200 : wire_score;
wire [31:0] wire_score;
assign wire_score = wireout_score;
assign wirein_speed = (wireout_initclock == 1) ? 32'd0 : wire_speed;
wire [31:0] scorediv4 = wireout_score[31:4];
wire [31:0] wire_speed = (`MAXSPEED > scorediv4) ? (`MAXSPEED - scorediv4) : 1;
assign wirein_level = (wireout_initclock == 1) ? 32'd0 : wire_level;
wire [31:0] wire_level;
assign wire_level = wireout_level;
wire [31:0] wirein_speed_count, wireout_speed_count;
hdl4se_reg #(31) terris_speed_count(wClk, wirein_speed_count, wireout_speed_count);
assign wirein_speed_count = (wireout_speed_count > 0) ? (wireout_speed_count - 1) : ((wireout_state == `ST_CHECKKEY)?wire_speed:0);
wire [7:0] newblockx = cur_key[0] ? (wireout_curposx+1) : (cur_key[1] ? (wireout_curposx-1) : wireout_curposx);
wire [7:0] newblocky = ((wireout_state == `ST_CHECKKEY) && (wireout_speed_count == 0) && (cur_key == 0)) ? (wireout_curposy + 1) : wireout_curposy;
assign clearkey = (wireout_state == `ST_CHECKKEY);
assign wirein_curposx = newshape ? 8 : newblockx;
assign wirein_curposy = newshape ? 0 : newblocky;
assign wirein_curblock = cur_key[3] ? turnleftblock: (newshape ? wireout_nextblock : wireout_curblock);
wire setshape = ((wireout_genblock_count >= 2) && (wireout_genblock_count <= 17));
wire newshape = (wireout_genblock_count == 1);
assign wirein_shapedata = newshape ? shapedata : (setshape ? settoshape : wireout_shapedata);
wire [15:0] settoshape;
hdl4se_bind2 #(15, 1) nextblockshape(wireout_shapedata[15:1], wireout_shapedata[0], settoshape);
wire [63:0] newblock;
wire [63:0] turnleftblock;
turnleft turnleft(wireout_curblock, turnleftblock);
hdl4se_bind2 #(60, 4) newnextblock(wireout_nextblock[63:4], wireout_shapedata[0]?colorindex:4'b0000, newblock);
assign wirein_nextblock = setshape ? newblock : wireout_nextblock;
hdl4se_mux8 #(4) mux_nextstate(
wireout_state,
`ST_FLUSHTODISP, // 0: ST_INIT
`ST_CHECKKEY, // 1: ST_FLUSHTODISP,
32'b0, // 2: ST_CHECKKEY,
wCBWCanSetTo, // 3: ST_CHECKBLOCKCANSETTO,
32'b0, // 4: ST_BLOCKWRITE,
bCKLResult, // 5: ST_CHECKLINE,
32'b0, // 6: ST_COPYLINES
32'b0, // 7: empty
bResult
stateAfterInit, // 0: ST_INIT
stateAfterFlushToDisp, // 1: ST_FLUSHTODISP,
stateAfterCheckKey, // 2: ST_CHECKKEY,
stateAfterCheckBlockCanSetTo,// 3: ST_CHECKBLOCKCANSETTO,
stateAfterBlockWrite, // 4: ST_BLOCKWRITE,
stateAfterCheckLine, // 5: ST_CHECKLINE,
stateAfterCopyLines, // 6: ST_COPYLINES
`ST_INIT, // 7: reset
nextstate
);
endmodule
\ No newline at end of file
examples/terris/verilog/terris_main_asm.v
浏览文件 @ 2f518ba1
......@@ -423,8 +423,84 @@ module hdl4se_reg
endmodule
module rand
(
input wClk,
output [15:0] randnum
)
;
wire [31:0] wirein_num;
wire [31:0] wireout_num;
assign randnum = wireout_num [15:0] ;
assign wirein_num = ((wireout_num*32'd214013)+32'd2531011);
hdl4se_reg #( 32 ) reg_rand( wClk, wirein_num, wireout_num );
endmodule
module turnleft
(
input [63:0] inblock,
output [63:0] outblock
)
;
wire [3:0] b00;
wire [3:0] b01;
wire [3:0] b02;
wire [3:0] b03;
wire [3:0] b10;
wire [3:0] b11;
wire [3:0] b12;
wire [3:0] b13;
wire [3:0] b20;
wire [3:0] b21;
wire [3:0] b22;
wire [3:0] b23;
wire [3:0] b30;
wire [3:0] b31;
wire [3:0] b32;
wire [3:0] b33;
wire [15:0] line0;
wire [15:0] line1;
wire [15:0] line2;
wire [15:0] line3;
assign b00 = inblock [3:0] ;
assign b01 = inblock [7:4] ;
assign b02 = inblock [11:8] ;
assign b03 = inblock [15:12] ;
assign b10 = inblock [19:16] ;
assign b11 = inblock [23:20] ;
assign b12 = inblock [27:24] ;
assign b13 = inblock [31:28] ;
assign b20 = inblock [35:32] ;
assign b21 = inblock [39:36] ;
assign b22 = inblock [43:40] ;
assign b23 = inblock [47:44] ;
assign b30 = inblock [51:48] ;
assign b31 = inblock [55:52] ;
assign b32 = inblock [59:56] ;
assign b33 = inblock [63:60] ;
hdl4se_bind4 #( 4, 4, 4, 4 ) bindline0( b03, b13, b23, b33, line0 );
hdl4se_bind4 #( 4, 4, 4, 4 ) bindline1( b02, b12, b22, b32, line1 );
hdl4se_bind4 #( 4, 4, 4, 4 ) bindline2( b01, b11, b21, b31, line2 );
hdl4se_bind4 #( 4, 4, 4, 4 ) bindline3( b00, b10, b20, b30, line3 );
hdl4se_bind4 #( 16, 16, 16, 16 ) bindline( line0, line1, line2, line3, outblock );
endmodule
module blockshape
(
input [3:0] sel,
output [15:0] blockshape
)
;
hdl4se_mux16 #( 16 ) mux_blockshape( sel, 1632, 61152, 1568, 1056, 17952
, 17476, 9792, 1248, 1024, 25120
, 25664, 61152, 1568, 1056, 25668
, 17952, blockshape );
endmodule
(*
HDL4SE = "LCOM",
CLSID = "158fa52-ca8b-4551-9b87-fc7cff466e2a",
softmodule = "hdl4se"
*)
......@@ -444,6 +520,17 @@ module teris_ctrl
input [31:0] wResult
)
;
wire [15:0] randnum;
wire [3:0] shapeindex;
wire [15:0] shapedata;
wire [3:0] colorindex_0;
wire [3:0] colorindex;
wire [15:0] wirein_shapedata;
wire [15:0] wireout_shapedata;
wire clearkey;
wire [31:0] wirein_key;
wire [31:0] wireout_key;
wire [31:0] cur_key;
wire [3:0] wirein_state;
wire [3:0] wireout_state;
wire [31:0] wirein_score;
......@@ -452,28 +539,107 @@ module teris_ctrl
wire [31:0] wireout_level;
wire [31:0] wirein_speed;
wire [31:0] wireout_speed;
wire [15:0] wirein_curpos;
wire [15:0] wireout_curpos;
wire [7:0] wirein_curposx;
wire [7:0] wireout_curposx;
wire [7:0] wirein_curposy;
wire [7:0] wireout_curposy;
wire [7:0] outputy;
wire [63:0] wirein_curblock;
wire [63:0] wireout_curblock;
wire [63:0] wirein_nextblock;
wire [63:0] wireout_nextblock;
wire [3:0] stateAfterInit;
wire [3:0] stateAfterFlushToDisp;
wire [3:0] stateAfterCheckKey;
wire [3:0] stateAfterCheckBlockCanSetTo;
wire [3:0] stateAfterBlockWrite;
wire [3:0] stateAfterCheckLine;
wire [3:0] stateAfterCopyLines;
wire [3:0] nextstate;
wire [6:0] wirein_initclock;
wire [6:0] wireout_initclock;
wire wirein_gennewblock;
wire wireout_gennewblock;
wire gennewblock;
wire [6:0] wirein_genblock_count;
wire [6:0] wireout_genblock_count;
wire [31:0] wire_score;
wire [31:0] scorediv4;
wire [31:0] wire_speed;
wire [31:0] wire_level;
wire [31:0] wirein_speed_count;
wire [31:0] wireout_speed_count;
wire [7:0] newblockx;
wire [7:0] newblocky;
wire setshape;
wire newshape;
wire [15:0] settoshape;
wire [63:0] newblock;
wire [63:0] turnleftblock;
assign wirein_key = bKeyData;
assign bState = wireout_state;
assign wirein_state = ((nwReset)?(nextstate):(7));
assign bScore = wireout_score;
assign bLevel = wireout_level;
assign bSpeed = wireout_speed;
assign bCurBlockPos = wireout_curpos;
assign bSpeed = (32'h7d0-wireout_speed);
assign bCurBlock = wireout_curblock;
assign bNextBlock = wireout_nextblock;
assign stateAfterInit = ((wStateComplete)?(1):(0));
assign stateAfterFlushToDisp = ((wStateComplete)?(2):(1));
assign stateAfterCheckKey = ((wStateComplete)?(1):(1));
assign stateAfterCheckBlockCanSetTo = ((wStateComplete)?(1):(1));
assign stateAfterBlockWrite = ((wStateComplete)?(1):(1));
assign stateAfterCheckLine = ((wStateComplete)?(1):(1));
assign stateAfterCopyLines = ((wStateComplete)?(1):(1));
assign wirein_initclock = (((wireout_state==0))?((wireout_initclock+1)):(0));
assign wirein_gennewblock = (((wireout_state==0))?(1):(gennewblock));
assign wirein_genblock_count = ((((wireout_genblock_count<7'd50)&&wireout_gennewblock))?((wireout_genblock_count+1)):(0));
assign wirein_score = (((wireout_initclock==1))?(32'd200):(wire_score));
assign wire_score = wireout_score;
assign wirein_speed = (((wireout_initclock==1))?(32'd0):(wire_speed));
assign wirein_level = (((wireout_initclock==1))?(32'd0):(wire_level));
assign wire_level = wireout_level;
assign wirein_speed_count = (((wireout_speed_count>0))?((wireout_speed_count-1)):((((wireout_state==2))?(wire_speed):(0))));
assign clearkey = (wireout_state==2);
assign wirein_curposx = ((newshape)?(8):(newblockx));
assign wirein_curposy = ((newshape)?(0):(newblocky));
assign wirein_curblock = ((cur_key [3] )?(turnleftblock):(((newshape)?(wireout_nextblock):(wireout_curblock))));
assign wirein_shapedata = ((newshape)?(shapedata):(((setshape)?(settoshape):(wireout_shapedata))));
assign wirein_nextblock = ((setshape)?(newblock):(wireout_nextblock));
assign shapeindex = randnum [3:0] ;
assign colorindex_0 = randnum [3:0] ;
assign colorindex = ((((colorindex_0==0)||(colorindex_0==1)))?((colorindex_0+4)):(colorindex_0));
assign cur_key = (((wireout_key==bKeyData))?(0):(bKeyData));
assign outputy = (24+(1-wireout_curposy));
assign gennewblock = ((wireout_state==2)&&(wireout_curposy>24));
assign scorediv4 = wireout_score [31:4] ;
assign wire_speed = (((32'h7d0>scorediv4))?((32'd2000-scorediv4)):(1));
assign newblockx = ((cur_key [0] )?((wireout_curposx+1)):(((cur_key [1] )?((wireout_curposx-1)):(wireout_curposx))));
assign newblocky = ((((wireout_state==2)&&((wireout_speed_count==0)&&(cur_key==0))))?((wireout_curposy+1)):(wireout_curposy));
assign setshape = ((wireout_genblock_count>=2)&&(wireout_genblock_count<=17));
assign newshape = (wireout_genblock_count==1);
rand randgen( wClk, randnum );
blockshape shape( shapeindex, shapedata );
hdl4se_reg #( 16 ) terris_shape( wClk, wirein_shapedata, wireout_shapedata );
hdl4se_reg #( 31 ) terris_key( wClk, wirein_key, wireout_key );
hdl4se_reg #( 4 ) terris_ctrlstate( wClk, wirein_state, wireout_state );
hdl4se_reg #( 32 ) terris_score( wClk, wirein_score, wireout_score );
hdl4se_reg #( 32 ) terris_level( wClk, wirein_level, wireout_level );
hdl4se_reg #( 32 ) terris_speed( wClk, wirein_speed, wireout_speed );
hdl4se_reg #( 15 ) terris_curpos( wClk, wirein_curpos, wireout_curpos );
hdl4se_reg #( 8 ) terris_curposx( wClk, wirein_curposx, wireout_curposx );
hdl4se_reg #( 8 ) terris_curposy( wClk, wirein_curposy, wireout_curposy );
hdl4se_bind2 #( 8, 8 ) bindpos( wireout_curposx, outputy, bCurBlockPos );
hdl4se_reg #( 64 ) terris_curblock( wClk, wirein_curblock, wireout_curblock );
hdl4se_reg #( 64 ) terris_nextblock( wClk, wirein_nextblock, wireout_nextblock );
hdl4se_mux8 #( 32 ) mux_nextstate( wireout_state, 1, 2, 32'h0, wCBWCanSetTo, 32'h0
, bCKLResult, 32'h0, 32'h0, bResult );
hdl4se_reg #( 7 ) terris_initclock( wClk, wirein_initclock, wireout_initclock );
hdl4se_reg #( 1 ) terris_gennewblock( wClk, wirein_gennewblock, wireout_gennewblock );
hdl4se_reg #( 7 ) terris_genblock_count( wClk, wirein_genblock_count, wireout_genblock_count );
hdl4se_reg #( 31 ) terris_speed_count( wClk, wirein_speed_count, wireout_speed_count );
hdl4se_bind2 #( 15, 1 ) nextblockshape( wireout_shapedata [15:1] , wireout_shapedata [0] , settoshape );
turnleft turnleft( wireout_curblock, turnleftblock );
hdl4se_bind2 #( 60, 4 ) newnextblock( wireout_nextblock [63:4] , ((wireout_shapedata [0] )?(colorindex):(4'b0000)), newblock );
hdl4se_mux8 #( 4 ) mux_nextstate( wireout_state, stateAfterInit, stateAfterFlushToDisp, stateAfterCheckKey, stateAfterCheckBlockCanSetTo, stateAfterBlockWrite
, stateAfterCheckLine, stateAfterCopyLines, 0, nextstate );
endmodule
......
hdl4secell/src/hdl4se_bind2.c
浏览文件 @ 2f518ba1
......@@ -44,6 +44,7 @@
#include "bignumber.h"
#include "hdl4secell.h"
#define HDL4SEDEBUG 0
/*
HDL4SE_BIND2
......@@ -247,8 +248,17 @@ static int hdl4se_bind2_hdl4se_unit_GetValue(HOBJECT object, int index, int widt
objectCall1(pobj->out_data, SetUnsigned, 1);
objectCall1(pobj->out_data, SetWidth, outputwidth);
for (i = BINDCOUNT - 1; i >= 0; i--) {
#if HDL4SEDEBUG
char buf[60];
objectCall3(pobj->in_data[i], GetStr, 16, buf, 60);
objectCall3(pobj->out_data, GetStr, 16, buf, 60);
#endif
objectCall2(pobj->out_data, SHL, pobj->out_data, pobj->inputwidth[i]);
objectCall2(pobj->out_data, Or, pobj->out_data, pobj->in_data[i]);
#if HDL4SEDEBUG
objectCall3(pobj->out_data, GetStr, 16, buf, 60);
objectCall3(pobj->in_data[i], GetStr, 16, buf, 60);
#endif
}
pobj->datavalid = 1;
}
......@@ -258,7 +268,7 @@ static int hdl4se_bind2_hdl4se_unit_GetValue(HOBJECT object, int index, int widt
}
objectCall1(value, Assign, pobj->out_data);
return 0;
}
}
static int hdl4se_bind2_hdl4se_unit_ClkTick(HOBJECT object)
{
......
hdl4secell/src/hdl4se_split1.c
浏览文件 @ 2f518ba1
......@@ -43,6 +43,7 @@
#include "bignumber.h"
#include "hdl4secell.h"
#define HDL4SEDEBUG 0
/*
HDL4SE_SPLIT1
......@@ -241,6 +242,7 @@ static int hdl4se_split1_hdl4se_unit_ConnectPart(HOBJECT object, int index, int
return 0;
}
static int hdl4se_split1_hdl4se_unit_GetValue(HOBJECT object, int index, int width, IBigNumber** value)
{
int i;
......@@ -250,9 +252,16 @@ static int hdl4se_split1_hdl4se_unit_GetValue(HOBJECT object, int index, int wid
return -1;
if (pobj->datavalid == 0) {
objectCall3(pobj->in, GetValue, pobj->in_index, pobj->width, pobj->in_data);
#if HDL4SEDEBUG
char buf[60];
objectCall3(pobj->in_data, GetStr, 16, buf, 60);
#endif
pobj->datavalid = 1;
for (i = 0; i < SPLITCOUNT; i++) {
objectCall3(pobj->out_data[i], AssignSubBits, pobj->in_data, pobj->out_info[i][1], pobj->out_info[i][0]);
#if HDL4SEDEBUG
objectCall3(pobj->out_data[i], GetStr, 16, buf, 60);
#endif
}
pobj->datavalid = 1;
}
......
testparser/main.c
浏览文件 @ 2f518ba1
......@@ -18,8 +18,8 @@ char* yytext;
static char logbuf[64 * 1024];
#define TERRIS 0
#define COUNTER 1
#define TERRIS 1
#define COUNTER 0
int main(int argc, char* argv[])
{
......
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