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提交 7c4b6d68 编写于 作者: 饶先宏's avatar 饶先宏
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202109081340

上级 0a05b736 4d58e88c
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Showing with 7691 addition and 1549 deletion
examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt
浏览文件 @ 7c4b6d68
...@@ -33,6 +33,11 @@ add_executable(riscv_sim ...@@ -33,6 +33,11 @@ add_executable(riscv_sim
"hdl4se_riscv_core.c" "hdl4se_riscv_core.c"
) )
add_executable(cod2mif
"cod2mif.c"
)
add_definitions(-D_CRT_SECURE_NO_WARNINGS) add_definitions(-D_CRT_SECURE_NO_WARNINGS)
if(WIN32) if(WIN32)
......
examples/hdl4se_riscv/hdl4se_riscv_sim/cod2mif.c 0 → 100644
浏览文件 @ 7c4b6d68
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* cod2mif.c
202109080600: rxh, initial version
*/
#include "stdlib.h"
#include "stdio.h"
#include "string.h"
int main(int argc, char * argv[])
{
unsigned int addr;
unsigned int RAMSIZE;
unsigned char* data;
if (argc < 4) {
printf("Usage : %s <codfile> <miffile> <size>\n", argv[0]);
exit(-1);
}
FILE* pFile = fopen(argv[1], "rt");
RAMSIZE = atoi(argv[3]);
if (RAMSIZE < 0x10 || RAMSIZE > 16 * 1024 * 1024) {
printf("size %d must between 16 .. 16M\n", RAMSIZE);
exit(-2);
}
if (pFile == NULL) {
printf("File %s can not open\n", argv[1]);
exit(-1);
}
data = (unsigned int*)malloc(RAMSIZE * 4);
addr = 0;
while (!feof(pFile)) {
char line[256];
fgets(line, 256, pFile);
if (strlen(line) < 2)
break;
if (line[0] == '@') {
sscanf(line + 1, "%08x", &addr);
}
else {
int len;
int i;
unsigned int temp[16];
if (addr >= RAMSIZE*4 - 16) {
printf("read file failed, address [%08x] overflow(maxaddr = %08x)\n", addr, RAMSIZE*4);
exit(-5);
}
len = sscanf(line, "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X",
&temp[0], &temp[1], &temp[2], &temp[3],
&temp[4], &temp[5], &temp[6], &temp[7],
&temp[8], &temp[9], &temp[10], &temp[11],
&temp[12], &temp[13], &temp[14], &temp[15]);
for (i = 0; i < len; i++)
data[addr + i] = temp[i];
addr += len;
}
}
fclose(pFile);
pFile = fopen(argv[2], "wt");
if (pFile == NULL) {
printf("Can create file %s\n", argv[2]);
exit(-3); }
fprintf(pFile, "DEPTH = %d;\n", RAMSIZE);
fprintf(pFile, "WIDTH = 32;\n");
fprintf(pFile, "ADDRESS_RADIX = HEX;\n");
fprintf(pFile, "DATA_RADIX = HEX;\n");
fprintf(pFile, "CONTENT\n");
fprintf(pFile, "BEGIN\n");
for (addr = 0; addr < RAMSIZE; addr++) {
fprintf(pFile, "%04X : %08X;\n", addr, *(unsigned int *)(data + addr * 4));
}
fprintf(pFile, "END;\n");
fclose(pFile);
return 0;
}
examples/hdl4se_riscv/test_code/console.bat
浏览文件 @ 7c4b6d68
set pathold=%path%
set path=%path%;D:/gitwork/riscv-tools-rv32im/bin;D:/gitwork/riscv-tools-rv32im/cygwin64/bin d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-gcc.exe -ffunction-sections -fdata-sections -Wl,-Tnostdlib.ld -Wl,--gc-sections console.c csr.S -o test.elf
riscv32-unknown-elf-gcc -nostdlib -ffunction-sections -fdata-sections -Wl,-Tnostdlib.ld -Wl,--gc-sections console.c csr.S -o test.elf d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-objcopy.exe test.elf -O ihex test.hex
riscv32-unknown-elf-objcopy test.elf -O ihex test.hex d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-objcopy.exe test.elf -O verilog test.cod
riscv32-unknown-elf-objcopy test.elf -O verilog test.cod d:/gitwork/riscv-tools-rv32im/bin/cod2mif.exe test.cod test.mif 1024
riscv32-unknown-elf-objdump -D -M no-aliases,numeric test.elf > test.txt d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-objdump.exe -D -M no-aliases,numeric test.elf > test.txt
riscv32-unknown-elf-readelf -a test.elf > test.info d:/gitwork/riscv-tools-rv32im/bin/riscv32-unknown-elf-readelf.exe -a test.elf > test.info
set path=%pathold%
examples/hdl4se_riscv/test_code/test.cod 已删除 100644 → 0
浏览文件 @ 0a05b736
@00000000
37 11 00 00 EF 00 50 29 6F F0 9F FF
@0000000C
13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00
83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A6 E7 EE B7 17 00 00 83 A7 C7 EE 93 F7 17 00
93 B7 17 00 93 F7 F7 0F 13 85 07 00 03 24 C1 00
13 01 01 01 67 80 00 00
@00000054
13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00
83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A6 E7 EE B7 17 00 00 03 A7 C7 EE B7 07 01 00
B3 77 F7 00 93 B7 17 00 93 F7 F7 0F 13 85 07 00
03 24 C1 00 13 01 01 01 67 80 00 00
@000000A0
13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
B7 17 00 00 83 A7 47 EE 93 87 87 00 03 A7 07 00
B7 17 00 00 23 A6 E7 EE B7 17 00 00 83 A7 C7 EE
93 F7 17 00 63 90 07 02 B7 17 00 00 83 A7 47 EE
93 87 47 00 03 27 C4 FE 23 A0 E7 00 93 07 00 00
6F 00 80 00 93 07 F0 FF 13 85 07 00 03 24 C1 01
13 01 01 02 67 80 00 00
@00000108
13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00
83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A6 E7 EE B7 17 00 00 03 A7 C7 EE B7 07 01 00
B3 77 F7 00 63 9A 07 00 B7 17 00 00 83 A7 47 EE
83 A7 07 00 6F 00 80 00 93 07 F0 FF 13 85 07 00
03 24 C1 00 13 01 01 01 67 80 00 00
@00000164
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
23 26 A4 FE 6F 00 00 03 13 00 00 00 83 27 C4 FE
83 C7 07 00 13 85 07 00 EF F0 5F F1 13 07 05 00
93 07 F0 FF E3 04 F7 FE 83 27 C4 FE 93 87 17 00
23 26 F4 FE 83 27 C4 FE 83 C7 07 00 E3 96 07 FC
93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01
13 01 01 02 67 80 00 00
@000001CC
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC 23 2C B4 FC 23 26 04 FE 03 27 84 FD
93 07 10 00 63 C6 E7 00 93 07 00 00 6F 00 80 09
EF F0 DF F0 23 24 A4 FE 03 27 84 FE 93 07 F0 FF
E3 08 F7 FE 83 27 C4 FE 13 87 17 00 23 26 E4 FE
13 87 07 00 83 27 C4 FD B3 87 E7 00 03 27 84 FE
13 77 F7 0F 23 80 E7 00 13 00 00 00 03 25 84 FE
EF F0 5F E6 13 07 05 00 93 07 F0 FF E3 08 F7 FE
83 27 84 FD 93 87 F7 FF 03 27 C4 FE 63 50 F7 02
03 27 84 FE 93 07 A0 00 63 0C F7 00 03 27 84 FE
93 07 D0 00 63 06 F7 00 6F F0 9F F8 13 00 00 00
83 27 C4 FE 03 27 C4 FD B3 07 F7 00 23 80 07 00
83 27 C4 FE 13 85 07 00 83 20 C1 02 03 24 81 02
13 01 01 03 67 80 00 00
@000002A4
13 01 01 FC 23 2E 81 02 13 04 01 04 23 26 A4 FC
23 24 B4 FC 23 24 04 FE 23 22 04 FE 83 27 84 FC
63 DA 07 00 83 27 84 FC B3 07 F0 40 23 24 F4 FC
23 22 04 FE 83 27 84 FC 63 96 07 06 83 27 84 FE
13 87 17 00 23 24 E4 FE 13 87 07 00 83 27 C4 FC
B3 87 E7 00 13 07 00 03 23 80 E7 00 6F 00 80 07
03 27 84 FC 93 07 A0 00 B3 67 F7 02 13 F7 F7 0F
83 27 84 FE 93 86 17 00 23 24 D4 FE 93 86 07 00
83 27 C4 FC B3 87 D7 00 13 07 07 03 13 77 F7 0F
23 80 E7 00 03 27 84 FC 93 07 A0 00 B3 47 F7 02
23 24 F4 FC 83 27 84 FC E3 4C F0 FA 83 27 44 FE
63 82 07 02 83 27 84 FE 13 87 17 00 23 24 E4 FE
13 87 07 00 83 27 C4 FC B3 87 E7 00 13 07 D0 02
23 80 E7 00 23 26 04 FE 6F 00 C0 06 83 27 84 FE
13 87 F7 FF 83 27 C4 FE B3 07 F7 40 23 20 F4 FE
83 27 C4 FE 03 27 C4 FC B3 07 F7 00 83 C7 07 00
A3 0F F4 FC 83 27 04 FE 03 27 C4 FC 33 07 F7 00
83 27 C4 FE 83 26 C4 FC B3 87 F6 00 03 47 07 00
23 80 E7 00 83 27 04 FE 03 27 C4 FC B3 07 F7 00
03 47 F4 FD 23 80 E7 00 83 27 C4 FE 93 87 17 00
23 26 F4 FE 83 27 84 FE 13 D7 F7 01 B3 07 F7 00
93 D7 17 40 13 87 07 00 83 27 C4 FE E3 C0 E7 F8
83 27 84 FE 03 27 C4 FC B3 07 F7 00 23 80 07 00
83 27 84 FE 13 85 07 00 03 24 C1 03 13 01 01 04
67 80 00 00
@00000428
13 01 01 FB 23 26 81 04 13 04 01 05 23 26 A4 FC
23 20 B4 FC 23 22 C4 FC 23 24 D4 FC 93 07 07 00
A3 0F F4 FA 23 24 04 FE 6F 00 00 09 83 27 04 FC
93 F7 F7 00 23 2E F4 FC 03 27 C4 FD 93 07 90 00
63 C4 E7 02 83 27 C4 FD 13 F7 F7 0F 83 27 84 FE
83 26 C4 FC B3 87 F6 00 13 07 07 03 13 77 F7 0F
23 80 E7 00 6F 00 40 02 83 27 C4 FD 13 F7 F7 0F
83 27 84 FE 83 26 C4 FC B3 87 F6 00 13 07 77 05
13 77 F7 0F 23 80 E7 00 83 27 44 FC 93 97 C7 01
03 27 04 FC 13 58 47 00 33 E8 07 01 83 27 44 FC
93 D8 47 00 23 20 04 FD 23 22 14 FD 83 27 84 FE
93 87 17 00 23 24 F4 FE 83 27 04 FC 03 27 44 FC
B3 E7 E7 00 E3 94 07 F6 6F 00 40 02 83 27 84 FE
13 87 17 00 23 24 E4 FE 13 87 07 00 83 27 C4 FC
B3 87 E7 00 03 47 F4 FB 23 80 E7 00 03 27 84 FE
83 27 84 FC E3 4C F7 FC 23 26 04 FE 6F 00 C0 06
83 27 84 FE 13 87 F7 FF 83 27 C4 FE B3 07 F7 40
23 22 F4 FE 83 27 C4 FE 03 27 C4 FC B3 07 F7 00
83 C7 07 00 A3 01 F4 FE 83 27 44 FE 03 27 C4 FC
33 07 F7 00 83 27 C4 FE 83 26 C4 FC B3 87 F6 00
03 47 07 00 23 80 E7 00 83 27 44 FE 03 27 C4 FC
B3 07 F7 00 03 47 34 FE 23 80 E7 00 83 27 C4 FE
93 87 17 00 23 26 F4 FE 83 27 84 FE 13 D7 F7 01
B3 07 F7 00 93 D7 17 40 13 87 07 00 83 27 C4 FE
E3 C0 E7 F8 83 27 84 FE 03 27 C4 FC B3 07 F7 00
23 80 07 00 83 27 84 FE 13 85 07 00 03 24 C1 04
13 01 01 05 67 80 00 00
@000005D0
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 93 07 10 00
23 22 F4 FE 6F 00 C0 08 83 27 C4 FD 83 C7 07 00
23 20 F4 FE 03 27 04 FE 93 07 F0 02 63 D2 E7 04
03 27 04 FE 93 07 90 03 63 CC E7 02 03 27 84 FE
93 07 07 00 93 97 27 00 B3 87 E7 00 93 97 17 00
13 87 07 00 83 27 04 FE B3 07 F7 00 93 87 07 FD
23 24 F4 FE 93 07 10 00 23 26 F4 FE 6F 00 80 02
83 27 C4 FE 63 9E 07 02 03 27 04 FE 93 07 D0 02
63 1A F7 00 93 07 F0 FF 23 22 F4 FE 93 07 10 00
23 26 F4 FE 83 27 C4 FD 93 87 17 00 23 2E F4 FC
83 27 C4 FD 83 C7 07 00 E3 98 07 F6 6F 00 80 00
13 00 00 00 03 27 84 FE 83 27 44 FE B3 07 F7 02
23 24 F4 FE 83 27 84 FD 63 88 07 00 83 27 84 FD
03 27 C4 FD 23 A0 E7 00 83 27 84 FE 13 85 07 00
03 24 C1 02 13 01 01 03 67 80 00 00
@000006CC
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 6F 00 00 0E
83 27 C4 FD 83 C7 07 00 23 22 F4 FE 03 27 44 FE
93 07 F0 02 63 DA E7 02 03 27 44 FE 93 07 90 03
63 C4 E7 02 93 07 10 00 23 26 F4 FE 83 27 84 FE
13 97 47 00 83 27 44 FE B3 07 F7 00 93 87 07 FD
23 24 F4 FE 6F 00 C0 08 03 27 44 FE 93 07 00 06
63 DA E7 02 03 27 44 FE 93 07 60 06 63 C4 E7 02
93 07 10 00 23 26 F4 FE 83 27 84 FE 13 97 47 00
83 27 44 FE B3 07 F7 00 93 87 97 FA 23 24 F4 FE
6F 00 00 05 03 27 44 FE 93 07 00 04 63 DA E7 02
03 27 44 FE 93 07 60 04 63 C4 E7 02 93 07 10 00
23 26 F4 FE 83 27 84 FE 13 97 47 00 83 27 44 FE
B3 07 F7 00 93 87 97 FC 23 24 F4 FE 6F 00 40 01
83 27 C4 FE 63 94 07 02 93 07 10 00 23 26 F4 FE
83 27 C4 FD 93 87 17 00 23 2E F4 FC 83 27 C4 FD
83 C7 07 00 E3 9E 07 F0 6F 00 80 00 13 00 00 00
83 27 84 FD 63 88 07 00 83 27 84 FD 03 27 C4 FD
23 A0 E7 00 83 27 84 FE 13 85 07 00 03 24 C1 02
13 01 01 03 67 80 00 00
@00000804
13 01 01 FB 23 26 11 04 23 24 81 04 23 22 21 05
23 20 31 05 23 2E 41 03 23 2C 51 03 13 04 01 05
B7 17 00 00 83 A7 87 EE 93 F7 07 FF 23 2A F4 FC
23 2C 04 FC 6F 00 C0 1B 83 27 44 FD 13 89 07 00
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93 07 C4 FB 13 85 07 00 EF F0 9F 8F B7 17 00 00
13 85 87 E4 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
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33 07 F7 00 B7 17 00 00 83 A7 87 EE 63 7A F7 00
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83 27 C4 FD 03 27 C4 FC B3 07 F7 00 83 C7 07 00
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EF F0 5F B4 93 07 C4 FB 13 85 07 00 EF F0 5F 87
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EF F0 1F 85 83 27 C4 FD 93 87 17 00 23 2E F4 FC
03 27 C4 FD 93 07 F0 00 E3 DC E7 F4 B7 17 00 00
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83 27 44 FD 23 28 F4 FC 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 03 C7 07 00 93 07 F0 01 63 FA E7 02
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B3 07 F7 00 83 C7 07 00 23 0E F4 FA 6F 00 C0 00
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B7 17 00 00 13 85 C7 E5 EF F0 8F F9 83 27 44 FD
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63 80 07 02 83 27 84 FD 93 87 17 00 23 2C F4 FC
03 27 84 FD 93 07 F0 00 E3 D0 E7 E4 6F 00 80 00
13 00 00 00 B7 17 00 00 13 85 07 E6 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A4 E7 EE 13 00 00 00
83 20 C1 04 03 24 81 04 03 29 41 04 83 29 01 04
03 2A C1 03 83 2A 81 03 13 01 01 05 67 80 00 00
@00000A44
13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01
B7 17 00 00 13 85 47 E6 EF F0 8F F0 B7 17 00 00
13 85 47 E7 EF F0 CF EF B7 17 00 00 13 85 87 E8
EF F0 0F EF B7 17 00 00 13 85 C7 E9 EF F0 4F EE
13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01
67 80 00 00
@00000A98
13 01 01 F8 23 2E 11 06 23 2C 81 06 23 2A 21 07
23 28 31 07 23 26 41 07 23 24 51 07 13 04 01 08
23 26 A4 F8 23 24 B4 F8 B7 07 00 F0 93 87 07 01
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B7 17 00 00 13 85 07 E6 EF F0 4F E2 03 47 04 F9
93 07 20 06 63 18 F7 04 93 07 04 F9 93 87 27 00
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6F 00 C0 29 03 47 04 F9 93 07 40 06 63 1C F7 02
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EF F0 5F B1 23 22 A4 FC 83 27 44 FC 63 58 F0 00
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6F 00 C0 25 03 47 04 F9 93 07 70 07 63 1C F7 0A
93 07 04 F9 93 87 27 00 13 07 C4 FB 93 05 07 00
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93 D7 F7 41 93 89 07 00 93 07 04 F9 13 07 00 03
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EF F0 0F E8 93 07 04 F9 13 85 07 00 EF F0 0F BB
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B7 17 00 00 13 85 07 EE EF F0 4F B3 13 00 00 00
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20 20 00 00 20 20 20 00 20 00 00 00 2D 20 00 00
20 20 7C 00 7C 0A 00 00 0A 0D 00 00 20 20 64 20
3C 61 64 64 72 3E 20 0A 00 00 00 00 20 20 62 20
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68 3E 0A 00 20 20 77 20 3C 61 64 64 72 3E 20 3C
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73 68 6F 72 74 20 40 00 69 6E 74 20 40 00 00 00
20 3D 20 00 28 00 00 00 29 0A 0D 00
@00000EE4
00 01 00 F0
@00000EE8
01 00 00 00
examples/hdl4se_riscv/test_code/test.hex 已删除 100644 → 0
浏览文件 @ 0a05b736
:0C00000037110000EF0050296FF09FFF47
:10000C00130101FF2326810013040101B71700001F
:10001C0083A747EE9387870003A70700B717000055
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:10003C0093B7170093F7F70F138507000324C1003C
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:1001840083C7070013850700EFF05FF1130705002D
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examples/hdl4se_riscv/test_code/test.mif 已删除 100644 → 0
浏览文件 @ 0a05b736
DEPTH = 1024;
WIDTH = 32;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
0000 : 00001137;
0001 : 295000EF;
0002 : FF9FF06F;
0003 : FF010113;
0004 : 00812623;
0005 : 01010413;
0006 : 000017B7;
0007 : EE47A783;
0008 : 00878793;
0009 : 0007A703;
000A : 000017B7;
000B : EEE7A623;
000C : 000017B7;
000D : EEC7A783;
000E : 0017F793;
000F : 0017B793;
0010 : 0FF7F793;
0011 : 00078513;
0012 : 00C12403;
0013 : 01010113;
0014 : 00008067;
0015 : FF010113;
0016 : 00812623;
0017 : 01010413;
0018 : 000017B7;
0019 : EE47A783;
001A : 00878793;
001B : 0007A703;
001C : 000017B7;
001D : EEE7A623;
001E : 000017B7;
001F : EEC7A703;
0020 : 000107B7;
0021 : 00F777B3;
0022 : 0017B793;
0023 : 0FF7F793;
0024 : 00078513;
0025 : 00C12403;
0026 : 01010113;
0027 : 00008067;
0028 : FE010113;
0029 : 00812E23;
002A : 02010413;
002B : FEA42623;
002C : 000017B7;
002D : EE47A783;
002E : 00878793;
002F : 0007A703;
0030 : 000017B7;
0031 : EEE7A623;
0032 : 000017B7;
0033 : EEC7A783;
0034 : 0017F793;
0035 : 02079063;
0036 : 000017B7;
0037 : EE47A783;
0038 : 00478793;
0039 : FEC42703;
003A : 00E7A023;
003B : 00000793;
003C : 0080006F;
003D : FFF00793;
003E : 00078513;
003F : 01C12403;
0040 : 02010113;
0041 : 00008067;
0042 : FF010113;
0043 : 00812623;
0044 : 01010413;
0045 : 000017B7;
0046 : EE47A783;
0047 : 00878793;
0048 : 0007A703;
0049 : 000017B7;
004A : EEE7A623;
004B : 000017B7;
004C : EEC7A703;
004D : 000107B7;
004E : 00F777B3;
004F : 00079A63;
0050 : 000017B7;
0051 : EE47A783;
0052 : 0007A783;
0053 : 0080006F;
0054 : FFF00793;
0055 : 00078513;
0056 : 00C12403;
0057 : 01010113;
0058 : 00008067;
0059 : FE010113;
005A : 00112E23;
005B : 00812C23;
005C : 02010413;
005D : FEA42623;
005E : 0300006F;
005F : 00000013;
0060 : FEC42783;
0061 : 0007C783;
0062 : 00078513;
0063 : F15FF0EF;
0064 : 00050713;
0065 : FFF00793;
0066 : FEF704E3;
0067 : FEC42783;
0068 : 00178793;
0069 : FEF42623;
006A : FEC42783;
006B : 0007C783;
006C : FC0796E3;
006D : 00000793;
006E : 00078513;
006F : 01C12083;
0070 : 01812403;
0071 : 02010113;
0072 : 00008067;
0073 : FD010113;
0074 : 02112623;
0075 : 02812423;
0076 : 03010413;
0077 : FCA42E23;
0078 : FCB42C23;
0079 : FE042623;
007A : FD842703;
007B : 00100793;
007C : 00E7C663;
007D : 00000793;
007E : 0980006F;
007F : F0DFF0EF;
0080 : FEA42423;
0081 : FE842703;
0082 : FFF00793;
0083 : FEF708E3;
0084 : FEC42783;
0085 : 00178713;
0086 : FEE42623;
0087 : 00078713;
0088 : FDC42783;
0089 : 00E787B3;
008A : FE842703;
008B : 0FF77713;
008C : 00E78023;
008D : 00000013;
008E : FE842503;
008F : E65FF0EF;
0090 : 00050713;
0091 : FFF00793;
0092 : FEF708E3;
0093 : FD842783;
0094 : FFF78793;
0095 : FEC42703;
0096 : 02F75063;
0097 : FE842703;
0098 : 00A00793;
0099 : 00F70C63;
009A : FE842703;
009B : 00D00793;
009C : 00F70663;
009D : F89FF06F;
009E : 00000013;
009F : FEC42783;
00A0 : FDC42703;
00A1 : 00F707B3;
00A2 : 00078023;
00A3 : FEC42783;
00A4 : 00078513;
00A5 : 02C12083;
00A6 : 02812403;
00A7 : 03010113;
00A8 : 00008067;
00A9 : FC010113;
00AA : 02812E23;
00AB : 04010413;
00AC : FCA42623;
00AD : FCB42423;
00AE : FE042423;
00AF : FE042223;
00B0 : FC842783;
00B1 : 0007DA63;
00B2 : FC842783;
00B3 : 40F007B3;
00B4 : FCF42423;
00B5 : FE042223;
00B6 : FC842783;
00B7 : 06079663;
00B8 : FE842783;
00B9 : 00178713;
00BA : FEE42423;
00BB : 00078713;
00BC : FCC42783;
00BD : 00E787B3;
00BE : 03000713;
00BF : 00E78023;
00C0 : 0780006F;
00C1 : FC842703;
00C2 : 00A00793;
00C3 : 02F767B3;
00C4 : 0FF7F713;
00C5 : FE842783;
00C6 : 00178693;
00C7 : FED42423;
00C8 : 00078693;
00C9 : FCC42783;
00CA : 00D787B3;
00CB : 03070713;
00CC : 0FF77713;
00CD : 00E78023;
00CE : FC842703;
00CF : 00A00793;
00D0 : 02F747B3;
00D1 : FCF42423;
00D2 : FC842783;
00D3 : FAF04CE3;
00D4 : FE442783;
00D5 : 02078263;
00D6 : FE842783;
00D7 : 00178713;
00D8 : FEE42423;
00D9 : 00078713;
00DA : FCC42783;
00DB : 00E787B3;
00DC : 02D00713;
00DD : 00E78023;
00DE : FE042623;
00DF : 06C0006F;
00E0 : FE842783;
00E1 : FFF78713;
00E2 : FEC42783;
00E3 : 40F707B3;
00E4 : FEF42023;
00E5 : FEC42783;
00E6 : FCC42703;
00E7 : 00F707B3;
00E8 : 0007C783;
00E9 : FCF40FA3;
00EA : FE042783;
00EB : FCC42703;
00EC : 00F70733;
00ED : FEC42783;
00EE : FCC42683;
00EF : 00F687B3;
00F0 : 00074703;
00F1 : 00E78023;
00F2 : FE042783;
00F3 : FCC42703;
00F4 : 00F707B3;
00F5 : FDF44703;
00F6 : 00E78023;
00F7 : FEC42783;
00F8 : 00178793;
00F9 : FEF42623;
00FA : FE842783;
00FB : 01F7D713;
00FC : 00F707B3;
00FD : 4017D793;
00FE : 00078713;
00FF : FEC42783;
0100 : F8E7C0E3;
0101 : FE842783;
0102 : FCC42703;
0103 : 00F707B3;
0104 : 00078023;
0105 : FE842783;
0106 : 00078513;
0107 : 03C12403;
0108 : 04010113;
0109 : 00008067;
010A : FB010113;
010B : 04812623;
010C : 05010413;
010D : FCA42623;
010E : FCB42023;
010F : FCC42223;
0110 : FCD42423;
0111 : 00070793;
0112 : FAF40FA3;
0113 : FE042423;
0114 : 0900006F;
0115 : FC042783;
0116 : 00F7F793;
0117 : FCF42E23;
0118 : FDC42703;
0119 : 00900793;
011A : 02E7C463;
011B : FDC42783;
011C : 0FF7F713;
011D : FE842783;
011E : FCC42683;
011F : 00F687B3;
0120 : 03070713;
0121 : 0FF77713;
0122 : 00E78023;
0123 : 0240006F;
0124 : FDC42783;
0125 : 0FF7F713;
0126 : FE842783;
0127 : FCC42683;
0128 : 00F687B3;
0129 : 05770713;
012A : 0FF77713;
012B : 00E78023;
012C : FC442783;
012D : 01C79793;
012E : FC042703;
012F : 00475813;
0130 : 0107E833;
0131 : FC442783;
0132 : 0047D893;
0133 : FD042023;
0134 : FD142223;
0135 : FE842783;
0136 : 00178793;
0137 : FEF42423;
0138 : FC042783;
0139 : FC442703;
013A : 00E7E7B3;
013B : F60794E3;
013C : 0240006F;
013D : FE842783;
013E : 00178713;
013F : FEE42423;
0140 : 00078713;
0141 : FCC42783;
0142 : 00E787B3;
0143 : FBF44703;
0144 : 00E78023;
0145 : FE842703;
0146 : FC842783;
0147 : FCF74CE3;
0148 : FE042623;
0149 : 06C0006F;
014A : FE842783;
014B : FFF78713;
014C : FEC42783;
014D : 40F707B3;
014E : FEF42223;
014F : FEC42783;
0150 : FCC42703;
0151 : 00F707B3;
0152 : 0007C783;
0153 : FEF401A3;
0154 : FE442783;
0155 : FCC42703;
0156 : 00F70733;
0157 : FEC42783;
0158 : FCC42683;
0159 : 00F687B3;
015A : 00074703;
015B : 00E78023;
015C : FE442783;
015D : FCC42703;
015E : 00F707B3;
015F : FE344703;
0160 : 00E78023;
0161 : FEC42783;
0162 : 00178793;
0163 : FEF42623;
0164 : FE842783;
0165 : 01F7D713;
0166 : 00F707B3;
0167 : 4017D793;
0168 : 00078713;
0169 : FEC42783;
016A : F8E7C0E3;
016B : FE842783;
016C : FCC42703;
016D : 00F707B3;
016E : 00078023;
016F : FE842783;
0170 : 00078513;
0171 : 04C12403;
0172 : 05010113;
0173 : 00008067;
0174 : FD010113;
0175 : 02812623;
0176 : 03010413;
0177 : FCA42E23;
0178 : FCB42C23;
0179 : FE042623;
017A : FE042423;
017B : 00100793;
017C : FEF42223;
017D : 08C0006F;
017E : FDC42783;
017F : 0007C783;
0180 : FEF42023;
0181 : FE042703;
0182 : 02F00793;
0183 : 04E7D263;
0184 : FE042703;
0185 : 03900793;
0186 : 02E7CC63;
0187 : FE842703;
0188 : 00070793;
0189 : 00279793;
018A : 00E787B3;
018B : 00179793;
018C : 00078713;
018D : FE042783;
018E : 00F707B3;
018F : FD078793;
0190 : FEF42423;
0191 : 00100793;
0192 : FEF42623;
0193 : 0280006F;
0194 : FEC42783;
0195 : 02079E63;
0196 : FE042703;
0197 : 02D00793;
0198 : 00F71A63;
0199 : FFF00793;
019A : FEF42223;
019B : 00100793;
019C : FEF42623;
019D : FDC42783;
019E : 00178793;
019F : FCF42E23;
01A0 : FDC42783;
01A1 : 0007C783;
01A2 : F60798E3;
01A3 : 0080006F;
01A4 : 00000013;
01A5 : FE842703;
01A6 : FE442783;
01A7 : 02F707B3;
01A8 : FEF42423;
01A9 : FD842783;
01AA : 00078863;
01AB : FD842783;
01AC : FDC42703;
01AD : 00E7A023;
01AE : FE842783;
01AF : 00078513;
01B0 : 02C12403;
01B1 : 03010113;
01B2 : 00008067;
01B3 : FD010113;
01B4 : 02812623;
01B5 : 03010413;
01B6 : FCA42E23;
01B7 : FCB42C23;
01B8 : FE042623;
01B9 : FE042423;
01BA : 0E00006F;
01BB : FDC42783;
01BC : 0007C783;
01BD : FEF42223;
01BE : FE442703;
01BF : 02F00793;
01C0 : 02E7DA63;
01C1 : FE442703;
01C2 : 03900793;
01C3 : 02E7C463;
01C4 : 00100793;
01C5 : FEF42623;
01C6 : FE842783;
01C7 : 00479713;
01C8 : FE442783;
01C9 : 00F707B3;
01CA : FD078793;
01CB : FEF42423;
01CC : 08C0006F;
01CD : FE442703;
01CE : 06000793;
01CF : 02E7DA63;
01D0 : FE442703;
01D1 : 06600793;
01D2 : 02E7C463;
01D3 : 00100793;
01D4 : FEF42623;
01D5 : FE842783;
01D6 : 00479713;
01D7 : FE442783;
01D8 : 00F707B3;
01D9 : FA978793;
01DA : FEF42423;
01DB : 0500006F;
01DC : FE442703;
01DD : 04000793;
01DE : 02E7DA63;
01DF : FE442703;
01E0 : 04600793;
01E1 : 02E7C463;
01E2 : 00100793;
01E3 : FEF42623;
01E4 : FE842783;
01E5 : 00479713;
01E6 : FE442783;
01E7 : 00F707B3;
01E8 : FC978793;
01E9 : FEF42423;
01EA : 0140006F;
01EB : FEC42783;
01EC : 02079463;
01ED : 00100793;
01EE : FEF42623;
01EF : FDC42783;
01F0 : 00178793;
01F1 : FCF42E23;
01F2 : FDC42783;
01F3 : 0007C783;
01F4 : F0079EE3;
01F5 : 0080006F;
01F6 : 00000013;
01F7 : FD842783;
01F8 : 00078863;
01F9 : FD842783;
01FA : FDC42703;
01FB : 00E7A023;
01FC : FE842783;
01FD : 00078513;
01FE : 02C12403;
01FF : 03010113;
0200 : 00008067;
0201 : FB010113;
0202 : 04112623;
0203 : 04812423;
0204 : 05212223;
0205 : 05312023;
0206 : 03412E23;
0207 : 03512C23;
0208 : 05010413;
0209 : 000017B7;
020A : EE87A783;
020B : FF07F793;
020C : FCF42A23;
020D : FC042C23;
020E : 1BC0006F;
020F : FD442783;
0210 : 00078913;
0211 : 00000993;
0212 : FBC40793;
0213 : 03000713;
0214 : 00800693;
0215 : 00090593;
0216 : 00098613;
0217 : 00078513;
0218 : BC9FF0EF;
0219 : FBC40793;
021A : 00078513;
021B : 8F9FF0EF;
021C : 000017B7;
021D : E4878513;
021E : 8EDFF0EF;
021F : FC042E23;
0220 : 0A40006F;
0221 : FD442783;
0222 : FCF42623;
0223 : FDC42703;
0224 : FD442783;
0225 : 00F70733;
0226 : 000017B7;
0227 : EE87A783;
0228 : 00F77A63;
0229 : 000017B7;
022A : E4C78513;
022B : 8B9FF0EF;
022C : 0500006F;
022D : FDC42783;
022E : FCC42703;
022F : 00F707B3;
0230 : 0007C783;
0231 : 00078A13;
0232 : 00000A93;
0233 : FBC40793;
0234 : 03000713;
0235 : 00200693;
0236 : 000A0593;
0237 : 000A8613;
0238 : 00078513;
0239 : B45FF0EF;
023A : FBC40793;
023B : 00078513;
023C : 875FF0EF;
023D : 000017B7;
023E : E5078513;
023F : 869FF0EF;
0240 : FDC42703;
0241 : 00700793;
0242 : 00F71863;
0243 : 000017B7;
0244 : E5478513;
0245 : 851FF0EF;
0246 : FDC42783;
0247 : 00178793;
0248 : FCF42E23;
0249 : FDC42703;
024A : 00F00793;
024B : F4E7DCE3;
024C : 000017B7;
024D : E5878513;
024E : 82DFF0EF;
024F : FC042E23;
0250 : 0780006F;
0251 : FD442783;
0252 : FCF42823;
0253 : FDC42783;
0254 : FD042703;
0255 : 00F707B3;
0256 : 0007C703;
0257 : 01F00793;
0258 : 02E7FA63;
0259 : FDC42783;
025A : FD042703;
025B : 00F707B3;
025C : 0007C703;
025D : 07E00793;
025E : 00E7EE63;
025F : FDC42783;
0260 : FD042703;
0261 : 00F707B3;
0262 : 0007C783;
0263 : FAF40E23;
0264 : 00C0006F;
0265 : 02E00793;
0266 : FAF40E23;
0267 : FA040EA3;
0268 : FBC40793;
0269 : 00078513;
026A : FBCFF0EF;
026B : FDC42783;
026C : 00178793;
026D : FCF42E23;
026E : FDC42703;
026F : 00F00793;
0270 : F8E7D2E3;
0271 : 000017B7;
0272 : E5C78513;
0273 : F98FF0EF;
0274 : FD442783;
0275 : 01078793;
0276 : FCF42A23;
0277 : FD442783;
0278 : 0FF7F793;
0279 : 02078063;
027A : FD842783;
027B : 00178793;
027C : FCF42C23;
027D : FD842703;
027E : 00F00793;
027F : E4E7D0E3;
0280 : 0080006F;
0281 : 00000013;
0282 : 000017B7;
0283 : E6078513;
0284 : F54FF0EF;
0285 : 000017B7;
0286 : FD442703;
0287 : EEE7A423;
0288 : 00000013;
0289 : 04C12083;
028A : 04812403;
028B : 04412903;
028C : 04012983;
028D : 03C12A03;
028E : 03812A83;
028F : 05010113;
0290 : 00008067;
0291 : FF010113;
0292 : 00112623;
0293 : 00812423;
0294 : 01010413;
0295 : 000017B7;
0296 : E6478513;
0297 : F08FF0EF;
0298 : 000017B7;
0299 : E7478513;
029A : EFCFF0EF;
029B : 000017B7;
029C : E8878513;
029D : EF0FF0EF;
029E : 000017B7;
029F : E9C78513;
02A0 : EE4FF0EF;
02A1 : 00000013;
02A2 : 00C12083;
02A3 : 00812403;
02A4 : 01010113;
02A5 : 00008067;
02A6 : F8010113;
02A7 : 06112E23;
02A8 : 06812C23;
02A9 : 07212A23;
02AA : 07312823;
02AB : 07412623;
02AC : 07512423;
02AD : 08010413;
02AE : F8A42623;
02AF : F8B42423;
02B0 : F00007B7;
02B1 : 01078793;
02B2 : 3F3F0737;
02B3 : 70770713;
02B4 : 00E7A023;
02B5 : 000017B7;
02B6 : EE47A783;
02B7 : 01078793;
02B8 : 1B200713;
02B9 : 00E7A023;
02BA : D24FF0EF;
02BB : 00050793;
02BC : 00078863;
02BD : 000017B7;
02BE : EB878513;
02BF : E68FF0EF;
02C0 : D54FF0EF;
02C1 : 00050793;
02C2 : FE078CE3;
02C3 : F9040793;
02C4 : 02700593;
02C5 : 00078513;
02C6 : EB4FF0EF;
02C7 : 00000013;
02C8 : 000017B7;
02C9 : EBC78513;
02CA : E3CFF0EF;
02CB : F9040793;
02CC : 00078513;
02CD : E30FF0EF;
02CE : 000017B7;
02CF : E6078513;
02D0 : E24FF0EF;
02D1 : F9044703;
02D2 : 06200793;
02D3 : 04F71863;
02D4 : F9040793;
02D5 : 00278793;
02D6 : 00000593;
02D7 : 00078513;
02D8 : A71FF0EF;
02D9 : FCA42023;
02DA : FC042783;
02DB : 02F05463;
02DC : 02FAF7B7;
02DD : 08078713;
02DE : FC042783;
02DF : 02F74733;
02E0 : 000017B7;
02E1 : EE47A783;
02E2 : 01078793;
02E3 : 00E7A023;
02E4 : 2A40006F;
02E5 : EB1FF0EF;
02E6 : 29C0006F;
02E7 : F9044703;
02E8 : 06400793;
02E9 : 02F71C63;
02EA : F9040793;
02EB : 00278793;
02EC : 00000593;
02ED : 00078513;
02EE : B15FF0EF;
02EF : FCA42223;
02F0 : FC442783;
02F1 : 00F05863;
02F2 : FC442703;
02F3 : 000017B7;
02F4 : EEE7A423;
02F5 : C31FF0EF;
02F6 : 25C0006F;
02F7 : F9044703;
02F8 : 07700793;
02F9 : 0AF71C63;
02FA : F9040793;
02FB : 00278793;
02FC : FBC40713;
02FD : 00070593;
02FE : 00078513;
02FF : AD1FF0EF;
0300 : FCA42823;
0301 : FBC42783;
0302 : FBC40713;
0303 : 00070593;
0304 : 00078513;
0305 : AB9FF0EF;
0306 : FCA42623;
0307 : FBC42783;
0308 : FBC40713;
0309 : 00070593;
030A : 00078513;
030B : AA1FF0EF;
030C : FCA42423;
030D : FC842703;
030E : 00100793;
030F : 00F71C63;
0310 : FD042783;
0311 : FCC42703;
0312 : 0FF77713;
0313 : 00E78023;
0314 : 1E40006F;
0315 : FC842703;
0316 : 00200793;
0317 : 00F71E63;
0318 : FD042783;
0319 : FCC42703;
031A : 01071713;
031B : 41075713;
031C : 00E79023;
031D : 1C00006F;
031E : FC842703;
031F : 00400793;
0320 : 00F71A63;
0321 : FD042783;
0322 : FCC42703;
0323 : 00E7A023;
0324 : 1A40006F;
0325 : DB1FF0EF;
0326 : 19C0006F;
0327 : F9044703;
0328 : 07200793;
0329 : 18F71863;
032A : FC042E23;
032B : F9040793;
032C : 00278793;
032D : FB840713;
032E : 00070593;
032F : 00078513;
0330 : A0DFF0EF;
0331 : FCA42C23;
0332 : FB842783;
0333 : FB840713;
0334 : 00070593;
0335 : 00078513;
0336 : 9F5FF0EF;
0337 : FCA42A23;
0338 : FD442703;
0339 : 00100793;
033A : 02F71063;
033B : FD842783;
033C : 0007C783;
033D : FCF42E23;
033E : 000017B7;
033F : EC078513;
0340 : C64FF0EF;
0341 : 0580006F;
0342 : FD442703;
0343 : 00200793;
0344 : 02F71063;
0345 : FD842783;
0346 : 00079783;
0347 : FCF42E23;
0348 : 000017B7;
0349 : EC878513;
034A : C3CFF0EF;
034B : 0300006F;
034C : FD442703;
034D : 00400793;
034E : 02F71063;
034F : FD842783;
0350 : 0007A783;
0351 : FCF42E23;
0352 : 000017B7;
0353 : ED078513;
0354 : C14FF0EF;
0355 : 0080006F;
0356 : CEDFF0EF;
0357 : FD442703;
0358 : 00100793;
0359 : 00F70E63;
035A : FD442703;
035B : 00200793;
035C : 00F70863;
035D : FD442703;
035E : 00400793;
035F : 0AF71C63;
0360 : FD842783;
0361 : 00078913;
0362 : 41F7D793;
0363 : 00078993;
0364 : F9040793;
0365 : 03000713;
0366 : 00800693;
0367 : 00090593;
0368 : 00098613;
0369 : 00078513;
036A : E80FF0EF;
036B : F9040793;
036C : 00078513;
036D : BB0FF0EF;
036E : 000017B7;
036F : ED878513;
0370 : BA4FF0EF;
0371 : F9040793;
0372 : FDC42583;
0373 : 00078513;
0374 : CD4FF0EF;
0375 : F9040793;
0376 : 00078513;
0377 : B88FF0EF;
0378 : 000017B7;
0379 : EDC78513;
037A : B7CFF0EF;
037B : FDC42783;
037C : 00078A13;
037D : 41F7D793;
037E : 00078A93;
037F : FD442783;
0380 : 00179693;
0381 : F9040793;
0382 : 03000713;
0383 : 000A0593;
0384 : 000A8613;
0385 : 00078513;
0386 : E10FF0EF;
0387 : F9040793;
0388 : 00078513;
0389 : B40FF0EF;
038A : 000017B7;
038B : EE078513;
038C : B34FF0EF;
038D : 00000013;
038E : 9D4FF0EF;
038F : 00050793;
0390 : FE078CE3;
0391 : CA5FF06F;
0392 : 00002020;
0393 : 00202020;
0394 : 00000020;
0395 : 0000202D;
0396 : 007C2020;
0397 : 00000A7C;
0398 : 00000D0A;
0399 : 20642020;
039A : 6464613C;
039B : 0A203E72;
039C : 00000000;
039D : 20622020;
039E : 7561623C;
039F : 74617264;
03A0 : 0A203E65;
03A1 : 00000000;
03A2 : 20722020;
03A3 : 6464613C;
03A4 : 3C203E72;
03A5 : 74646977;
03A6 : 000A3E68;
03A7 : 20772020;
03A8 : 6464613C;
03A9 : 3C203E72;
03AA : 756C6176;
03AB : 3C203E65;
03AC : 74646977;
03AD : 000A3E68;
03AE : 00003E3E;
03AF : 003A0D0A;
03B0 : 72616863;
03B1 : 00004020;
03B2 : 726F6873;
03B3 : 00402074;
03B4 : 20746E69;
03B5 : 00000040;
03B6 : 00203D20;
03B7 : 00000028;
03B8 : 000D0A29;
03B9 : F0000100;
03BA : 00000001;
03BB : 00000001;
03BC : CDCDCDCD;
03BD : CDCDCDCD;
03BE : CDCDCDCD;
03BF : CDCDCDCD;
03C0 : CDCDCDCD;
03C1 : CDCDCDCD;
03C2 : CDCDCDCD;
03C3 : CDCDCDCD;
03C4 : CDCDCDCD;
03C5 : CDCDCDCD;
03C6 : CDCDCDCD;
03C7 : CDCDCDCD;
03C8 : CDCDCDCD;
03C9 : CDCDCDCD;
03CA : CDCDCDCD;
03CB : CDCDCDCD;
03CC : CDCDCDCD;
03CD : CDCDCDCD;
03CE : CDCDCDCD;
03CF : CDCDCDCD;
03D0 : CDCDCDCD;
03D1 : CDCDCDCD;
03D2 : CDCDCDCD;
03D3 : CDCDCDCD;
03D4 : CDCDCDCD;
03D5 : CDCDCDCD;
03D6 : CDCDCDCD;
03D7 : CDCDCDCD;
03D8 : CDCDCDCD;
03D9 : CDCDCDCD;
03DA : CDCDCDCD;
03DB : CDCDCDCD;
03DC : CDCDCDCD;
03DD : CDCDCDCD;
03DE : CDCDCDCD;
03DF : CDCDCDCD;
03E0 : CDCDCDCD;
03E1 : CDCDCDCD;
03E2 : CDCDCDCD;
03E3 : CDCDCDCD;
03E4 : CDCDCDCD;
03E5 : CDCDCDCD;
03E6 : CDCDCDCD;
03E7 : CDCDCDCD;
03E8 : CDCDCDCD;
03E9 : CDCDCDCD;
03EA : CDCDCDCD;
03EB : CDCDCDCD;
03EC : CDCDCDCD;
03ED : CDCDCDCD;
03EE : CDCDCDCD;
03EF : CDCDCDCD;
03F0 : CDCDCDCD;
03F1 : CDCDCDCD;
03F2 : CDCDCDCD;
03F3 : CDCDCDCD;
03F4 : CDCDCDCD;
03F5 : CDCDCDCD;
03F6 : CDCDCDCD;
03F7 : CDCDCDCD;
03F8 : CDCDCDCD;
03F9 : CDCDCDCD;
03FA : CDCDCDCD;
03FB : CDCDCDCD;
03FC : CDCDCDCD;
03FD : CDCDCDCD;
03FE : CDCDCDCD;
03FF : CDCDCDCD;
END;
examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/gui_handlers.wdf 0 → 100644
浏览文件 @ 7c4b6d68
version:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
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examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/java_command_handlers.wdf 0 → 100644
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version:1
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examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/project.wpc 0 → 100644
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examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis.wdf 0 → 100644
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version:1
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examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/synthesis_details.wdf 0 → 100644
浏览文件 @ 7c4b6d68
version:1
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examples/hdl4se_riscv/z7/project_2/project_2.cache/wt/webtalk_pa.xml 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Sep 7 21:21:21 2021">
<section name="Project Information" visible="false">
<property name="ProjectID" value="a743487f8c054e19bd0c70665a8528bf" type="ProjectID"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="CreateBlockDesign" value="1" type="JavaHandler"/>
<property name="ExitApp" value="1" type="JavaHandler"/>
<property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="1" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="2" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="5" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="5" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
<property name="NewIpWizard_CREATE_NEW_AXI4_IP_CREATE_AXI4" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SYNTH_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_CUSTOM_COMMANDS" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="1" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="1" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
</item>
</section>
</application>
</document>
examples/hdl4se_riscv/z7/project_2/project_2.hw/project_2.lpr 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_1.xml 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
examples/hdl4se_riscv/z7/project_2/project_2.runs/.jobs/vrs_config_2.xml 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.init_design.begin.rst 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="15884">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.opt_design.begin.rst 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="15884">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.phys_opt_design.begin.rst 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="15884">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.place_design.begin.rst 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="15884">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.route_design.begin.rst 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="15884">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/.vivado.begin.rst 0 → 100644
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="9068" HostCore="20" HostMemory="034090057728">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.js 0 → 100644
浏览文件 @ 7c4b6d68
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/ISEWrap.sh 0 → 100644
浏览文件 @ 7c4b6d68
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/gen_run.xml 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k70tfbv484-1" LaunchTime="1631018123">
<File Type="ROUTE-PWR" Name="riscv_core_power_routed.rpt"/>
<File Type="PA-TCL" Name="riscv_core.tcl"/>
<File Type="BITSTR-MMI" Name="riscv_core.mmi"/>
<File Type="OPT-METHODOLOGY-DRC" Name="riscv_core_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="riscv_core_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR-SUM" Name="riscv_core_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="riscv_core_reports.tcl"/>
<File Type="OPT-TIMING" Name="riscv_core_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="riscv_core_opt.dcp"/>
<File Type="OPT-DRC" Name="riscv_core_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="riscv_core.hwdef"/>
<File Type="PWROPT-DCP" Name="riscv_core_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="riscv_core_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="riscv_core_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="riscv_core_placed.dcp"/>
<File Type="PLACE-IO" Name="riscv_core_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="riscv_core_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="riscv_core_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="riscv_core_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="riscv_core_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="riscv_core_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="riscv_core_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BIN" Name="riscv_core.bin"/>
<File Type="PLACE-TIMING" Name="riscv_core_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="riscv_core_postplace_pwropt.dcp"/>
<File Type="BITSTR-MSK" Name="riscv_core.msk"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="riscv_core_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="riscv_core_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="riscv_core_drc_physopted.rpt"/>
<File Type="BITSTR-RBT" Name="riscv_core.rbt"/>
<File Type="PHYSOPT-TIMING" Name="riscv_core_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="riscv_core_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="riscv_core_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="riscv_core_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="riscv_core_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="riscv_core_drc_routed.pb"/>
<File Type="ROUTE-DRC-RPX" Name="riscv_core_drc_routed.rpx"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="riscv_core_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="riscv_core_methodology_drc_routed.rpx"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="riscv_core_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="riscv_core_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="riscv_core_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="riscv_core_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="riscv_core_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="riscv_core_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="riscv_core_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="riscv_core_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="riscv_core_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="riscv_core_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="riscv_core_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="riscv_core_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="riscv_core_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="riscv_core_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="riscv_core_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="riscv_core_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="riscv_core_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="riscv_core_bus_skew_postroute_physopted.rpt"/>
<File Type="BG-BIT" Name="riscv_core.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="riscv_core_bus_skew_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="riscv_core_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-NKY" Name="riscv_core.nky"/>
<File Type="BITSTR-BMM" Name="riscv_core_bd.bmm"/>
<File Type="PDI-FILE" Name="riscv_core.pdi"/>
<File Type="RCFI_FILE" Name="riscv_core.rcfi"/>
<File Type="CFI_FILE" Name="riscv_core.cfi"/>
<File Type="RNPI_FILE" Name="riscv_core.rnpi"/>
<File Type="NPI_FILE" Name="riscv_core.npi"/>
<File Type="RBD_FILE" Name="riscv_core.rbd"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="riscv_core.ltx"/>
<File Type="BITSTR-SYSDEF" Name="riscv_core.sysdef"/>
<File Type="BG-BGN" Name="riscv_core.bgn"/>
<File Type="BG-DRC" Name="riscv_core.drc"/>
<File Type="RDI-RDI" Name="riscv_core.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../verilog/alu/div32.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../verilog/alu/mul32.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../verilog/riscv_core_v4.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../verilog/altera/uart/altera_uart.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../verilog/uart/uart_ctrl.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="riscv_core"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/htr.txt 0 → 100644
浏览文件 @ 7c4b6d68
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
REM
vivado -log riscv_core.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/project.wdf 0 → 100644
浏览文件 @ 7c4b6d68
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3764356431346564313833653430343962656265633534323531626437333330:506172656e742050412070726f6a656374204944:00
eof:254497829
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.tcl 0 → 100644
浏览文件 @ 7c4b6d68
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
namespace eval ::optrace {
variable script "D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.tcl"
variable category "vivado_impl"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
} elseif { [info exist ::env(HOST)] } {
set host $::env(HOST)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
OPTRACE "impl_1" END { }
}
OPTRACE "impl_1" START { ROLLUP_1 }
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param chipscope.maxJobs 5
OPTRACE "create in-memory project" START { }
create_project -in_memory -part xc7k70tfbv484-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
OPTRACE "create in-memory project" END { }
OPTRACE "set parameters" START { }
set_property webtalk.parent_dir D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.cache/wt [current_project]
set_property parent.project_path D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.xpr [current_project]
set_property ip_output_repo D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "set parameters" END { }
OPTRACE "add files" START { }
add_files -quiet D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp
OPTRACE "read constraints: implementation" START { }
OPTRACE "read constraints: implementation" END { }
OPTRACE "add files" END { }
OPTRACE "link_design" START { }
link_design -top riscv_core -part xc7k70tfbv484-1
OPTRACE "link_design" END { }
OPTRACE "gray box cells" START { }
OPTRACE "gray box cells" END { }
OPTRACE "init_design_reports" START { REPORT }
OPTRACE "init_design_reports" END { }
OPTRACE "init_design_write_hwdef" START { }
OPTRACE "init_design_write_hwdef" END { }
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
OPTRACE "Phase: Init Design" END { }
OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
OPTRACE "read constraints: opt_design" START { }
OPTRACE "read constraints: opt_design" END { }
OPTRACE "opt_design" START { }
opt_design
OPTRACE "opt_design" END { }
OPTRACE "read constraints: opt_design_post" START { }
OPTRACE "read constraints: opt_design_post" END { }
OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
write_checkpoint -force riscv_core_opt.dcp
OPTRACE "Opt Design: write_checkpoint" END { }
OPTRACE "opt_design reports" START { REPORT }
create_report "impl_1_opt_report_drc_0" "report_drc -file riscv_core_drc_opted.rpt -pb riscv_core_drc_opted.pb -rpx riscv_core_drc_opted.rpx"
OPTRACE "opt_design reports" END { }
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
OPTRACE "Phase: Opt Design" END { }
OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
OPTRACE "read constraints: place_design" START { }
OPTRACE "read constraints: place_design" END { }
if { [llength [get_debug_cores -quiet] ] > 0 } {
OPTRACE "implement_debug_core" START { }
implement_debug_core
OPTRACE "implement_debug_core" END { }
}
OPTRACE "place_design" START { }
place_design
OPTRACE "place_design" END { }
OPTRACE "read constraints: place_design_post" START { }
OPTRACE "read constraints: place_design_post" END { }
OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
write_checkpoint -force riscv_core_placed.dcp
OPTRACE "Place Design: write_checkpoint" END { }
OPTRACE "place_design reports" START { REPORT }
create_report "impl_1_place_report_io_0" "report_io -file riscv_core_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file riscv_core_utilization_placed.rpt -pb riscv_core_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file riscv_core_control_sets_placed.rpt"
OPTRACE "place_design reports" END { }
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
OPTRACE "Phase: Place Design" END { }
OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
start_step phys_opt_design
set ACTIVE_STEP phys_opt_design
set rc [catch {
create_msg_db phys_opt_design.pb
OPTRACE "read constraints: phys_opt_design" START { }
OPTRACE "read constraints: phys_opt_design" END { }
OPTRACE "phys_opt_design" START { }
phys_opt_design
OPTRACE "phys_opt_design" END { }
OPTRACE "read constraints: phys_opt_design_post" START { }
OPTRACE "read constraints: phys_opt_design_post" END { }
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
write_checkpoint -force riscv_core_physopt.dcp
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
OPTRACE "phys_opt_design report" START { REPORT }
OPTRACE "phys_opt_design report" END { }
close_msg_db -file phys_opt_design.pb
} RESULT]
if {$rc} {
step_failed phys_opt_design
return -code error $RESULT
} else {
end_step phys_opt_design
unset ACTIVE_STEP
}
OPTRACE "Phase: Physical Opt Design" END { }
OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
OPTRACE "read constraints: route_design" START { }
OPTRACE "read constraints: route_design" END { }
OPTRACE "route_design" START { }
route_design
OPTRACE "route_design" END { }
OPTRACE "read constraints: route_design_post" START { }
OPTRACE "read constraints: route_design_post" END { }
OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
write_checkpoint -force riscv_core_routed.dcp
OPTRACE "Route Design: write_checkpoint" END { }
OPTRACE "route_design reports" START { REPORT }
create_report "impl_1_route_report_drc_0" "report_drc -file riscv_core_drc_routed.rpt -pb riscv_core_drc_routed.pb -rpx riscv_core_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file riscv_core_methodology_drc_routed.rpt -pb riscv_core_methodology_drc_routed.pb -rpx riscv_core_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file riscv_core_power_routed.rpt -pb riscv_core_power_summary_routed.pb -rpx riscv_core_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file riscv_core_route_status.rpt -pb riscv_core_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file riscv_core_timing_summary_routed.rpt -pb riscv_core_timing_summary_routed.pb -rpx riscv_core_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file riscv_core_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file riscv_core_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file riscv_core_bus_skew_routed.rpt -pb riscv_core_bus_skew_routed.pb -rpx riscv_core_bus_skew_routed.rpx"
OPTRACE "route_design reports" END { }
OPTRACE "route_design misc" START { }
close_msg_db -file route_design.pb
OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
OPTRACE "route_design write_checkpoint" END { }
} RESULT]
if {$rc} {
write_checkpoint -force riscv_core_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
OPTRACE "route_design misc" END { }
OPTRACE "Phase: Route Design" END { }
OPTRACE "impl_1" END { }
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_bus_skew_routed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:36:12 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file riscv_core_bus_skew_routed.rpt -pb riscv_core_bus_skew_routed.pb -rpx riscv_core_bus_skew_routed.rpx
| Design : riscv_core
| Device : 7k70t-fbv484
| Speed File : -1 PRODUCTION 1.12 2017-02-17
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_clock_utilization_routed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:36:12 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_clock_utilization -file riscv_core_clock_utilization_routed.rpt
| Design : riscv_core
| Device : 7k70t-fbv484
| Speed File : -1 PRODUCTION 1.12 2017-02-17
| Design State : Routed
----------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y0
8. Clock Region Cell Placement per Global Clock: Region X0Y1
9. Clock Region Cell Placement per Global Clock: Region X0Y2
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 96 | 0 | 0 | 0 |
| BUFIO | 0 | 24 | 0 | 0 | 0 |
| BUFMR | 0 | 12 | 0 | 0 | 0 |
| BUFR | 0 | 24 | 0 | 0 | 0 |
| MMCM | 0 | 6 | 0 | 0 | 0 |
| PLL | 0 | 6 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 3 | 600 | 0 | | | wClk_IBUF_BUFG_inst/O | wClk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+
| src0 | g0 | IBUF/O | None | IOB_X0Y178 | X0Y3 | 1 | 0 | | | wClk_IBUF_inst/O | wClk_IBUF |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+------------------+-----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 125 | 1800 | 57 | 500 | 0 | 40 | 0 | 20 | 0 | 40 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1300 | 0 | 400 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 468 | 1200 | 202 | 500 | 0 | 40 | 0 | 20 | 0 | 40 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1300 | 0 | 400 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 7 | 1200 | 0 | 500 | 0 | 40 | 0 | 20 | 0 | 40 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 750 | 0 | 250 | 0 | 10 | 0 | 5 | 0 | 20 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 500 | 0 | 40 | 0 | 20 | 0 | 40 |
| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 900 | 0 | 300 | 0 | 20 | 0 | 10 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y3 | 0 | 0 |
| Y2 | 1 | 0 |
| Y1 | 1 | 0 |
| Y0 | 1 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+
| g0 | BUFG/O | n/a | | | | 600 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+----+-----------------------+
| | X0 | X1 | HORIZONTAL PROG DELAY |
+----+------+----+-----------------------+
| Y3 | 0 | 0 | 0 |
| Y2 | 7 | 0 | 0 |
| Y1 | 468 | 0 | 0 |
| Y0 | 125 | 0 | 0 |
+----+------+----+-----------------------+
7. Clock Region Cell Placement per Global Clock: Region X0Y0
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| g0 | n/a | BUFG/O | None | 125 | 0 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
8. Clock Region Cell Placement per Global Clock: Region X0Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
| g0 | n/a | BUFG/O | None | 468 | 0 | 468 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
9. Clock Region Cell Placement per Global Clock: Region X0Y2
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------+
| g0 | n/a | BUFG/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | wClk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y16 [get_cells wClk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y178 [get_ports wClk]
# Clock net "wClk_IBUF_BUFG" driven by instance "wClk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock {CLKAG_wClk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_wClk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="wClk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_wClk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}
#endgroup
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_control_sets_placed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:35:58 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file riscv_core_control_sets_placed.rpt
| Design : riscv_core
| Device : xc7k70t
---------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Total control sets | 22 |
| Minimum number of control sets | 22 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 48 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
2. Histogram
------------
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
| Total control sets | 22 |
| >= 0 to < 4 | 2 |
| >= 4 to < 6 | 1 |
| >= 6 to < 8 | 2 |
| >= 8 to < 10 | 1 |
| >= 10 to < 12 | 0 |
| >= 12 to < 14 | 0 |
| >= 14 to < 16 | 0 |
| >= 16 | 16 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 1 | 1 |
| Yes | No | No | 349 | 171 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 250 | 117 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+-----------------+-------------------------+---------------------------------+------------------+----------------+--------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
+-----------------+-------------------------+---------------------------------+------------------+----------------+--------------+
| wClk_IBUF_BUFG | | FSM_sequential_state[3]_i_1_n_0 | 1 | 1 | 1.00 |
| wClk_IBUF_BUFG | writedata[31]_i_1_n_0 | writemask[3]_i_1_n_0 | 1 | 1 | 1.00 |
| wClk_IBUF_BUFG | mul/E[0] | FSM_sequential_state[3]_i_1_n_0 | 2 | 5 | 2.50 |
| wClk_IBUF_BUFG | div/count[5]_i_1_n_0 | mul/wStart0 | 2 | 6 | 3.00 |
| wClk_IBUF_BUFG | imm | imm[10]_i_1_n_0 | 2 | 6 | 3.00 |
| wClk_IBUF_BUFG | lastv | lastv[31]_i_1_n_0 | 5 | 8 | 1.60 |
| wClk_IBUF_BUFG | lastv | | 17 | 24 | 1.41 |
| wClk_IBUF_BUFG | imm | | 16 | 26 | 1.62 |
| wClk_IBUF_BUFG | writeaddr[31]_i_1_n_0 | | 9 | 30 | 3.33 |
| wClk_IBUF_BUFG | mul/wStart0 | FSM_sequential_state[3]_i_1_n_0 | 25 | 32 | 1.28 |
| wClk_IBUF_BUFG | mul/bbuf | mul/abuf[63]_i_1_n_0 | 10 | 32 | 3.20 |
| wClk_IBUF_BUFG | div/abuf[31]_i_1__0_n_0 | | 22 | 32 | 1.45 |
| wClk_IBUF_BUFG | div/abuf[31]_i_1__0_n_0 | mul/wStart0 | 9 | 32 | 3.56 |
| wClk_IBUF_BUFG | csr_r | csr_r[31]_i_1_n_0 | 20 | 32 | 1.60 |
| wClk_IBUF_BUFG | lastaddr | | 15 | 32 | 2.13 |
| wClk_IBUF_BUFG | misa | FSM_sequential_state[3]_i_1_n_0 | 25 | 32 | 1.28 |
| wClk_IBUF_BUFG | csr_r | | 16 | 34 | 2.12 |
| wClk_IBUF_BUFG | mul/wStart0 | | 21 | 35 | 1.67 |
| wClk_IBUF_BUFG | writedata[31]_i_1_n_0 | | 18 | 35 | 1.94 |
| wClk_IBUF_BUFG | ldaddr[31]_i_1_n_0 | | 12 | 37 | 3.08 |
| wClk_IBUF_BUFG | mul/result | mul/wStart0 | 16 | 64 | 4.00 |
| wClk_IBUF_BUFG | mul/bbuf | | 25 | 64 | 2.56 |
+-----------------+-------------------------+---------------------------------+------------------+----------------+--------------+
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_opted.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:35:51 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_drc -file riscv_core_drc_opted.rpt -pb riscv_core_drc_opted.pb -rpx riscv_core_drc_opted.rpx
| Design : riscv_core
| Device : xc7k70tfbv484-1
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
284 out of 284 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0],
bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0],
regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0],
regwrdata[31:0], regwren (the first 15 of 19 listed).
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
284 out of 284 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0],
bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0],
regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0],
regwrdata[31:0], regwren (the first 15 of 19 listed).
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_drc_routed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:36:09 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_drc -file riscv_core_drc_routed.rpt -pb riscv_core_drc_routed.pb -rpx riscv_core_drc_routed.rpx
| Design : riscv_core
| Device : xc7k70tfbv484-1
| Speed File : -1
| Design State : Fully Routed
------------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
284 out of 284 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0],
bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0],
regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0],
regwrdata[31:0], regwren (the first 15 of 19 listed).
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
284 out of 284 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: bReadAddr[31:0], bReadData[31:0], bWriteAddr[31:0], bWriteData[31:0],
bWriteMask[3:0], nwReset, regena2[3:0], regena[3:0], regno2[4:0],
regno[4:0], regrddata2[31:0], regrddata[31:0], regwrdata2[31:0],
regwrdata[31:0], regwren (the first 15 of 19 listed).
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_power_routed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:36:11 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_power -file riscv_core_power_routed.rpt -pb riscv_core_power_summary_routed.pb -rpx riscv_core_power_routed.rpx
| Design : riscv_core
| Device : xc7k70tfbv484-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+----------------------------------+
| Total On-Chip Power (W) | 79.599 (Junction temp exceeded!) |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 78.569 |
| Device Static (W) | 1.029 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 0.0 |
| Junction Temperature (C) | 125.0 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+----------------------------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 10.889 | 3279 | --- | --- |
| LUT as Logic | 10.003 | 2121 | 41000 | 5.17 |
| CARRY4 | 0.624 | 166 | 10250 | 1.62 |
| Register | 0.255 | 600 | 82000 | 0.73 |
| BUFG | 0.006 | 1 | 32 | 3.13 |
| F7/F8 Muxes | <0.001 | 3 | 41000 | <0.01 |
| Others | 0.000 | 5 | --- | --- |
| Signals | 13.775 | 2697 | --- | --- |
| I/O | 53.905 | 284 | 285 | 99.65 |
| Static Power | 1.029 | | | |
| Total | 79.599 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 25.927 | 25.053 | 0.874 | NA | Unspecified | NA |
| Vccaux | 1.800 | 4.424 | 4.373 | 0.051 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco18 | 1.800 | 25.359 | 25.358 | 0.001 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.025 | 0.000 | 0.025 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 2.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.2 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+------------+-----------+
| Name | Power (W) |
+------------+-----------+
| riscv_core | 78.569 |
| div | 5.037 |
| mul | 5.937 |
+------------+-----------+
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_route_status.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 4147 :
# of nets not needing routing.......... : 1448 :
# of internally routed nets........ : 1448 :
# of routable nets..................... : 2699 :
# of fully routed nets............. : 2699 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.pb 0 → 100644
浏览文件 @ 7c4b6d68
2012.4)Timing analysis from Implemented netlist.
\ No newline at end of file
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_timing_summary_routed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:36:11 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file riscv_core_timing_summary_routed.rpt -pb riscv_core_timing_summary_routed.pb -rpx riscv_core_timing_summary_routed.rpx -warn_on_violation
| Design : riscv_core
| Device : 7k70t-fbv484
| Speed File : -1 PRODUCTION 1.12 2017-02-17
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
Rule Severity Description Violations
--------- ---------------- --------------------------- ----------
TIMING-17 Critical Warning Non-clocked sequential cell 600
Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
check_timing report
Table of Contents
-----------------
1. checking no_clock (600)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (1450)
5. checking no_input_delay (95)
6. checking no_output_delay (184)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (600)
--------------------------
There are 600 register/latch pins with no clock driven by root clock pin: wClk (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (1450)
---------------------------------------------------
There are 1450 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (95)
-------------------------------
There are 95 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (184)
---------------------------------
There are 184 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core_utilization_placed.rpt 0 → 100644
浏览文件 @ 7c4b6d68
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date : Tue Sep 7 20:35:58 2021
| Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
| Command : report_utilization -file riscv_core_utilization_placed.rpt -pb riscv_core_utilization_placed.pb
| Design : riscv_core
| Device : 7k70tfbv484-1
| Design State : Fully Placed
-----------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs | 2121 | 0 | 0 | 41000 | 5.17 |
| LUT as Logic | 2121 | 0 | 0 | 41000 | 5.17 |
| LUT as Memory | 0 | 0 | 0 | 13400 | 0.00 |
| Slice Registers | 600 | 0 | 0 | 82000 | 0.73 |
| Register as Flip Flop | 600 | 0 | 0 | 82000 | 0.73 |
| Register as Latch | 0 | 0 | 0 | 82000 | 0.00 |
| F7 Muxes | 3 | 0 | 0 | 20500 | 0.01 |
| F8 Muxes | 0 | 0 | 0 | 10250 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 29 | Yes | Set | - |
| 571 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
| Slice | 597 | 0 | 0 | 10250 | 5.82 |
| SLICEL | 347 | 0 | | | |
| SLICEM | 250 | 0 | | | |
| LUT as Logic | 2121 | 0 | 0 | 41000 | 5.17 |
| using O5 output only | 0 | | | | |
| using O6 output only | 1738 | | | | |
| using O5 and O6 | 383 | | | | |
| LUT as Memory | 0 | 0 | 0 | 13400 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 600 | 0 | 0 | 82000 | 0.73 |
| Register driven from within the Slice | 475 | | | | |
| Register driven from outside the Slice | 125 | | | | |
| LUT in front of the register is unused | 7 | | | | |
| LUT in front of the register is used | 118 | | | | |
| Unique Control Sets | 22 | | 0 | 10250 | 0.21 |
+--------------------------------------------+------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 240 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 284 | 0 | 0 | 285 | 99.65 |
| IOB Master Pads | 138 | | | | |
| IOB Slave Pads | 136 | | | | |
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
| BUFR | 0 | 0 | 0 | 24 | 0.00 |
+------------+------+-------+------------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 1047 | LUT |
| FDRE | 571 | Flop & Latch |
| LUT4 | 494 | LUT |
| LUT5 | 313 | LUT |
| LUT2 | 242 | LUT |
| LUT3 | 211 | LUT |
| LUT1 | 197 | LUT |
| OBUF | 186 | IO |
| CARRY4 | 166 | CarryLogic |
| IBUF | 98 | IO |
| FDSE | 29 | Flop & Latch |
| MUXF7 | 3 | MuxFx |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/rundef.js 0 → 100644
浏览文件 @ 7c4b6d68
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.1/bin;";
} else {
PathVal = "C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.1/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
// pre-commands:
ISETouchFile( "init_design", "begin" );
ISEStep( "vivado",
"-log riscv_core.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.bat 0 → 100644
浏览文件 @ 7c4b6d68
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/runme.sh 0 → 100644
浏览文件 @ 7c4b6d68
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
echo "This script was generated under a different operating system."
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
exit
if [ -z "$PATH" ]; then
PATH=C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.1/bin
else
PATH=C:/Xilinx/Vivado/2021.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2021.1/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
# pre-commands:
/bin/touch .init_design.begin.rst
EAStep vivado -log riscv_core.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace
examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/vivado.jou 0 → 100644
浏览文件 @ 7c4b6d68
#-----------------------------------------------------------
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Tue Sep 7 20:35:31 2021
# Process ID: 15884
# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1
# Command line: vivado.exe -log riscv_core.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source riscv_core.tcl -notrace
# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1/riscv_core.vdi
# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source riscv_core.tcl -notrace
examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/.vivado.begin.rst 0 → 100644
浏览文件 @ 7c4b6d68
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="raoxi" Host="DESKTOP-I91JIJO" Pid="14576" HostCore="20" HostMemory="034090057728">
</Process>
</ProcessHandle>
examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/ISEWrap.sh 0 → 100644
浏览文件 @ 7c4b6d68
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/htr.txt 0 → 100644
浏览文件 @ 7c4b6d68
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
REM
vivado -log riscv_core.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl
examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/project.wdf 0 → 100644
浏览文件 @ 7c4b6d68
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3764356431346564313833653430343962656265633534323531626437333330:506172656e742050412070726f6a656374204944:00
eof:254497829
examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/runme.bat 0 → 100644
浏览文件 @ 7c4b6d68
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/vivado.jou 0 → 100644
浏览文件 @ 7c4b6d68
#-----------------------------------------------------------
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Tue Sep 7 20:34:47 2021
# Process ID: 4436
# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1
# Command line: vivado.exe -log riscv_core.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl
# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds
# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source riscv_core.tcl -notrace
examples/hdl4se_riscv/z7/project_2/project_2.xpr 0 → 100644
浏览文件 @ 7c4b6d68
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