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提交 9d69d016 编写于 作者: 饶先宏's avatar 饶先宏
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202106122123: 编译器终于能够将俄罗斯方块的verilog代码编译为正确的目标代码了，还差表达式求值部分的代码，可以尝试做计数器这边的网表文件编译。

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bignumber/src/bignumber.c
浏览文件 @ 9d69d016
......@@ -336,14 +336,12 @@ static int bigint_bn_GetStr(HOBJECT object, int base, char* str, int buflen)
i = ((bc + (CELL_WIDTH-1)) / CELL_WIDTH) - 1;
ac = actualwidth(pobj->buf[i]);
ac = (ac + 7) / 8;
sprintf(fmt, "%%%dx_", ac);
sprintf(fmt, "%%%dx", ac);
sprintf(buf, fmt, pobj->buf[i]);
strcat(str, buf);
for (i = ((bc + (CELL_WIDTH-1)) / CELL_WIDTH)-2; i >= 0; i--) {
sprintf(buf, "%08x", pobj->buf[i]);
strcat(str, buf);
if (i > 0)
strcat(str, "_");
}
return 0;
}
......
examples/counter/src/main_gen.c
浏览文件 @ 9d69d016
此差异已折叠。
examples/counter/verilog/main_asm.v
浏览文件 @ 9d69d016
......@@ -104,14 +104,14 @@ hdl4se_const #(WIDTH, RESETVALUE) const_RESETVALUE(bConst_RESETVALUE);
wire wEQ_bCurrentCounter_MAXVALUE;
/* 比较器 bCurrentCounter == MAXVALUE */
hdl4se_binop #(WIDTH, WIDTH, 1, BINOP_EQ)
hdl4se_binop #(WIDTH, WIDTH, 1, `BINOP_EQ)
binop_EQ_bCurrentCounter_MAXVALUE(
wireout_bCurrentCounter,
bConst_MAXVALUE,
wEQ_bCurrentCounter_MAXVALUE
);
hdl4se_binop #(1, 1, 1, BINOP_AND)
hdl4se_binop #(1, 1, 1, `BINOP_AND)
binop_counter_overfloat(
wEQ_bCurrentCounter_MAXVALUE,
wCounterIt,
......@@ -123,7 +123,7 @@ hdl4se_binop #(1, 1, 1, BINOP_AND)
wire [WIDTH-1:0] bConst_One;
wire [WIDTH-1:0] bCurrentCounterPlusOne;
hdl4se_const #(WIDTH, 1) const_One(bConst_One);
hdl4se_binop #(WIDTH, WIDTH, 1, BINOP_ADD)
hdl4se_binop #(WIDTH, WIDTH, 1, `BINOP_ADD)
binop_bCurrentCounterInc(
wireout_bCurrentCounter,
bConst_One,
......@@ -249,15 +249,15 @@ assign wCounterin9 = wCounterin8;
wireout_wCounterIt
);
wire wButton0NotPressed;
hdl4se_unop #(1, 1, UNOP_NOT) Button0NotPressed(wButton0Pressed, wButton0NotPressed);
hdl4se_unop #(1, 1, `UNOP_NOT) Button0NotPressed(wButton0Pressed, wButton0NotPressed);
/*counterit= (~b1) & b2*/
wire wButton1NotPressed;
hdl4se_unop #(1, 1, UNOP_NOT) unop_Button1NotPressed(wButton1Pressed, wButton1NotPressed);
hdl4se_binop #(1, 1, 1, BINOP_AND) binop_counterit(wButton1NotPressed, wButton2Pressed, wirein_wCounterIt);
hdl4se_unop #(1, 1, `UNOP_NOT) unop_Button1NotPressed(wButton1Pressed, wButton1NotPressed);
hdl4se_binop #(1, 1, 1, `BINOP_AND) binop_counterit(wButton1NotPressed, wButton2Pressed, wirein_wCounterIt);
/*assign nwResetCount = (~b0) & nwReset; */
hdl4se_binop #(1, 1, 1, BINOP_AND) binop_resetcounter(wButton0NotPressed, nwReset, nwResetCount);
hdl4se_binop #(1, 1, 1, `BINOP_AND) binop_resetcounter(wButton0NotPressed, nwReset, nwResetCount);
/* 以下是译码器连接，十个计数器的输出对应到十个译码器 */
wire [7:0] code0;
......@@ -286,13 +286,13 @@ dec2seg dec9(bCount9, code9);
wire wCounterin98, wCounterin76, wCounterin54, wCounterin32, wCounterin10,
wCounterin7654, wCounterin3210;
hdl4se_binop #(1, 1, 1, BINOP_OR) or98(wCounterin9, wCounterin8, wCounterin98);
hdl4se_binop #(1, 1, 1, BINOP_OR) or76(wCounterin7, wCounterin6, wCounterin76);
hdl4se_binop #(1, 1, 1, BINOP_OR) or54(wCounterin5, wCounterin4, wCounterin54);
hdl4se_binop #(1, 1, 1, BINOP_OR) or32(wCounterin3, wCounterin2, wCounterin32);
hdl4se_binop #(1, 1, 1, BINOP_OR) or10(wCounterin1, wCounterin0, wCounterin10);
hdl4se_binop #(1, 1, 1, BINOP_OR) or32(wCounterin76, wCounterin54, wCounterin7654);
hdl4se_binop #(1, 1, 1, BINOP_OR) or10(wCounterin32, wCounterin10, wCounterin3210);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or98(wCounterin9, wCounterin8, wCounterin98);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or76(wCounterin7, wCounterin6, wCounterin76);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or54(wCounterin5, wCounterin4, wCounterin54);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or32(wCounterin3, wCounterin2, wCounterin32);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or10(wCounterin1, wCounterin0, wCounterin10);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or32(wCounterin76, wCounterin54, wCounterin7654);
hdl4se_binop #(1, 1, 1, `BINOP_OR) or10(wCounterin32, wCounterin10, wCounterin3210);
wire[2:0] wirein_bCounterChanged, wireout_bCounterChanged;
hdl4se_reg #(3) reg_bCounterChanged(
......
examples/counter/verilog/main_asm_dump.v
浏览文件 @ 9d69d016
......@@ -461,10 +461,10 @@ module counter
hdl4se_reg #( WIDTH ) bCurrentCounter( wClk, wirein_bCurrentCounter, wireout_bCurrentCounter );
hdl4se_const #( WIDTH, MAXVALUE ) const_MAXVALUE( bConst_MAXVALUE );
hdl4se_const #( WIDTH, RESETVALUE ) const_RESETVALUE( bConst_RESETVALUE );
hdl4se_binop #( WIDTH, WIDTH, 1, BINOP_EQ ) binop_EQ_bCurrentCounter_MAXVALUE( wireout_bCurrentCounter, bConst_MAXVALUE, wEQ_bCurrentCounter_MAXVALUE );
hdl4se_binop #( 1, 1, 1, BINOP_AND ) binop_counter_overfloat( wEQ_bCurrentCounter_MAXVALUE, wCounterIt, wCounterOverflow );
hdl4se_binop #( WIDTH, WIDTH, 1, 4 ) binop_EQ_bCurrentCounter_MAXVALUE( wireout_bCurrentCounter, bConst_MAXVALUE, wEQ_bCurrentCounter_MAXVALUE );
hdl4se_binop #( 1, 1, 1, 10 ) binop_counter_overfloat( wEQ_bCurrentCounter_MAXVALUE, wCounterIt, wCounterOverflow );
hdl4se_const #( WIDTH, 1 ) const_One( bConst_One );
hdl4se_binop #( WIDTH, WIDTH, 1, BINOP_ADD ) binop_bCurrentCounterInc( wireout_bCurrentCounter, bConst_One, bCurrentCounterPlusOne );
hdl4se_binop #( WIDTH, WIDTH, 1, 0 ) binop_bCurrentCounterInc( wireout_bCurrentCounter, bConst_One, bCurrentCounterPlusOne );
hdl4se_mux2 #( WIDTH ) mux_bCurrentCounter_if_wCounterIt( wEQ_bCurrentCounter_MAXVALUE, bCurrentCounterPlusOne, bConst_RESETVALUE, bCurrentCounter_if_wCounterIt );
hdl4se_const #( 1, 1 ) const_1( wConst_1 );
hdl4se_const #( 1, 0 ) const_0( wConst_0 );
......@@ -598,10 +598,10 @@ module main
counter #( 4, 9, 0 ) counter8( wClk, nwResetCount, wCounterin8, bCount8, wOverflow8 );
counter #( 4, 9, 0 ) counter9( wClk, nwResetCount, wCounterin9, bCount9, wnouse );
hdl4se_reg #( 1 ) wCounterIt( wClk, wirein_wCounterIt, wireout_wCounterIt );
hdl4se_unop #( 1, 1, UNOP_NOT ) Button0NotPressed( wButton0Pressed, wButton0NotPressed );
hdl4se_unop #( 1, 1, UNOP_NOT ) unop_Button1NotPressed( wButton1Pressed, wButton1NotPressed );
hdl4se_binop #( 1, 1, 1, BINOP_AND ) binop_counterit( wButton1NotPressed, wButton2Pressed, wirein_wCounterIt );
hdl4se_binop #( 1, 1, 1, BINOP_AND ) binop_resetcounter( wButton0NotPressed, nwReset, nwResetCount );
hdl4se_unop #( 1, 1, 1 ) Button0NotPressed( wButton0Pressed, wButton0NotPressed );
hdl4se_unop #( 1, 1, 1 ) unop_Button1NotPressed( wButton1Pressed, wButton1NotPressed );
hdl4se_binop #( 1, 1, 1, 10 ) binop_counterit( wButton1NotPressed, wButton2Pressed, wirein_wCounterIt );
hdl4se_binop #( 1, 1, 1, 10 ) binop_resetcounter( wButton0NotPressed, nwReset, nwResetCount );
dec2seg dec0( bCount0, code0 );
dec2seg dec1( bCount1, code1 );
dec2seg dec2( bCount2, code2 );
......@@ -612,13 +612,13 @@ module main
dec2seg dec7( bCount7, code7 );
dec2seg dec8( bCount8, code8 );
dec2seg dec9( bCount9, code9 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or98( wCounterin9, wCounterin8, wCounterin98 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or76( wCounterin7, wCounterin6, wCounterin76 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or54( wCounterin5, wCounterin4, wCounterin54 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or32( wCounterin3, wCounterin2, wCounterin32 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or10( wCounterin1, wCounterin0, wCounterin10 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or32( wCounterin76, wCounterin54, wCounterin7654 );
hdl4se_binop #( 1, 1, 1, BINOP_OR ) or10( wCounterin32, wCounterin10, wCounterin3210 );
hdl4se_binop #( 1, 1, 1, 11 ) or98( wCounterin9, wCounterin8, wCounterin98 );
hdl4se_binop #( 1, 1, 1, 11 ) or76( wCounterin7, wCounterin6, wCounterin76 );
hdl4se_binop #( 1, 1, 1, 11 ) or54( wCounterin5, wCounterin4, wCounterin54 );
hdl4se_binop #( 1, 1, 1, 11 ) or32( wCounterin3, wCounterin2, wCounterin32 );
hdl4se_binop #( 1, 1, 1, 11 ) or10( wCounterin1, wCounterin0, wCounterin10 );
hdl4se_binop #( 1, 1, 1, 11 ) or32( wCounterin76, wCounterin54, wCounterin7654 );
hdl4se_binop #( 1, 1, 1, 11 ) or10( wCounterin32, wCounterin10, wCounterin3210 );
hdl4se_reg #( 3 ) reg_bCounterChanged( wClk, wirein_bCounterChanged, wireout_bCounterChanged );
hdl4se_bind3 #( 1, 1, 1 ) bind_wCounterin( wCounterin98, wCounterin7654, wCounterin3210, bChanged_if_nwReset );
hdl4se_const #( 3, 0 ) const_b3b0( b3b0 );
......
examples/terris/src/main.c
浏览文件 @ 9d69d016
......@@ -68,7 +68,7 @@ int main(int argc, char* argv[])
IHDL4SEUnit** sim_unit;
A_u_t_o_registor_terrisctrl();
sim = hdl4sesimCreateSimulator();
topmodule = hdl4seCreate_main2(NULL, "", "main");
topmodule = hdl4seCreate_main(NULL, "", "main");
gui = guiCreate(0xf0000000, "terris");
objectCall1(sim, SetTopModule, topmodule);
objectCall1(sim, AddDevice, gui);
......
examples/terris/src/topmodule.c
浏览文件 @ 9d69d016
......@@ -31,7 +31,7 @@
/*
* Created by HDL4SE @ Sat Jun 12 15:21:53 2021
* Created by HDL4SE @ Sat Jun 12 21:02:17 2021
* Don't edit it.
*/
......@@ -47,20 +47,6 @@
#include "verilog_parsetree.h"
typedef IHDL4SEUnit** (*hdl4seCreate_Func)(IHDL4SEModule** parent, const char* instanceparam, const char* name);
typedef struct s_module_info {
int isbasiccell;
int moduleindex;
union {
const char** clsid;
hdl4seCreate_Func *hdl4seCreate_func;
};
}module_info;
static const char *softmodule_000F = "hdl4se";
static const char *softmodule_000B = "hdl4se";
IHDL4SEUnit** hdl4seCreate_main(IHDL4SEModule** parent, const char* instanceparam, const char* name)
{ /* module main */
IHDL4SEModule** module;
......@@ -84,42 +70,29 @@ IHDL4SEUnit** hdl4seCreate_main(IHDL4SEModule** parent, const char* instancepara
/* 8*/ objectCall3(module, AddPort, PORT_DIRECT_INPUT , 32, "bReadData");
{/* 模块实例化 */
char instanceparam[256];
/* 0 teris_ctrl ctrl*/
{
modules[0] = hdl4seCreateUnit2(module, "6f8a9aa6-ec57-4734-a183-7871ed57ea95", instanceparam, "ctrl");
}
/* 1 hdl4se_const const_wRead*/
{
modules[1] = hdl4seCreateUnit2(module, "8FBE5B87-B484-4f95-8291-DBEF86A1C354", instanceparam, "const_wRead");
}
/* 2 hdl4se_const const_bReadAddr*/
{
modules[2] = hdl4seCreateUnit2(module, "8FBE5B87-B484-4f95-8291-DBEF86A1C354", instanceparam, "const_bReadAddr");
}
/* 3 hdl4se_const const_wWrite*/
{
modules[3] = hdl4seCreateUnit2(module, "8FBE5B87-B484-4f95-8291-DBEF86A1C354", instanceparam, "const_wWrite");
}
modules[ 0] = hdl4seCreateUnit2(module, "6f8a9aa6-ec57-4734-a183-7871ed57ea95", "", "ctrl");
modules[ 1] = hdl4seCreateUnit2(module, "8FBE5B87-B484-4f95-8291-DBEF86A1C354", "2'h1, 2'h1", "const_wRead");
modules[ 2] = hdl4seCreateUnit2(module, "8FBE5B87-B484-4f95-8291-DBEF86A1C354", "7'h20, 32'hf0000000", "const_bReadAddr");
modules[ 3] = hdl4seCreateUnit2(module, "8FBE5B87-B484-4f95-8291-DBEF86A1C354", "2'h1, 2'h1", "const_wWrite");
}
/* 线网连接 */
/* instance "ctrl", module "teris_ctrl" */
objectCall3(modules[0], Connect, 0, unit, 0);
objectCall3(modules[0], Connect, 1, unit, 1);
objectCall3(unit, Connect, 3, modules[0], 2);
objectCall3(unit, Connect, 4, modules[0], 3);
objectCall3(modules[0], Connect, 4, unit, 8);
objectCall3(modules[0], Connect, 0, unit, 0);
objectCall3(modules[0], Connect, 1, unit, 1);
objectCall3(unit, Connect, 3, modules[0], 2);
objectCall3(unit, Connect, 4, modules[0], 3);
objectCall3(modules[0], Connect, 4, unit, 8);
/* instance "const_wRead", module "hdl4se_const" */
objectCall3(unit, Connect, 6, modules[1], 0);
objectCall3(unit, Connect, 6, modules[1], 0);
/* instance "const_bReadAddr", module "hdl4se_const" */
objectCall3(unit, Connect, 7, modules[2], 0);
objectCall3(unit, Connect, 7, modules[2], 0);
/* instance "const_wWrite", module "hdl4se_const" */
objectCall3(unit, Connect, 2, modules[3], 0);
objectCall3(unit, Connect, 2, modules[3], 0);
/*释放module接口*/
objectRelease(module);
......
hdl4secell/src/hdl4secell.c
浏览文件 @ 9d69d016
......@@ -110,7 +110,7 @@ IHDL4SEUnit** hdl4seCreateUnit2(IHDL4SEModule** parent, const char* clsid, const
{
unsigned int inclsid[4];
str2iid(clsid, inclsid);
return hdl4seCreateUnit2(parent, inclsid, instanceparam, name);
return hdl4seCreateUnit(parent, inclsid, instanceparam, name);
}
......
parser/verilog_expr.c
浏览文件 @ 9d69d016
......@@ -45,6 +45,7 @@
#include "conststring.h"
#include "verilog_parsetree.h"
#include "verilog_module.h"
#include "verilog_varsel.h"
#define IMPLEMENT_GUID
#include "verilog_expr.h"
#undef IMPLEMENT_GUID
......@@ -420,42 +421,76 @@ int verilogparseGenConstExpr(FILE* pFile, const char* pre, HOBJECT expr, HOBJECT
count = 1;
switch (pobj->data.exprtype) {
case EXPRTYPE_NUMBER:
{
fprintf(pFile, "%s{.exprtype=EXPRTYPE_NUMBER, .value=\"%s\" }, \n", pre, pobj->data.value->string);
break;
}
case EXPRTYPE_BIGNUMBER:
{
objectCall3(pobj->data.bignumber, GetStr, 16, hdl4se_parse_logbuf(), 1024);
fprintf(pFile, "%s{.exprtype=EXPRTYPE_NUMBER, .value=\"%s\" }, \n", pre, hdl4se_parse_logbuf());
break;
}
case EXPRTYPE_STRING:
{
fprintf(pFile, "%s{.exprtype=EXPRTYPE_STRING, .value=%s},\n", pre, pobj->data.value->string);
break;
}
case EXPRTYPE_PARAM:
{
fprintf(pFile, "%s{.exprtype=EXPRTYPE_PARAM, .index=%d},/* %s */\n", pre, verilogModuleGetParamIndex(module, pobj->data.value->string), pobj->data.value->string);
break;
}
case EXPRTYPE_LOCALPARAM:
{
fprintf(pFile, "%s{.exprtype=EXPRTYPE_LOCALPARAM, .index=%d},/* %s */\n", pre, verilogModuleGetLocalParamIndex(module, pobj->data.value->string), pobj->data.value->string);
break;
}
case EXPRTYPE_BINOP:
{
count = verilogparseGenConstExpr(pFile, pre, pobj->data.expr0, module);
count += verilogparseGenConstExpr(pFile, pre, pobj->data.expr1, module);
fprintf(pFile, "%s{.exprtype=EXPRTYPE_BINOP, .op=%s},\n", pre, OPERATOR_name[pobj->data.op]);
count++;
break;
}
case EXPRTYPE_UNOP:
{
count = verilogparseGenConstExpr(pFile, pre, pobj->data.expr0, module);
fprintf(pFile, "%s{.exprtype=EXPRTYPE_UNOP, .op=%s},\n", pre, OPERATOR_name[pobj->data.op]);
count++;
break;
}
case EXPRTYPE_IFOP:
{
count = verilogparseGenConstExpr(pFile, pre, pobj->data.expr0, module);
count += verilogparseGenConstExpr(pFile, pre, pobj->data.expr1, module);
count += verilogparseGenConstExpr(pFile, pre, pobj->data.expr2, module);
fprintf(pFile, "%s{.exprtype=EXPRTYPE_IFOP, .op=0},\n", pre);
count++;
break;
}
case EXPRTYPE_HIERARCHICAL_IDENT:
{
int index = -1;
/* 目前只取第一个名称 */
verilogVarSel* select;
select = verilogVarSelGetData(pobj->data.elementselect->__dlist_pNext);
if (select != NULL) {
index = verilogModuleGetParamIndex(module, select->name->string);
}
if (index >= 0)
fprintf(pFile, "%s{.exprtype=EXPRTYPE_PARAM, .index=%d},/* %s */\n", pre, index, select->name->string);
else
fprintf(pFile, "%s{error: can not find parameter %s}\n", pre, select->name->string);
break;
}
default:
{
fprintf(pFile, "%s error type %d,\n", pre, pobj->data.exprtype);
count = 0;
break;
break;
}
}
return count;
}
\ No newline at end of file
parser/verilog_module.c
浏览文件 @ 9d69d016
......@@ -277,15 +277,35 @@ int verilogModuleGetLocalParamIndex(HOBJECT object, const char* name)
char* moduleinstanceGetParameterString(verilogModuleInstance* moduleinstance)
{
/* 目前先简单地假定实参中已经列出所有的参数 */
int index;
IDListVarPtr pitem, pitemtemp;
verilogParameterInstance* paraminst;
IDListVarPtr plist = moduleinstance->parameter_value_assignment;
char* buf = hdl4se_parse_logbuf();
pitem = plist->__dlist_pNext;
index = 0;
while (pitem != plist) {
verilogExpr* expr0;
paraminst = verilogParameterInstanceGetData(pitem);
pitemtemp = pitem->__dlist_pNext;
expr0 = verilogExprGetData(paraminst->expr0);
if (expr0 == NULL)
return NULL;
if (expr0->exprtype != EXPRTYPE_BIGNUMBER) {
return NULL;
}
if (index > 0) {
*buf++ = ',';
*buf++ = ' ';
}
if (0 != objectCall3(expr0->bignumber, GetStr, 16, buf, 1024)) {
return NULL;
}
buf = buf + strlen(buf);
index++;
pitem = pitemtemp;
}
return NULL;
return hdl4se_parse_logbuf();
}
static int verilogmodule_verilognode_gencode(HOBJECT object, FILE * pFile, const char * modulename, void * opt)
......@@ -503,13 +523,13 @@ static int verilogmodule_verilognode_gencode(HOBJECT object, FILE * pFile, const
moduleinstance->index = index++;
if (dlistItemCount(moduleinfo->module_parameters) <= 0) {
if (moduleinfo->isbasiccell) {
fprintf(pFile, "\t\tmodules[%d] = hdl4seCreateUnit2(module, %s, \"\", \"%s\");\n",
fprintf(pFile, "\t\tmodules[%3d] = hdl4seCreateUnit2(module, %s, \"\", \"%s\");\n",
moduleinstance->index,
moduleinfo->cell_clsid->string,
moduleinstance->instname->string);
}
else {
fprintf(pFile, "\t\tmodules[%d] = hdl4seCreate_%04X(module, \"\", \"%s\");\n",
fprintf(pFile, "\t\tmodules[%3d] = hdl4seCreate_%04X(module, \"\", \"%s\");\n",
moduleinstance->index,
moduleinfo->moduleindex,
moduleinstance->instname->string);
......@@ -519,14 +539,14 @@ static int verilogmodule_verilognode_gencode(HOBJECT object, FILE * pFile, const
parameterstring = moduleinstanceGetParameterString(moduleinstance);
if (parameterstring != NULL) {
if (moduleinfo->isbasiccell) {
fprintf(pFile, "\t\t\tmodules[%d] = hdl4seCreateUnit2(module, %s, \"%s\", \"%s\");\n",
fprintf(pFile, "\t\tmodules[%3d] = hdl4seCreateUnit2(module, %s, \"%s\", \"%s\");\n",
moduleinstance->index,
moduleinfo->cell_clsid->string,
parameterstring,
moduleinstance->instname->string);
}
else {
fprintf(pFile, "\t\t\tmodules[%d] = hdl4seCreate_%04X(module, \"%s\", \"%s\");\n",
fprintf(pFile, "\t\tmodules[%3d] = hdl4seCreate_%04X(module, \"%s\", \"%s\");\n",
moduleinstance->index,
moduleinfo->moduleindex,
parameterstring,
......@@ -534,22 +554,46 @@ static int verilogmodule_verilognode_gencode(HOBJECT object, FILE * pFile, const
}
}
else {
int exprcount;
fprintf(pFile, "\t\t/*%3d %s %s*/\n",
moduleinstance->index,
moduleinstance->modulename->string,
moduleinstance->instname->string);
fprintf(pFile, "\t\t{\n");
fprintf(pFile, "\t\t\tchar *instanceparam;\n");
fprintf(pFile, "\t\t\tconst expr_code expr_info[] = {\n");
exprcount = 0;
{
IDListVarPtr pitem, pitemtemp;
verilogParameterInstance* paraminst;
IDListVarPtr plist = moduleinstance->parameter_value_assignment;
pitem = plist->__dlist_pNext;
while (pitem != plist) {
paraminst = verilogParameterInstanceGetData(pitem);
pitemtemp = pitem->__dlist_pNext;
exprcount += verilogparseGenConstExpr(pFile, "\t\t\t\t", paraminst->expr0, object);
fprintf(pFile, "\t\t\t\t{.exprtype=EXPRTYPE_EMIT},\n");
exprcount++;
pitem = pitemtemp;
}
}
fprintf(pFile, "\t\t\t};\n");
if (moduleinfo->isbasiccell) {
fprintf(pFile, "\t\t\tmodules[%d] = hdl4seCreateUnit2(module, %s, instanceparam, \"%s\");\n",
fprintf(pFile, "\t\t\tmodules[%3d] = hdl4seCreateUnit2(module, %s, const_expr_list_eval(%d, expr_info, %d, %s), \"%s\");\n",
moduleinstance->index,
moduleinfo->cell_clsid->string,
exprcount,
paramcount,
paramcount > 0 ? "parameters" : "NULL",
moduleinstance->instname->string);
}
else {
fprintf(pFile, "\t\t\tmodules[%d] = hdl4seCreate_%04X(module, instanceparam, \"%s\");\n",
fprintf(pFile, "\t\t\tmodules[%3d] = hdl4seCreate_%04X(module, const_expr_list_eval(%d, expr_info, %d, %s), \"%s\");\n",
moduleinstance->index,
moduleinfo->moduleindex,
exprcount,
paramcount,
paramcount > 0 ? "parameters" : "NULL",
moduleinstance->instname->string);
}
fprintf(pFile, "\t\t}\n");
......
parser/verilog_parsetree.h
浏览文件 @ 9d69d016
......@@ -155,6 +155,7 @@ enum exprtype {
EXPRTYPE_IFOP,
EXPRTYPE_IDENT,
EXPRTYPE_HIERARCHICAL_IDENT,
EXPRTYPE_EMIT,
};
enum RANGE_TYPE {
......@@ -300,6 +301,7 @@ typedef struct _expr_code {
}expr_code;
int const_expr_eval(int expr_infosize, expr_code *expr_info, int paramcount, IBigNumber***parameters);
const char * const_expr_list_eval(int expr_infosize, expr_code* expr_info, int paramcount, IBigNumber*** parameters);
#endif
......
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