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提交 c4750924 编写于 作者: 饶先宏's avatar 饶先宏
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202108272000

上级 08c63023
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examples/hdl4se_riscv/de1/PLLJ_PLLSPE_INFO.txt
浏览文件 @ c4750924
PLL_Name clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL PLL_Name clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
PLLJITTER 21 PLLJITTER 22
PLLSPEmax 50 PLLSPEmax 50
PLLSPEmin -50 PLLSPEmin -50
......
examples/hdl4se_riscv/de1/alu/div.v
浏览文件 @ c4750924
...@@ -37,11 +37,13 @@ ...@@ -37,11 +37,13 @@
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
// synopsys translate_on // synopsys translate_on
module div ( module div (
clock,
denom, denom,
numer, numer,
quotient, quotient,
remain); remain);
input clock;
input [31:0] denom; input [31:0] denom;
input [31:0] numer; input [31:0] numer;
output [31:0] quotient; output [31:0] quotient;
...@@ -49,21 +51,22 @@ module div ( ...@@ -49,21 +51,22 @@ module div (
wire [31:0] sub_wire0; wire [31:0] sub_wire0;
wire [31:0] sub_wire1; wire [31:0] sub_wire1;
wire [31:0] quotient = sub_wire0[31:0]; wire [31:0] remain = sub_wire0[31:0];
wire [31:0] remain = sub_wire1[31:0]; wire [31:0] quotient = sub_wire1[31:0];
lpm_divide LPM_DIVIDE_component ( lpm_divide LPM_DIVIDE_component (
.clock (clock),
.denom (denom), .denom (denom),
.numer (numer), .numer (numer),
.quotient (sub_wire0), .remain (sub_wire0),
.remain (sub_wire1), .quotient (sub_wire1),
.aclr (1'b0), .aclr (1'b0),
.clken (1'b1), .clken (1'b1));
.clock (1'b0));
defparam defparam
LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED", LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE", LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED", LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_pipeline = 12,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE", LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32, LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32; LPM_DIVIDE_component.lpm_widthn = 32;
...@@ -78,20 +81,23 @@ endmodule ...@@ -78,20 +81,23 @@ endmodule
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" // Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" // Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0" // Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" // Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1" // Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" // Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" // Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" // Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]" // Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]" // Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]" // Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]" // Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0 // Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0 // Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0 // Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
......
examples/hdl4se_riscv/de1/alu/div_bb.v
浏览文件 @ c4750924
...@@ -32,11 +32,13 @@ ...@@ -32,11 +32,13 @@
//applicable agreement for further details. //applicable agreement for further details.
module div ( module div (
clock,
denom, denom,
numer, numer,
quotient, quotient,
remain); remain);
input clock;
input [31:0] denom; input [31:0] denom;
input [31:0] numer; input [31:0] numer;
output [31:0] quotient; output [31:0] quotient;
...@@ -51,20 +53,23 @@ endmodule ...@@ -51,20 +53,23 @@ endmodule
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" // Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" // Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0" // Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" // Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1" // Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED" // Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" // Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED" // Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]" // Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]" // Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]" // Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]" // Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0 // Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0 // Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0 // Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
......
examples/hdl4se_riscv/de1/alu/div_s.v
浏览文件 @ c4750924
...@@ -37,11 +37,13 @@ ...@@ -37,11 +37,13 @@
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
// synopsys translate_on // synopsys translate_on
module div_s ( module div_s (
clock,
denom, denom,
numer, numer,
quotient, quotient,
remain); remain);
input clock;
input [31:0] denom; input [31:0] denom;
input [31:0] numer; input [31:0] numer;
output [31:0] quotient; output [31:0] quotient;
...@@ -49,21 +51,22 @@ module div_s ( ...@@ -49,21 +51,22 @@ module div_s (
wire [31:0] sub_wire0; wire [31:0] sub_wire0;
wire [31:0] sub_wire1; wire [31:0] sub_wire1;
wire [31:0] quotient = sub_wire0[31:0]; wire [31:0] remain = sub_wire0[31:0];
wire [31:0] remain = sub_wire1[31:0]; wire [31:0] quotient = sub_wire1[31:0];
lpm_divide LPM_DIVIDE_component ( lpm_divide LPM_DIVIDE_component (
.clock (clock),
.denom (denom), .denom (denom),
.numer (numer), .numer (numer),
.quotient (sub_wire0), .remain (sub_wire0),
.remain (sub_wire1), .quotient (sub_wire1),
.aclr (1'b0), .aclr (1'b0),
.clken (1'b1), .clken (1'b1));
.clock (1'b0));
defparam defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED", LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE", LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED", LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 12,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE", LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32, LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32; LPM_DIVIDE_component.lpm_widthn = 32;
...@@ -78,20 +81,23 @@ endmodule ...@@ -78,20 +81,23 @@ endmodule
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" // Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" // Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0" // Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" // Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1" // Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED" // Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" // Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED" // Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]" // Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]" // Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]" // Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]" // Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0 // Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0 // Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0 // Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
......
examples/hdl4se_riscv/de1/alu/div_s_bb.v
浏览文件 @ c4750924
...@@ -32,11 +32,13 @@ ...@@ -32,11 +32,13 @@
//applicable agreement for further details. //applicable agreement for further details.
module div_s ( module div_s (
clock,
denom, denom,
numer, numer,
quotient, quotient,
remain); remain);
input clock;
input [31:0] denom; input [31:0] denom;
input [31:0] numer; input [31:0] numer;
output [31:0] quotient; output [31:0] quotient;
...@@ -51,20 +53,23 @@ endmodule ...@@ -51,20 +53,23 @@ endmodule
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE" // Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1" // Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0" // Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2" // Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1" // Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED" // Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE" // Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED" // Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]" // Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]" // Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]" // Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]" // Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0 // Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0 // Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0 // Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
......
examples/hdl4se_riscv/de1/clk/clk100M.v
浏览文件 @ c4750924
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
// GENERATION: XML // GENERATION: XML
// clk100M.v // clk100M.v
// Generated using ACDS version 13.1 162 at 2021.08.27.08:01:33 // Generated using ACDS version 13.1 162 at 2021.08.27.17:20:30
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
module clk100M ( module clk100M (
...@@ -68,7 +68,7 @@ endmodule ...@@ -68,7 +68,7 @@ endmodule
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" /> // Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" /> // Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" /> // Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="400.0" /> // Retrieval info: <generic name="gui_output_clock_frequency0" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" /> // Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" /> // Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" /> // Retrieval info: <generic name="gui_ps_units0" value="ps" />
......
examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v
浏览文件 @ c4750924
...@@ -22,7 +22,7 @@ module clk100M_0002( ...@@ -22,7 +22,7 @@ module clk100M_0002(
.reference_clock_frequency("50.0 MHz"), .reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"), .operation_mode("direct"),
.number_of_clocks(2), .number_of_clocks(2),
.output_clock_frequency0("400.000000 MHz"), .output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"), .phase_shift0("0 ps"),
.duty_cycle0(50), .duty_cycle0(50),
.output_clock_frequency1("75.000000 MHz"), .output_clock_frequency1("75.000000 MHz"),
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl
浏览文件 @ c4750924
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40 # ACDS 13.1 162 win32 2021.08.27.17:20:37
# ---------------------------------------- # ----------------------------------------
# Auto-generated simulation script # Auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh
浏览文件 @ c4750924
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40 # ACDS 13.1 162 win32 2021.08.27.17:20:37
# ---------------------------------------- # ----------------------------------------
# ncsim - auto-generated simulation script # ncsim - auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo
浏览文件 @ c4750924
...@@ -210,7 +210,7 @@ module clk100M ...@@ -210,7 +210,7 @@ module clk100M
clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false", clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false",
clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2, clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2,
clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct", clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "400.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "100.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz",
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl
浏览文件 @ c4750924
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40 # ACDS 13.1 162 win32 2021.08.27.17:20:37
# ---------------------------------------- # ----------------------------------------
# Auto-generated simulation script # Auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh
浏览文件 @ c4750924
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40 # ACDS 13.1 162 win32 2021.08.27.17:20:37
# ---------------------------------------- # ----------------------------------------
# vcs - auto-generated simulation script # vcs - auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh
浏览文件 @ c4750924
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40 # ACDS 13.1 162 win32 2021.08.27.17:20:37
# ---------------------------------------- # ----------------------------------------
# vcsmx - auto-generated simulation script # vcsmx - auto-generated simulation script
......
examples/hdl4se_riscv/de1/clk100M.xml
浏览文件 @ c4750924
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
<generic name="gui_frac_multiply_factor" value="1" /> <generic name="gui_frac_multiply_factor" value="1" />
<generic name="gui_divide_factor_n" value="1" /> <generic name="gui_divide_factor_n" value="1" />
<generic name="gui_cascade_counter0" value="false" /> <generic name="gui_cascade_counter0" value="false" />
<generic name="gui_output_clock_frequency0" value="100.0" /> <generic name="gui_output_clock_frequency0" value="10.0" />
<generic name="gui_divide_factor_c0" value="1" /> <generic name="gui_divide_factor_c0" value="1" />
<generic name="gui_actual_output_clock_frequency0" value="0 MHz" /> <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
<generic name="gui_ps_units0" value="ps" /> <generic name="gui_ps_units0" value="ps" />
......
examples/hdl4se_riscv/de1/de1_risc.cr.mti
浏览文件 @ c4750924
...@@ -99,6 +99,13 @@ Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 ...@@ -99,6 +99,13 @@ Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
Top level modules: Top level modules:
riscv_core riscv_core
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module div_s
Top level modules:
div_s
} {} {}} C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v {1 {vlog -work work C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v } {} {}} C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v {1 {vlog -work work C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module lcell -- Compiling module lcell
...@@ -225,13 +232,6 @@ Top level modules: ...@@ -225,13 +232,6 @@ Top level modules:
sld_virtual_jtag_basic sld_virtual_jtag_basic
altsource_probe altsource_probe
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module div_s
Top level modules:
div_s
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v } {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module mulsu -- Compiling module mulsu
...@@ -239,13 +239,6 @@ Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 ...@@ -239,13 +239,6 @@ Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
Top level modules: Top level modules:
mulsu mulsu
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module de1_riscv
Top level modules:
de1_riscv
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v } {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module adder -- Compiling module adder
......
examples/hdl4se_riscv/de1/de1_risc.mpf
浏览文件 @ c4750924
...@@ -133,8 +133,8 @@ twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm ...@@ -133,8 +133,8 @@ twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
work = work
220model_0 = C:/altera/13.1/modelsim_ae/altera/verilog/220model 220model_0 = C:/altera/13.1/modelsim_ae/altera/verilog/220model
work = work
[vcom] [vcom]
; VHDL93 variable selects language version as the default. ; VHDL93 variable selects language version as the default.
; Default is VHDL-2002. ; Default is VHDL-2002.
...@@ -448,35 +448,39 @@ ConcurrentFileLimit = 40 ...@@ -448,35 +448,39 @@ ConcurrentFileLimit = 40
Project_Version = 6 Project_Version = 6
Project_DefaultLib = work Project_DefaultLib = work
Project_SortMethod = unused Project_SortMethod = unused
Project_Files_Count = 14 Project_Files_Count = 16
Project_File_0 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_test.v Project_File_0 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1629979729 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1630042952 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/altera/13.1/quartus/eda/sim_lib/220model.v Project_File_1 = C:/altera/13.1/quartus/eda/sim_lib/220model.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637203 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637203 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v Project_File_2 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629976037 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630049086 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v Project_File_3 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629976037 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969062 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v Project_File_4 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1629987192 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629968208 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v Project_File_5 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1630021006 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630042952 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v Project_File_6 = D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637282 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1630054226 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v Project_File_7 = C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629976037 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637282 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v Project_File_8 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630013728 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1630054286 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v Project_File_9 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1629977359 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1630042952 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v Project_File_10 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629976037 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630053824 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v Project_File_11 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630014534 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v Project_File_12 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629976037 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969030 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v Project_File_13 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629976037 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1630042952 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1630054260 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629968242 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0 Project_Sim_Count = 0
Project_Folder_Count = 0 Project_Folder_Count = 0
Echo_Compile_Output = 0 Echo_Compile_Output = 0
......
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
浏览文件 @ c4750924
Assembler report for de1_riscv Assembler report for de1_riscv
Fri Aug 27 13:40:33 2021 Fri Aug 27 17:23:28 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
...@@ -37,7 +37,7 @@ applicable agreement for further details. ...@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Aug 27 13:40:33 2021 ; ; Assembler Status ; Successful - Fri Aug 27 17:23:28 2021 ;
; Revision Name ; de1_riscv ; ; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ; ; Family ; Cyclone V ;
...@@ -92,8 +92,8 @@ applicable agreement for further details. ...@@ -92,8 +92,8 @@ applicable agreement for further details.
; Option ; Setting ; ; Option ; Setting ;
+----------------+--------------------------------------------------------------------+ +----------------+--------------------------------------------------------------------+
; Device ; 5CSEMA5F31C6 ; ; Device ; 5CSEMA5F31C6 ;
; JTAG usercode ; 0x00DD6BE7 ; ; JTAG usercode ; 0x0122624D ;
; Checksum ; 0x00DD6BE7 ; ; Checksum ; 0x0122624D ;
+----------------+--------------------------------------------------------------------+ +----------------+--------------------------------------------------------------------+
...@@ -103,13 +103,13 @@ applicable agreement for further details. ...@@ -103,13 +103,13 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Fri Aug 27 13:40:19 2021 Info: Processing started: Fri Aug 27 17:23:13 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 627 megabytes Info: Peak virtual memory: 661 megabytes
Info: Processing ended: Fri Aug 27 13:40:33 2021 Info: Processing ended: Fri Aug 27 17:23:28 2021
Info: Elapsed time: 00:00:14 Info: Elapsed time: 00:00:15
Info: Total CPU time (on all processors): 00:00:14 Info: Total CPU time (on all processors): 00:00:15
examples/hdl4se_riscv/de1/de1_riscv.done
浏览文件 @ c4750924
Fri Aug 27 13:41:00 2021 Fri Aug 27 17:24:02 2021
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
浏览文件 @ c4750924
Fitter Status : Successful - Fri Aug 27 13:40:16 2021 Fitter Status : Successful - Fri Aug 27 17:23:08 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv Revision Name : de1_riscv
Top-level Entity Name : de1_riscv Top-level Entity Name : de1_riscv
Family : Cyclone V Family : Cyclone V
Device : 5CSEMA5F31C6 Device : 5CSEMA5F31C6
Timing Models : Preliminary Timing Models : Preliminary
Logic utilization (in ALMs) : 249 / 32,070 ( < 1 % ) Logic utilization (in ALMs) : 2,468 / 32,070 ( 8 % )
Total registers : 207 Total registers : 1833
Total pins : 204 / 457 ( 45 % ) Total pins : 204 / 457 ( 45 % )
Total virtual pins : 0 Total virtual pins : 0
Total block memory bits : 63,488 / 4,065,280 ( 2 % ) Total block memory bits : 66,560 / 4,065,280 ( 2 % )
Total DSP Blocks : 4 / 87 ( 5 % ) Total DSP Blocks : 10 / 87 ( 11 % )
Total HSSI RX PCSs : 0 Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0 Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0 Total HSSI TX PCSs : 0
Total HSSI TX Channels : 0 Total HSSI TX Channels : 0
Total PLLs : 0 / 6 ( 0 % ) Total PLLs : 1 / 6 ( 17 % )
Total DLLs : 0 / 4 ( 0 % ) Total DLLs : 0 / 4 ( 0 % )
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
浏览文件 @ c4750924
Flow report for de1_riscv Flow report for de1_riscv
Fri Aug 27 13:40:59 2021 Fri Aug 27 17:24:01 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
...@@ -40,24 +40,24 @@ applicable agreement for further details. ...@@ -40,24 +40,24 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------------+---------------------------------------------+ +---------------------------------+---------------------------------------------+
; Flow Status ; Successful - Fri Aug 27 13:40:33 2021 ; ; Flow Status ; Successful - Fri Aug 27 17:23:28 2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ; ; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ; ; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ; ; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ; ; Timing Models ; Preliminary ;
; Logic utilization (in ALMs) ; 249 / 32,070 ( < 1 % ) ; ; Logic utilization (in ALMs) ; 2,468 / 32,070 ( 8 % ) ;
; Total registers ; 207 ; ; Total registers ; 1833 ;
; Total pins ; 204 / 457 ( 45 % ) ; ; Total pins ; 204 / 457 ( 45 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total block memory bits ; 63,488 / 4,065,280 ( 2 % ) ; ; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ;
; Total DSP Blocks ; 4 / 87 ( 5 % ) ; ; Total DSP Blocks ; 10 / 87 ( 11 % ) ;
; Total HSSI RX PCSs ; 0 ; ; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ; ; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ; ; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ; ; Total HSSI TX Channels ; 0 ;
; Total PLLs ; 0 / 6 ( 0 % ) ; ; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ; ; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+---------------------------------------------+ +---------------------------------+---------------------------------------------+
...@@ -67,50 +67,66 @@ applicable agreement for further details. ...@@ -67,50 +67,66 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 08/27/2021 13:39:08 ; ; Start date & time ; 08/27/2021 17:20:52 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; de1_riscv ; ; Revision Name ; de1_riscv ;
+-------------------+---------------------+ +-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ; ; Flow Non-Default Global Settings ;
+-------------------------------------+---------------------------------------+---------------+-------------+------------+ +-------------------------------------+---------------------------------------+---------------+--------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+-------------+------------+ +-------------------------------------+---------------------------------------+---------------+--------------+------------+
; COMPILER_SIGNATURE_ID ; 621136229624.163004274808040 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 621136229624.163005605235460 ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ; ; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ; ; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; altera_pll ; -- ; clk100M ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; altera_pll ; -- ; clk100M ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_NAME ; altera_pll ; -- ; clk100M_0002 ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; ram/ram8kb_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; regfile/regfile_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_s_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_s_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MISC_FILE ; alu/adder_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M ; -- ;
; MISC_FILE ; alu/suber_bb.v ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; ; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M_0002 ; -- ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; ; MISC_FILE ; ram/ram8kb_bb.v ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; ; MISC_FILE ; regfile/regfile_bb.v ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------------+---------------+-------------+------------+ ; MISC_FILE ; alu/mult_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_s_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_s_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/adder_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/suber_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mulsu_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; clk/clk100M.cmp ; -- ; -- ; -- ;
; MISC_FILE ; clk/clk100M_sim/clk100M.vo ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; SPD_FILE ; clk/clk100M.spd ; -- ; -- ; -- ;
; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------+
...@@ -118,11 +134,11 @@ applicable agreement for further details. ...@@ -118,11 +134,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 590 MB ; 00:00:04 ; ; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 670 MB ; 00:00:20 ;
; Fitter ; 00:01:02 ; 1.2 ; 2235 MB ; 00:01:12 ; ; Fitter ; 00:01:53 ; 1.4 ; 2325 MB ; 00:02:30 ;
; Assembler ; 00:00:14 ; 1.0 ; 627 MB ; 00:00:14 ; ; Assembler ; 00:00:15 ; 1.0 ; 661 MB ; 00:00:15 ;
; TimeQuest Timing Analyzer ; 00:00:25 ; 1.0 ; 1039 MB ; 00:00:26 ; ; TimeQuest Timing Analyzer ; 00:00:32 ; 1.3 ; 1135 MB ; 00:00:41 ;
; Total ; 00:01:46 ; -- ; -- ; 00:01:56 ; ; Total ; 00:03:01 ; -- ; -- ; 00:03:46 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
......
examples/hdl4se_riscv/de1/de1_riscv.jdi
浏览文件 @ c4750924
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="41afdacbf39d62304e2f"/> <hash md5_digest_80b="ad09d8c1da314a1d4db5"/>
</project> </project>
<file_info> <file_info>
<file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/> <file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/>
......
examples/hdl4se_riscv/de1/de1_riscv.map.summary
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Analysis & Synthesis Status : Successful - Fri Aug 27 13:39:13 2021 Analysis & Synthesis Status : Successful - Fri Aug 27 17:21:13 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv Revision Name : de1_riscv
Top-level Entity Name : de1_riscv Top-level Entity Name : de1_riscv
Family : Cyclone V Family : Cyclone V
Logic utilization (in ALMs) : N/A Logic utilization (in ALMs) : N/A
Total registers : 198 Total registers : 1608
Total pins : 204 Total pins : 204
Total virtual pins : 0 Total virtual pins : 0
Total block memory bits : 63,520 Total block memory bits : 67,296
Total DSP Blocks : 4 Total DSP Blocks : 10
Total HSSI RX PCSs : 0 Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0 Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0 Total HSSI TX PCSs : 0
Total HSSI TX Channels : 0 Total HSSI TX Channels : 0
Total PLLs : 0 Total PLLs : 1
Total DLLs : 0 Total DLLs : 0
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
浏览文件 @ c4750924
因为 它太大了无法显示 source diff 。你可以改为 查看blob。
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
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...@@ -2,52 +2,84 @@ ...@@ -2,52 +2,84 @@
TimeQuest Timing Analyzer Summary TimeQuest Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup 'CLOCK_50' Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 9.427 Slack : -1.729
TNS : -126.223
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.281
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.666
TNS : 0.000 TNS : 0.000
Type : Slow 1100mV 85C Model Hold 'CLOCK_50' Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.347 Slack : 3.775
TNS : 0.000 TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50' Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.896 Slack : 9.670
TNS : 0.000 TNS : 0.000
Type : Slow 1100mV 0C Model Setup 'CLOCK_50' Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 9.366 Slack : -1.885
TNS : -158.135
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.260
TNS : 0.000 TNS : 0.000
Type : Slow 1100mV 0C Model Hold 'CLOCK_50' Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 0.329 Slack : 1.666
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.753
TNS : 0.000 TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.926 Slack : 9.673
TNS : 0.000
Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.113
TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.163
TNS : 0.000 TNS : 0.000
Type : Fast 1100mV 85C Model Setup 'CLOCK_50' Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 13.670 Slack : 1.666
TNS : 0.000 TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'CLOCK_50' Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.178 Slack : 3.889
TNS : 0.000 TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50' Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.490 Slack : 9.336
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 3.512
TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.147
TNS : 0.000 TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'CLOCK_50' Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 14.071 Slack : 1.666
TNS : 0.000 TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'CLOCK_50' Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.167 Slack : 3.889
TNS : 0.000 TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.443 Slack : 9.286
TNS : 0.000 TNS : 0.000
------------------------------------------------------------ ------------------------------------------------------------
examples/hdl4se_riscv/de1/de1_riscv.v
浏览文件 @ c4750924
...@@ -3,6 +3,8 @@ ...@@ -3,6 +3,8 @@
// This code is generated by Terasic System Builder // This code is generated by Terasic System Builder
//======================================================= //=======================================================
`define USECLOCK50_1
module de1_riscv( module de1_riscv(
//////////// ADC ////////// //////////// ADC //////////
...@@ -90,14 +92,18 @@ module de1_riscv( ...@@ -90,14 +92,18 @@ module de1_riscv(
inout [35:0] GPIO inout [35:0] GPIO
); );
`ifdef USECLOCK50
wire wClk = CLOCK_50;
`else
wire clk100MHz, clk75MHz, clklocked; wire clk100MHz, clk75MHz, clklocked;
clk100M clk100(.refclk(CLOCK_50), clk100M clk100(.refclk(CLOCK_50),
.rst(~KEY[3]), .rst(~KEY[3]),
.outclk_0(clk100MHz), .outclk_0(clk100MHz),
.outclk_1(clk75MHz), .outclk_1(clk75MHz),
.locked(clklocked)); .locked(clklocked));
wire wClk = clk100MHz; wire wClk = clk100MHz;
`endif
wire nwReset = KEY[3]; wire nwReset = KEY[3];
wire wWrite, wRead; wire wWrite, wRead;
......
examples/hdl4se_riscv/de1/doc/altera_pll.pdf 0 → 100644
浏览文件 @ c4750924
此差异已折叠。
examples/hdl4se_riscv/test_code/main.c
浏览文件 @ c4750924
...@@ -29,7 +29,7 @@ int main(int argc, char* argv[]) ...@@ -29,7 +29,7 @@ int main(int argc, char* argv[])
leddata[0] = 0x6f7f077d; leddata[0] = 0x6f7f077d;
leddata[1] = 0x6d664f5b; leddata[1] = 0x6d664f5b;
do { do {
/*unsigned int key; unsigned int key;
key = *ledkey; key = *ledkey;
if (key & 1) { if (key & 1) {
count = 0; count = 0;
...@@ -40,7 +40,7 @@ int main(int argc, char* argv[]) ...@@ -40,7 +40,7 @@ int main(int argc, char* argv[])
else if (key & 4) { else if (key & 4) {
countit = 1; countit = 1;
} }
if (countit)*/ if (countit)
count++; count++;
ctemp = count; ctemp = count;
......
examples/hdl4se_riscv/verilog/riscv_core.v
浏览文件 @ c4750924
...@@ -36,10 +36,12 @@ ...@@ -36,10 +36,12 @@
`define RISCVSTATE_READ_INST 2 `define RISCVSTATE_READ_INST 2
`define RISCVSTATE_READ_RS1 3 `define RISCVSTATE_READ_RS1 3
`define RISCVSTATE_READ_RS2 4 `define RISCVSTATE_READ_RS2 4
`define RISCVSTATE_WRITE_RD 5 `define RISCVSTATE_STORE_RS2 5
`define RISCVSTATE_EXEC_INST 6 `define RISCVSTATE_WRITE_RD 6
`define RISCVSTATE_WAIT_LD 7 `define RISCVSTATE_EXEC_INST 7
`define RISCVSTATE_WAIT_ST 8 `define RISCVSTATE_WAIT_LD 8
`define RISCVSTATE_WAIT_ST 9
`define RISCVSTATE_WAIT_DIV 10
`define RAMSIZE 2048 `define RAMSIZE 2048
...@@ -67,6 +69,7 @@ module riscv_core( ...@@ -67,6 +69,7 @@ module riscv_core(
reg [31:0] pc; //GREG(pc, 32, riscv_core_reg_gen_pc); reg [31:0] pc; //GREG(pc, 32, riscv_core_reg_gen_pc);
reg [31:0] instr; //GREG(instr, 32, riscv_core_reg_gen_instr); reg [31:0] instr; //GREG(instr, 32, riscv_core_reg_gen_instr);
reg [31:0] rs1; //GREG(rs1, 32, riscv_core_reg_gen_rs1); reg [31:0] rs1; //GREG(rs1, 32, riscv_core_reg_gen_rs1);
reg [31:0] rs2; //GREG(rs1, 32, riscv_core_reg_gen_rs2);
reg write; //GREG(write, 1, riscv_core_gen_write); reg write; //GREG(write, 1, riscv_core_gen_write);
reg [31:0] writeaddr; //GREG(writeaddr, 32, riscv_core_gen_write); reg [31:0] writeaddr; //GREG(writeaddr, 32, riscv_core_gen_write);
reg [31:0] writedata; //GREG(writedata, 32, riscv_core_gen_write); reg [31:0] writedata; //GREG(writedata, 32, riscv_core_gen_write);
...@@ -77,7 +80,7 @@ module riscv_core( ...@@ -77,7 +80,7 @@ module riscv_core(
reg [4:0] dstreg; //GREG(dstreg, 5, riscv_core_gen_dstreg); reg [4:0] dstreg; //GREG(dstreg, 5, riscv_core_gen_dstreg);
reg [31:0] dstvalue; //GREG(dstvalue, 32, riscv_core_gen_dstreg); reg [31:0] dstvalue; //GREG(dstvalue, 32, riscv_core_gen_dstreg);
reg [1:0] ldaddr; //GREG(ldaddr, 2, riscv_core_gen_ldaddr); reg [1:0] ldaddr; //GREG(ldaddr, 2, riscv_core_gen_ldaddr);
reg [4:0] divclk;
assign wWrite = write; assign wWrite = write;
assign bWriteAddr = writeaddr; assign bWriteAddr = writeaddr;
...@@ -85,7 +88,6 @@ module riscv_core( ...@@ -85,7 +88,6 @@ module riscv_core(
assign bWriteMask = writemask; assign bWriteMask = writemask;
wire [4:0] opcode = instr[6:2]; wire [4:0] opcode = instr[6:2];
wire [31:0] rs2 = regrddata;
wire [4:0] rd = instr[11:7]; wire [4:0] rd = instr[11:7];
wire [2:0] func3 = instr[14:12]; wire [2:0] func3 = instr[14:12];
reg cond; reg cond;
...@@ -104,8 +106,8 @@ module riscv_core( ...@@ -104,8 +106,8 @@ module riscv_core(
mult mul(rs1, rs2, mul_result); mult mul(rs1, rs2, mul_result);
mult_s mul_s(rs1, rs2, muls_result); mult_s mul_s(rs1, rs2, muls_result);
mulsu mul_su(rs1, {8'b0, rs2}, mulsu_result); mulsu mul_su(rs1, {8'b0, rs2}, mulsu_result);
div div(rs2, rs1, div_result_r, mod_result_r); div div(wClk, rs2, rs1, div_result_r, mod_result_r);
div_s divs(rs2, rs1, divs_result_r, mods_result_r); div_s divs(wClk, rs2, rs1, divs_result_r, mods_result_r);
assign div_result = (rs2 == 0) ? 32'hffffffff : div_result_r; assign div_result = (rs2 == 0) ? 32'hffffffff : div_result_r;
assign divs_result = (rs2 == 0) ? 32'hffffffff : divs_result_r; assign divs_result = (rs2 == 0) ? 32'hffffffff : divs_result_r;
...@@ -156,6 +158,11 @@ module riscv_core( ...@@ -156,6 +158,11 @@ module riscv_core(
if (state == `RISCVSTATE_READ_RS2) if (state == `RISCVSTATE_READ_RS2)
rs1 <= regrddata; rs1 <= regrddata;
//DEFINE_FUNC(riscv_core_reg_gen_rs2, "state, regrddata") {
always @(posedge wClk)
if (state == `RISCVSTATE_STORE_RS2)
rs2 <= regrddata;
//DEFINE_FUNC(riscv_core_gen_write, "nwReset, state, pc, instr, rs1, regrddata, imm") { //DEFINE_FUNC(riscv_core_gen_write, "nwReset, state, pc, instr, rs1, regrddata, imm") {
always @(posedge wClk) always @(posedge wClk)
if (!nwReset) begin if (!nwReset) begin
...@@ -221,18 +228,28 @@ module riscv_core( ...@@ -221,18 +228,28 @@ module riscv_core(
`RISCVSTATE_INIT_REGX2: state <= `RISCVSTATE_READ_INST; `RISCVSTATE_INIT_REGX2: state <= `RISCVSTATE_READ_INST;
`RISCVSTATE_READ_INST: state <= `RISCVSTATE_READ_RS1; `RISCVSTATE_READ_INST: state <= `RISCVSTATE_READ_RS1;
`RISCVSTATE_READ_RS1: state <= `RISCVSTATE_READ_RS2; `RISCVSTATE_READ_RS1: state <= `RISCVSTATE_READ_RS2;
`RISCVSTATE_READ_RS2: state <= `RISCVSTATE_EXEC_INST; `RISCVSTATE_READ_RS2: state <= `RISCVSTATE_STORE_RS2;
`RISCVSTATE_STORE_RS2: state <= `RISCVSTATE_EXEC_INST;
`RISCVSTATE_WRITE_RD: state <= `RISCVSTATE_READ_INST; `RISCVSTATE_WRITE_RD: state <= `RISCVSTATE_READ_INST;
`RISCVSTATE_EXEC_INST: begin `RISCVSTATE_EXEC_INST: begin
if (opcode == 5'h00) if (opcode == 5'h00)
state <= `RISCVSTATE_WAIT_LD; state <= `RISCVSTATE_WAIT_LD;
else if (opcode == 5'h08) else if (opcode == 5'h08)
state <= `RISCVSTATE_WAIT_ST; state <= `RISCVSTATE_WAIT_ST;
else else if (opcode == 5'h0c && instr[25] && func3[2]) begin
state <= `RISCVSTATE_WAIT_DIV;
divclk <= 11;
end else
state <= `RISCVSTATE_WRITE_RD; state <= `RISCVSTATE_WRITE_RD;
end end
`RISCVSTATE_WAIT_LD: state <= `RISCVSTATE_WRITE_RD; `RISCVSTATE_WAIT_LD: state <= `RISCVSTATE_WRITE_RD;
`RISCVSTATE_WAIT_ST: state <= `RISCVSTATE_READ_INST; `RISCVSTATE_WAIT_ST: state <= `RISCVSTATE_READ_INST;
`RISCVSTATE_WAIT_DIV: begin
if (divclk == 0)
state <= `RISCVSTATE_WRITE_RD;
else
divclk <= divclk - 1;
end
endcase endcase
end end
...@@ -345,6 +362,39 @@ module riscv_core( ...@@ -345,6 +362,39 @@ module riscv_core(
end end
endcase endcase
end end
`RISCVSTATE_WAIT_DIV: if (divclk == 0) begin
dstreg <= 0;
case (func3[1:0])
0: begin //div
dstreg <= rd;
if (rs2 == 0)
dstvalue <= 32'hffffffff;
else
dstvalue <= divs_result;
end
1: begin //divu
dstreg <= rd;
if (rs2 == 0)
dstvalue <= 32'hffffffff;
else
dstvalue <= div_result;
end
2: begin//rem
dstreg <= rd;
if (rs2 == 0)
dstvalue <= rs1;
else
dstvalue <= mods_result;
end
3: begin //remu
dstreg <= rd;
if (rs2 == 0)
dstvalue <= rs1;
else
dstvalue <= mod_result;
end
endcase
end
`RISCVSTATE_EXEC_INST: begin `RISCVSTATE_EXEC_INST: begin
dstreg <= rd; dstreg <= rd;
case (opcode) case (opcode)
...@@ -389,6 +439,24 @@ module riscv_core( ...@@ -389,6 +439,24 @@ module riscv_core(
3: begin //mulhu 3: begin //mulhu
dstvalue <= mul_result[63:32]; dstvalue <= mul_result[63:32];
end end
4: begin //div
dstreg <= 0;
dstvalue <= 0;//divs_result;
end
5: begin //divu
dstreg <= 0;
dstvalue <= 0;//div_result;
end
6: begin//rem
dstreg <= 0;
dstvalue <= 0;//mods_result;
end
7: begin //remu
dstreg <= 0;
dstvalue <= 0;//mod_result;
end
/*
4: begin //div 4: begin //div
if (rs2 == 0) if (rs2 == 0)
dstvalue <= 32'hffffffff; dstvalue <= 32'hffffffff;
...@@ -413,6 +481,7 @@ module riscv_core( ...@@ -413,6 +481,7 @@ module riscv_core(
else else
dstvalue <= mod_result; dstvalue <= mod_result;
end end
*/
endcase endcase
end else begin end else begin
case (func3) case (func3)
......
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