提交 e2dc5cc2 编写于 作者: 饶先宏's avatar 饶先宏

202108211245

上级 2534e874
......@@ -25,7 +25,7 @@ int main(int argc, char* argv[])
unsigned int* ledkey = (unsigned int*)0xF0000000;
unsigned int* leddata = (unsigned int*)0xf0000010;
count = 0;
ledata[0] = 0x3f3f3f3f;
leddata[0] = 0x3f3f3f3f;
do {
count++;
leddata[0] = num2seg(count) |
......@@ -42,4 +42,4 @@ int main(int argc, char* argv[])
((num2seg(count / 100000000000)) << 24);
} while (1);
return 1;
}
\ No newline at end of file
}
无法预览此类型文件
/*
** HDL4SE: 软件Verilog综合仿真平台
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
......@@ -31,7 +31,7 @@
/*
* cnncell_coeffbuf.c
修改记录:
修改记录:
202107061104: rxh, initial version
202107181003: rxh, macro version
*/
......@@ -49,7 +49,7 @@
#ifdef WIN32
#define DATADIR "d:/gitwork/hdl4se/examples/hdl4secnn/googlenet/model-data"
#else
#define DATADIR "/media/raoxianhong/_dde_data/gitwork/hdl4se/examples/hdl4secnn/googlenet/model-data"
#define DATADIR "/home/raoxianhong/work/gitwork/hdl4se/examples/hdl4secnn/googlenet/model-data"
#endif
#define M_ID(id) cnncell_coeffbuf##id
......
/*
** HDL4SE: 软件Verilog综合仿真平台
** HDL4SE: ����Verilog�ۺϷ���ƽ̨
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** LCOM: �������������ģ��
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
......@@ -31,7 +31,7 @@
/*
* cnncell_dataoutput.c
修改记录:
�޸ļ�¼��
202107061554: rxh, initial version
202107181103: rxh, macro version
*/
......@@ -50,7 +50,7 @@ static const char* labels[1000] = {
#ifdef WIN32
#include "d:/gitwork/hdl4se/examples/hdl4secnn/googlenet/model2verilog/imagenet-classes.txt"
#else
#include "/media/raoxianhong/_dde_data/gitwork/hdl4se/examples/hdl4secnn/googlenet/model2verilog/imagenet-classes.txt"
#include "/home/raoxianhong/work/gitwork/hdl4se/examples/hdl4secnn/googlenet/model2verilog/imagenet-classes.txt"
#endif
};
......
/*
** HDL4SE: 软件Verilog综合仿真平台
** HDL4SE: ����Verilog�ۺϷ���ƽ̨
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** LCOM: �������������ģ��
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
......@@ -31,7 +31,7 @@
/*
* cnncell_datasource.c
修改记录:
�޸ļ�¼��
202107050547: rxh, initial version
202107180941: rxh, macro version
*/
......@@ -45,11 +45,11 @@
#include "hdl4secell.h"
#include "threadlock.h"
/* 我们首先以keyboard数据作为测试数据 */
/* ����������keyboard�������������� */
#ifdef WIN32
#include "d:/gitwork/hdl4se/examples/hdl4secnn/googlenet/model2verilog/keyboard.txt"
#else
#include "/media/raoxianhong/_dde_data/gitwork/hdl4se/examples/hdl4secnn/googlenet/model2verilog/keyboard.txt"
#include "/home/raoxianhong/work/gitwork/hdl4se/examples/hdl4secnn/googlenet/model2verilog/keyboard.txt"
#endif
#define M_ID(id) cnncell_datasource##id
......@@ -84,7 +84,7 @@ DEFINE_FUNC(cnncell_datasource_gen_bDataWriteData, "cur_c, cur_h, cur_w") {
} END_DEFINE_FUNC
DEFINE_FUNC(cnncell_datasource_gen_cur_whc, "reset, complete, wDataWriteEnable, index, cur_c, cur_w, cur_h") {
if (vget(reset) == 0) {/* 低电平有效 */
if (vget(reset) == 0) {/* �͵�ƽ��Ч */
vput(index, 0);
vput(complete, 0);
vput(cur_w, 0);
......
/*
** HDL4SE: 软件Verilog综合仿真平台
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
......@@ -31,7 +31,7 @@
/*
* hdl4se_ram2p.c
修改记录:
修改记录:
202106101426: rxh, initial version
202107180708: rxh, initial version
*/
......
/*
** HDL4SE: 软件Verilog综合仿真平台
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
......@@ -31,10 +31,10 @@
/*
* hdl4se_reg.c
修改记录:
修改记录:
202105222048: rxh, initial version
202105241522:rxh, 增加Detector接口
202107180718:rxh, macro version
202105241522:rxh, 增加Detector接口
202107180718:rxh, macro version
*/
#include "stdlib.h"
#include "stdio.h"
......
/*
** HDL4SE: 软件Verilog综合仿真平台
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
......@@ -31,7 +31,7 @@
/*
* hdl4se_general.c
修改记录:
修改记录:
202107140531: rxh, initial version
*/
......@@ -137,7 +137,7 @@ int vartempInit()
int vartempClean()
{
/* 将所有正在使用的临时变量移动到空闲表中去 */
/* 将所有正在使用的临时变量移动到空闲表中去 */
threadlockLock(tempvar_lock);
if (tempvar_using_list.pNext != &tempvar_using_list) {
tempvar_using_list.pNext->pLast = tempvar_list.pLast;
......@@ -156,14 +156,14 @@ ModuleVariable* varTemp(int width, int isunsigned)
ModuleVariable* temp;
threadlockLock(tempvar_lock);
if (tempvar_list.pNext == &tempvar_list) {
/* 空闲的临时变量表为空,此时新生成一个 */
/* 空闲的临时变量表为空,此时新生成一个 */
temp = variableCreate(VTYPE_TEMP, width, 0, isunsigned, "");
if (temp != NULL) {
newtempvarcount++;
}
}
else {
/* 空闲表非空,取一个下来 */
/* 空闲表非空,取一个下来 */
temp = tempvar_list.pNext;
temp->pNext->pLast = temp->pLast;
temp->pLast->pNext = temp->pNext;
......@@ -174,7 +174,7 @@ ModuleVariable* varTemp(int width, int isunsigned)
objectCall1(temp->data, SetUnsigned, isunsigned);
#endif
}
/* 加入到正在使用的表中 */
/* 加入到正在使用的表中 */
temp->pLast = &tempvar_using_list;
temp->pNext = tempvar_using_list.pNext;
temp->pLast->pNext = temp;
......
......@@ -241,7 +241,7 @@ static int hdl4sesim_hdl4se_simulator_SetReset(HOBJECT object, int reset)
return 0;
}
#define THREADCOUNT 3
#define THREADCOUNT 9
static int hdl4sesim_hdl4se_simulator_ClkTick(HOBJECT object)
{
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册