Add taihu bsp (PPC405)

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2350 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/taihu/SConscript

+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/taihu/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-taihu.' + rtconfig.TARGET_EXT
+cwd = GetCurrentDir()
+
+# add include path for asm
+rtconfig.AFLAGS = rtconfig.AFLAGS + ' -I' + RTT_ROOT + '/libcpu/ppc/ppc405/include '
+rtconfig.CFLAGS = rtconfig.CFLAGS + ' -I' + RTT_ROOT + '/libcpu/ppc/ppc405/include '
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# build program 
+DoBuilding(TARGET, objs)

bsp/taihu/applications/SConscript

+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd, Dir('#')]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/taihu/applications/application.c

+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-04-16         first version
+ */
+
+#include <rtthread.h>
+
+#define THREAD_STACK_SIZE	1024
+
+#if 0
+struct rt_semaphore sem1, sem2;
+static struct rt_thread thread1;
+ALIGN(4)
+static rt_uint8_t thread1_stack[THREAD_STACK_SIZE];
+static struct rt_thread thread2;
+ALIGN(4)
+static rt_uint8_t thread2_stack[THREAD_STACK_SIZE];
+
+static void thread1_entry(void* parameter)
+{
+	while (1)
+	{
+		rt_sem_release(&sem2);
+		rt_kprintf("thread1..: %s\n", rt_thread_self()->name);
+		rt_sem_take(&sem1, RT_WAITING_FOREVER);
+		rt_kprintf("get semaphore: %s!\n", rt_thread_self()->name);
+	}
+}
+
+static void thread2_entry(void* parameter)
+{
+	while (1)
+	{
+		rt_sem_take(&sem2, RT_WAITING_FOREVER);
+		rt_kprintf("thread2--->: %s\n", rt_thread_self()->name);
+		rt_sem_release(&sem1);
+	}
+}
+
+/* user application */
+int rt_application_init()
+{
+	rt_err_t result;
+
+	rt_sem_init(&sem1, "s1", 0, RT_IPC_FLAG_FIFO);
+	rt_sem_init(&sem2, "s2", 0, RT_IPC_FLAG_FIFO);
+
+	result = rt_thread_init(&thread1, "t1",	thread1_entry, RT_NULL,
+		&thread1_stack[0], sizeof(thread1_stack), 10, 10);
+	if (result == RT_EOK)
+		rt_thread_startup(&thread1);
+
+	result = rt_thread_init(&thread2, "t2", thread2_entry, RT_NULL,
+		&thread2_stack[0], sizeof(thread2_stack), 18, 10);
+	if (result == RT_EOK)
+		rt_thread_startup(&thread2);
+
+	return 0;
+}
+#else
+static struct rt_thread thread1;
+ALIGN(4)
+static rt_uint8_t thread1_stack[THREAD_STACK_SIZE];
+rt_timer_t ttimer;
+
+static void thread1_entry(void* parameter)
+{
+	rt_uint32_t count = 0;
+	while (1)
+	{
+		rt_kprintf("%s: count = %d\n", rt_thread_self()->name, count ++);
+
+		rt_thread_delay(10);
+	}
+}
+
+/* user application */
+int rt_application_init()
+{
+	rt_err_t result;
+
+	result = rt_thread_init(&thread1, "t1",	thread1_entry, RT_NULL,
+		&thread1_stack[0], sizeof(thread1_stack), 10, 10);
+
+	ttimer = &(thread1.thread_timer);
+	if (result == RT_EOK)
+		rt_thread_startup(&thread1);
+
+	return 0;
+}
+#endif

bsp/taihu/applications/board.c

+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-04-16         first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "board.h"
+
+void rt_hw_board_init()
+{
+	rt_hw_serial_init();
+	rt_console_set_device("uart1");
+}

bsp/taihu/applications/board.h

+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-04-16         first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+void rt_hw_board_init(void);
+
+#endif

bsp/taihu/applications/startup.c

+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-04-16     nsj          first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+extern void finsh_system_init(void);
+#endif
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_DEVICE
+extern rt_err_t rt_hw_serial_init(void);
+#endif
+
+extern int __heap_start;
+extern int __heap_end;
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init hardware interrupt */
+	rt_hw_interrupt_init();
+
+	/* init board */
+	rt_hw_board_init();
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+	/* init memory system */
+#ifdef RT_USING_HEAP
+	rt_system_heap_init((void*)&__heap_start, (void*)&__heap_end);
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device("uart1");
+#endif
+
+	/* init soft timer thread */
+	rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}

bsp/taihu/rtconfig.h

+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX	32
+#define IDLE_THREAD_STACK_SIZE	1024
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND	100
+/* CPU Frequency 200MHz */
+#define RT_CPU_FREQ			200
+
+/* SECTION: RT_DEBUG */
+/* open debug for system assert */
+// #define RT_DEBUG
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+/* #define RT_SCHEDULER_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+
+// #define RT_USING_NOLIBC
+#define RT_TINY_SIZE
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+#define RT_UART_RX_BUFFER_SIZE	64
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* #define RT_USING_LWIP */
+/* LwIP uses RT-Thread Memory Management */
+#define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+#endif

bsp/taihu/rtconfig.py

+# toolchains options
+ARCH='ppc'
+CPU='ppc405'
+CROSS_TOOL='gcc'
+TextBase = '0x00000000'
+
+PLATFORM = 'gcc'
+EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'powerpc-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=405 -mno-multiple -mno-string -mno-update -fno-exceptions -fno-builtin -msoft-float'
+
+    CFLAGS = DEVICE + ' -D__KERNEL__'
+    AFLAGS = '-D__ASSEMBLY__ -fno-exceptions  -fno-builtin  -mregnames -c -Wall -Xassembler -m405 -msoft-float -ffunction-sections'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,--cref,-Map=rtthread.map -T taihu.lds' + ' -Ttext=' + TextBase
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    DASM_ACTION = OBJDUMP + ' -d rtthread-taihu.elf > rtt.asm\n'
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' # + DASM_ACTION

bsp/taihu/taihu.lds

+OUTPUT_ARCH(powerpc)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)           }
+  .dynsym        : { *(.dynsym)         }
+  .dynstr        : { *(.dynstr)         }
+  .rel.text      : { *(.rel.text)       }
+  .rela.text     : { *(.rela.text)      }
+  .rel.data      : { *(.rel.data)       }
+  .rela.data     : { *(.rela.data)      }
+  .rel.rodata    : { *(.rel.rodata)     }
+  .rela.rodata   : { *(.rela.rodata)    }
+  .rel.got       : { *(.rel.got)        }
+  .rela.got      : { *(.rela.got)       }
+  .rel.ctors     : { *(.rel.ctors)      }
+  .rela.ctors    : { *(.rela.ctors)     }
+  .rel.dtors     : { *(.rel.dtors)      }
+  .rela.dtors    : { *(.rela.dtors)     }
+  .rel.bss       : { *(.rel.bss)        }
+  .rela.bss      : { *(.rela.bss)       }
+  .rel.plt       : { *(.rel.plt)        }
+  .rela.plt      : { *(.rela.plt)       }
+  /* .init          : { *(.init)           } */
+  .plt : { *(.plt) }
+
+  .text      :
+  {
+    KEEP(build\libcpu\ppc\ppc405\start_gcc.o (.text))
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  __bss_end = .;
+
+  . = ALIGN(256);
+
+  PROVIDE(__stack_bottom = .);
+  . += 0x100000; /* 1MB */
+  PROVIDE(__stack_top = .);
+
+  . = ALIGN(256);
+  PROVIDE (__heap_start = .);
+  . += 0x500000; /* 5MB */
+  PROVIDE(__heap_end = .);
+
+  _end = . ;
+  PROVIDE (end = .);
+}

libcpu/ppc/common/ptrace.h

+#ifndef _PPC_PTRACE_H
+#define _PPC_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below.  This simplifies arch/ppc/kernel/ptrace.c.
+ */
+
+#ifndef __ASSEMBLY__
+#define PPC_REG unsigned long
+
+struct pt_regs {
+	PPC_REG gpr[32];
+	PPC_REG nip;
+	PPC_REG msr;
+	PPC_REG orig_gpr3;	/* Used for restarting system calls */
+	PPC_REG ctr;
+	PPC_REG link;
+	PPC_REG xer;
+	PPC_REG ccr;
+	PPC_REG mq;		/* 601 only (not used at present) */
+				    /* Used on APUS to hold IPL value. */
+	PPC_REG trap;		/* Reason for being here */
+	PPC_REG dar;		/* Fault registers */
+	PPC_REG dsisr;
+	PPC_REG result;		/* Result of a system call */
+}__attribute__((packed)) CELL_STACK_FRAME_t;
+#endif
+
+#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE	64
+
+#define instruction_pointer(regs) ((regs)->nip)
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+#define PT_R26	26
+#define PT_R27	27
+#define PT_R28	28
+#define PT_R29	29
+#define PT_R30	30
+#define PT_R31	31
+
+#define PT_NIP	32
+#define PT_MSR	33
+#define PT_ORIG_R3 34
+#define PT_CTR	35
+#define PT_LNK	36
+#define PT_XER	37
+#define PT_CCR	38
+#define PT_MQ	39
+
+#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#endif

libcpu/ppc/common/stack.c

+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-14     Fred         first implementation for 
+ */
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup PowerPC
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+    rt_uint8_t *stack_addr, void *texit)
+{
+    unsigned long *stk;
+    rt_uint32_t msr;
+
+    __asm__ __volatile__("mfmsr %0\n" : "=r" (msr));
+    msr |= 0x00028000;
+
+    stk      = (unsigned long *)stack_addr;
+    --stk;
+    *(--stk) = msr;                 /* srr0: machine status register */
+    *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */
+    *(--stk) = (rt_uint32_t)texit;  /* lr: link register */
+    *(--stk) = 0x0F0F0F0F;          /* ctr: counter register */
+    *(--stk) = 0x0F0F0F0F;          /* xer: fixed-point exception register */
+    *(--stk) = 0x0F0F0F0F;          /* cr : condition register */
+    *(--stk) = 0x00;                /* usprg0 */
+
+    *(--stk) = 0x31;            /* r31 */
+    *(--stk) = 0x30;            /* r30 */
+    *(--stk) = 0x29;            /* r29 */
+    *(--stk) = 0x28;            /* r28 */
+    *(--stk) = 0x27;            /* r27 */
+    *(--stk) = 0x26;            /* r26 */
+    *(--stk) = 0x25;            /* r25 */
+    *(--stk) = 0x24;            /* r24 */
+    *(--stk) = 0x23;            /* r23 */
+    *(--stk) = 0x22;            /* r22 */
+    *(--stk) = 0x21;            /* r21 */
+    *(--stk) = 0x20;            /* r20 */
+    *(--stk) = 0x19;            /* r19 */
+    *(--stk) = 0x18;            /* r18 */
+    *(--stk) = 0x17;            /* r17 */
+    *(--stk) = 0x16;            /* r16 */
+    *(--stk) = 0x15;            /* r15 */
+    *(--stk) = 0x14;            /* r14 */
+    *(--stk) = 0x13;            /* r13: thread id */
+    *(--stk) = 0x12;            /* r12 */
+    *(--stk) = 0x11;            /* r11 */
+    *(--stk) = 0x10;            /* r10 */
+    *(--stk) = 0x09;            /* r09 */
+    *(--stk) = 0x08;            /* r08 */
+    *(--stk) = 0x07;            /* r07 */
+    *(--stk) = 0x06;            /* r06 */
+    *(--stk) = 0x05;            /* r05 */
+    *(--stk) = 0x04;            /* r04 */
+    *(--stk) = (rt_uint32_t)parameter;  /* r03: parameter and return  */
+    *(--stk) = 0x02;            /* r02: toc */
+                                /* r01: sp */
+    *(--stk) = 0x0;             /* r00 */
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
+/*@}*/

libcpu/ppc/ppc405/cache.h

+#ifndef __CACHE_H__
+#define __CACHE_H__
+
+#include <asm/processor.h>
+
+#if !defined(__ASSEMBLY__)
+void flush_dcache_range(unsigned long start, unsigned long stop);
+void clean_dcache_range(unsigned long start, unsigned long stop);
+void invalidate_dcache_range(unsigned long start, unsigned long stop);
+void flush_dcache(void);
+void invalidate_dcache(void);
+void invalidate_icache(void);
+
+void icache_enable(void);
+void icache_disable(void);
+unsigned long icache_status(void);
+
+void dcache_enable(void);
+void dcache_disable(void);
+unsigned long dcache_status(void);
+#endif
+
+#endif

libcpu/ppc/ppc405/cache_gcc.S

+#define	L1_CACHE_SHIFT		5
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+#define DCACHE_SIZE		(16 << 10)/* For AMCC 405 CPUs	*/
+
+/*
+ * Flush instruction cache.
+ */
+	.globl invalidate_icache
+invalidate_icache:
+	iccci	r0,r0
+	isync
+	blr
+
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ *
+ * flush_icache_range(unsigned long start, unsigned long stop)
+ */
+	.globl flush_icache_range
+flush_icache_range:
+	li	r5,L1_CACHE_BYTES-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,L1_CACHE_SHIFT
+	beqlr
+	mtctr	r4
+	mr	r6,r3
+1:	dcbst	0,r3
+	addi	r3,r3,L1_CACHE_BYTES
+	bdnz	1b
+	sync				/* wait for dcbst's to get to ram */
+	mtctr	r4
+2:	icbi	0,r6
+	addi	r6,r6,L1_CACHE_BYTES
+	bdnz	2b
+	sync				/* additional sync needed on g4 */
+	isync
+	blr
+
+/*
+ * Write any modified data cache blocks out to memory.
+ * Does not invalidate the corresponding cache lines (especially for
+ * any corresponding instruction cache).
+ *
+ * clean_dcache_range(unsigned long start, unsigned long stop)
+ */
+	.globl clean_dcache_range
+clean_dcache_range:
+	li	r5,L1_CACHE_BYTES-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,L1_CACHE_SHIFT
+	beqlr
+	mtctr	r4
+
+1:	dcbst	0,r3
+	addi	r3,r3,L1_CACHE_BYTES
+	bdnz	1b
+	sync				/* wait for dcbst's to get to ram */
+	blr
+
+/*
+ * Write any modified data cache blocks out to memory and invalidate them.
+ * Does not invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+	.globl flush_dcache_range
+flush_dcache_range:
+	li	r5,L1_CACHE_BYTES-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,L1_CACHE_SHIFT
+	beqlr
+	mtctr	r4
+
+1:	dcbf	0,r3
+	addi	r3,r3,L1_CACHE_BYTES
+	bdnz	1b
+	sync				/* wait for dcbst's to get to ram */
+	blr
+
+/*
+ * Like above, but invalidate the D-cache.  This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+	.globl invalidate_dcache_range
+invalidate_dcache_range:
+	li	r5,L1_CACHE_BYTES-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,L1_CACHE_SHIFT
+	beqlr
+	mtctr	r4
+
+1:	dcbi	0,r3
+	addi	r3,r3,L1_CACHE_BYTES
+	bdnz	1b
+	sync				/* wait for dcbi's to get to ram */
+	blr
+
+/*
+ * 40x cores have 8K or 16K dcache and 32 byte line size.
+ * 44x has a 32K dcache and 32 byte line size.
+ * 8xx has 1, 2, 4, 8K variants.
+ * For now, cover the worst case of the 44x.
+ * Must be called with external interrupts disabled.
+ */
+#define CACHE_NWAYS     64
+#define CACHE_NLINES    32
+
+	.globl flush_dcache
+flush_dcache:
+	li	r4,(2 * CACHE_NWAYS * CACHE_NLINES)
+	mtctr	r4
+	lis	r5,0
+1:	lwz	r3,0(r5)		/* Load one word from every line */
+	addi	r5,r5,L1_CACHE_BYTES
+	bdnz	1b
+	sync
+	blr
+
+	.globl invalidate_dcache
+invalidate_dcache:
+	addi	r6,0,0x0000		/* clear GPR 6 */
+	/* Do loop for # of dcache congruence classes. */
+	lis	r7,(DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha	/* TBS for large sized cache */
+	ori	r7,r7,(DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
+					/* NOTE: dccci invalidates both */
+	mtctr	r7			/* ways in the D cache */
+dcloop:
+	dccci	0,r6			/* invalidate line */
+	addi	r6,r6,L1_CACHE_BYTES	/* bump to next line */
+	bdnz	dcloop
+	sync
+	blr
+
+/*
+ * Cache functions.
+ *
+ * Icache-related functions are used in POST framework.
+ */
+	.globl	icache_enable
+icache_enable:
+	mflr	r8
+	bl	invalidate_icache
+	mtlr	r8
+	isync
+	addis	r3,r0, 0xc000	      /* set bit 0 */
+	mticcr	r3
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	addis	r3,r0, 0x0000	      /* clear bit 0 */
+	mticcr	r3
+	isync
+	blr
+
+	.globl	icache_status
+icache_status:
+	mficcr	r3
+	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	blr
+
+	.globl	dcache_enable
+dcache_enable:
+	mflr	r8
+	bl	invalidate_dcache
+	mtlr	r8
+	isync
+	addis	r3,r0, 0x8000	      /* set bit 0 */
+	mtdccr	r3
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	mflr	r8
+	bl	flush_dcache
+	mtlr	r8
+	addis	r3,r0, 0x0000	      /* clear bit 0 */
+	mtdccr	r3
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfdccr	r3
+	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	blr

libcpu/ppc/ppc405/context.h

+#ifndef __CONTEXT_H__
+#define __CONTEXT_H__
+
+#define MSR_ME		(1<<12)		/* Machine Check Enable */
+#define MSR_EE      (1<<15)     /* External Interrupt Enable */
+#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */
+
+#define GPR0    0
+#define GPR2    4
+#define GPR3    8
+#define GPR4    12
+#define GPR5    16
+#define GPR6    20
+#define GPR7    24
+#define GPR8    28
+#define GPR9    32
+#define GPR10   36
+#define GPR11   40
+#define GPR12   44
+#define GPR13   48
+#define GPR14   52
+#define GPR15   56
+#define GPR16   60
+#define GPR17   64
+#define GPR18   68
+#define GPR19   72
+#define GPR20   76
+#define GPR21   80
+#define GPR22   84
+#define GPR23   88
+#define GPR24   92
+#define GPR25   96
+#define GPR26   100
+#define GPR27   104
+#define GPR28   108
+#define GPR29   112
+#define GPR30   116
+#define GPR31   120
+#define USPRG0  (GPR31 + 4)
+#define CR      (USPRG0 + 4)
+#define XER     (CR + 4)
+#define CTR     (XER + 4)
+#define LR      (CTR + 4)
+#define SRR0    (LR + 4)
+#define SRR1    (SRR0 + 4)
+#define STACK_FRAME_SIZE (SRR1 + 4)
+
+#endif

libcpu/ppc/ppc405/context_gcc.S

+#include "context.h"
+#define SPRG0	0x110	/* Special Purpose Register General 0 */
+#define SPRG1	0x111	/* Special Purpose Register General 1 */
+
+    .globl rt_hw_interrupt_disable
+    .globl rt_hw_interrupt_enable
+    .globl rt_hw_context_switch
+    .globl rt_hw_context_switch_to
+    .globl rt_hw_context_switch_interrupt
+    .globl rt_hw_systemcall_entry
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ * return the interrupt status and disable interrupt
+ */
+#if 0
+rt_hw_interrupt_disable:
+    mfmsr   r3          /* Disable interrupts */
+    li      r4,0
+    ori     r4,r4,MSR_EE
+    andc    r4,r4,r3
+    SYNC                /* Some chip revs need this... */
+    mtmsr   r4
+    SYNC
+    blr
+#else
+rt_hw_interrupt_disable:
+    addis  r4, r0, 0xFFFD
+    ori    r4, r4, 0x7FFF
+    mfmsr  r3
+    and    r4, r4, 3                                      /* Clear bits 14 and 16, corresponding to...   */
+    mtmsr  r4                                            /* ...critical and non-critical interrupts     */
+    blr
+#endif
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ * restore interrupt
+ */
+rt_hw_interrupt_enable:
+    mtmsr   r3
+    SYNC
+    blr
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r3 --> from
+ * r4 --> to
+ *
+ * r1: stack pointer
+ */
+rt_hw_systemcall_entry:
+    mtspr   SPRG0,r3                            /* save r3 to SPRG0 */
+    mtspr   SPRG1,r4                            /* save r4 to SPRG1 */
+
+    lis     r3,rt_thread_switch_interrput_flag@h
+    ori     r3,r3,rt_thread_switch_interrput_flag@l
+    lwz     r4,0(r3)
+    cmpi    cr0,0,r4,0x0                        /* whether is 0     */
+    beq     _no_switch                          /* no switch, exit  */
+    li      r4,0x0                              /* set rt_thread_switch_interrput_flag to 0 */
+    stw     r4,0(r3)
+
+    /* load from thread to r3 */
+    lis     r3,rt_interrupt_from_thread@h       /* set rt_interrupt_from_thread */
+    ori     r3,r3,rt_interrupt_from_thread@l
+    lwz     r3,0(r3)
+
+    cmpi    cr0,0,r3,0x0                        /* whether is 0 */
+    beq     _restore                            /* it's first switch, goto _restore */
+
+    /* save r1:sp to thread[from] stack pointer */
+    subi    r1, r1, STACK_FRAME_SIZE
+    stw     r1, 0(r3)
+
+    /* restore r3, r4 from SPRG */
+    mfspr   r3,SPRG0
+    mfspr   r4,SPRG0
+
+    /* save registers   */
+    stw     r0,GPR0(r1)                         /* save general purpose registers 0    */
+    stmw    r2,GPR2(r1)                         /* save general purpose registers 2-31 */
+
+    mfusprg0 r0                                 /* save usprg0  */
+    stw     r0,USPRG0(r1)
+    mfcr    r0,                                 /* save cr      */
+    stw     r0,CR(r1)
+    mfxer   r0                                  /* save xer     */
+    stw     r0,XER(r1)
+    mfctr   r0                                  /* save ctr     */
+    stw     r0,CTR(r1)
+    mflr    r0                                  /* save lr      */
+    stw     r0, LR(r1)
+
+    mfsrr0  r0                                  /* save SRR0 and SRR1   */
+    stw     r0,SRR0(r1)
+    mfsrr1  r0
+    stw     r0,SRR1(r1)
+
+_restore:
+    /* get thread[to] stack pointer */
+    lis     r4,rt_interrupt_to_thread@h
+    ori     r4,r4,rt_interrupt_to_thread@l
+    lwz     r1,0(r4)
+    lwz     r1,0(r1)
+
+    lwz     r0,SRR1(r1)                         /* restore SRR1 and SRR0   */
+    mtsrr1  r0
+    lwz     r0,SRR0(r1)
+    mtsrr0  r0
+
+    lwz     r0,LR(r1)                           /* restore lr       */
+    mtlr    r0
+    lwz     r0,CTR(r1)                          /* restore ctr     */
+    mtctr   r0
+    lwz     r0,XER(r1)                          /* restore xer     */
+    mtxer   r0
+    lwz     r0,CR(r1)                           /* restore cr      */
+    mtcr    r0
+    lwz     r0,USPRG0(r1)                       /* restore usprg0  */
+    // mtusprg0 r0
+
+    lmw     r2, GPR2(r1)                        /* restore general register */
+    lwz     r0,GPR0(r1)
+    addi    r1, r1, STACK_FRAME_SIZE
+    /* RFI will restore status register and thus the correct priority*/
+    rfi
+
+_no_switch:
+    /* restore r3, r4 from SPRG */
+    mfspr   r3,SPRG0
+    mfspr   r4,SPRG0
+    rfi
+
+    /* void rt_hw_context_switch_to(to); */
+    .globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    /* set rt_thread_switch_interrput_flag = 1 */
+    lis     r5,rt_thread_switch_interrput_flag@h
+    ori     r5,r5,rt_thread_switch_interrput_flag@l
+    li      r6, 0x01
+    stw     r6,0(r5)
+
+    /* set rt_interrupt_from_thread = 0 */
+    lis     r5,rt_interrupt_from_thread@h
+    ori     r5,r5,rt_interrupt_from_thread@l
+    li      r6, 0x00
+    stw     r6,0(r5)
+
+    /* set rt_interrupt_from_thread = to */
+    lis     r5,rt_interrupt_to_thread@h
+    ori     r5,r5,rt_interrupt_to_thread@l
+    stw     r3,0(r5)
+
+    /* trigger a system call */
+    sc
+
+    blr
+
+    /* void rt_hw_context_switch(from, to); */
+    .globl rt_hw_context_switch
+rt_hw_context_switch:
+    /* compare rt_thread_switch_interrupt_flag and set it */
+    lis     r5,rt_thread_switch_interrput_flag@h
+    ori     r5,r5,rt_thread_switch_interrput_flag@l
+    lwz     r6,0(r5)
+    cmpi    cr0,0,r6,0x1                        /* whether is 1 */
+    beq     _reswitch                           /* set already, goto _reswitch */
+    li      r6,0x1                              /* set rt_thread_switch_interrput_flag to 1*/
+    stw     r6,0(r5)
+
+    /* set rt_interrupt_from_thread to 'from' */
+    lis     r5,rt_interrupt_from_thread@h
+    ori     r5,r5,rt_interrupt_from_thread@l
+    stw     r3,0(r5)
+
+_reswitch:
+    /* set rt_interrupt_to_thread to 'to' */
+    lis     r6,rt_interrupt_to_thread@h
+    ori     r6,r6,rt_interrupt_to_thread@l
+    stw     r4,0(r6)
+
+    /* trigger a system call */
+    sc
+
+    blr
+
+    .globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    /* compare rt_thread_switch_interrupt_flag and set it */
+    lis     r5,rt_thread_switch_interrput_flag@h
+    ori     r5,r5,rt_thread_switch_interrput_flag@l
+    lwz     r6,0(r5)
+    cmpi    cr0,0,r6,0x1                        /* whether is 1 */
+    beq     _int_reswitch                       /* set already, goto _reswitch */
+    li      r6,0x1                              /* set rt_thread_switch_interrput_flag to 1*/
+    stw     r6,0(r5)
+
+    /* set rt_interrupt_from_thread to 'from' */
+    lis     r5,rt_interrupt_from_thread@h
+    ori     r5,r5,rt_interrupt_from_thread@l
+    stw     r3,0(r5)
+
+_int_reswitch:
+    /* set rt_interrupt_to_thread to 'to' */
+    lis     r6,rt_interrupt_to_thread@h
+    ori     r6,r6,rt_interrupt_to_thread@l
+    stw     r4,0(r6)
+
+    blr

libcpu/ppc/ppc405/dcr_gcc.S

+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/ppc4xx.h>
+
+/*****************************************************************************
+ *
+ *  XXX - DANGER
+ *        These routines make use of self modifying code.  DO NOT CALL THEM
+ *	  UNTIL THEY ARE RELOCATED TO RAM.  Additionally, I do not
+ *	  recommend them for use in anything other than an interactive
+ *        debugging environment.  This is mainly due to performance reasons.
+ *
+ ****************************************************************************/
+
+/*
+ * static void _create_MFDCR(unsigned short dcrn)
+ *
+ * Builds a 'mfdcr' instruction for get_dcr
+ * function.
+ */
+		.section ".text"
+		.align 2
+		.type	 _create_MFDCR,@function
+_create_MFDCR:
+		/*
+		 * Build up a 'mfdcr' instruction formatted as follows:
+		 *
+		 *  OPCD |   RT   |    DCRF      |     XO       | CR |
+		 * ---------------|--------------|--------------|----|
+		 * 0   5 | 6   10 | 11        20 | 21        30 | 31 |
+		 *       |        |    DCRN      |              |    |
+		 *   31  |  %r3   | (5..9|0..4)  |      323     |  0 |
+		 *
+		 * Where:
+		 *	OPCD = opcode - 31
+		 *	RT   = destination register - %r3 return register
+		 *	DCRF = DCRN # with upper and lower halves swapped
+		 *	XO   = extended opcode - 323
+		 *	CR   = CR[CR0] NOT undefined - 0
+		 */
+		rlwinm	r0, r3, 27, 27, 31	/* OPCD = 31 */
+		rlwinm	r3, r3, 5, 22, 26
+		or	r3, r3, r0
+		slwi	r3, r3, 10
+		oris	r3, r3, 0x3e30		/* RT = %r3 */
+		ori	r3, r3, 323		/* XO = 323 */
+		slwi	r3, r3, 1		/* CR = 0 */
+
+		mflr	r4
+		stw	r3, 0(r4)		/* Store instr in get_dcr() */
+		dcbst	r0, r4			/* Make sure val is written out */
+		sync				/* Wait for write to complete */
+		icbi	r0, r4			/* Make sure old instr is dumped */
+		isync				/* Wait for icbi to complete */
+
+		blr
+.Lfe1:		.size	 _create_MFDCR,.Lfe1-_create_MFDCR
+/* end _create_MFDCR() */
+
+/*
+ * static void _create_MTDCR(unsigned short dcrn, unsigned long value)
+ *
+ * Builds a 'mtdcr' instruction for set_dcr
+ * function.
+ */
+		.section ".text"
+		.align 2
+		.type	 _create_MTDCR,@function
+_create_MTDCR:
+		/*
+		 * Build up a 'mtdcr' instruction formatted as follows:
+		 *
+		 *  OPCD |   RS   |    DCRF      |     XO       | CR |
+		 * ---------------|--------------|--------------|----|
+		 * 0   5 | 6   10 | 11        20 | 21        30 | 31 |
+		 *       |        |    DCRN      |              |    |
+		 *   31  |  %r3   | (5..9|0..4)  |      451     |  0 |
+		 *
+		 * Where:
+		 *	OPCD = opcode - 31
+		 *	RS   = source register - %r4
+		 *	DCRF = dest. DCRN # with upper and lower halves swapped
+		 *	XO   = extended opcode - 451
+		 *	CR   = CR[CR0] NOT undefined - 0
+		 */
+		rlwinm	r0, r3, 27, 27, 31	/* OPCD = 31 */
+		rlwinm	r3, r3, 5, 22, 26
+		or	r3, r3, r0
+		slwi	r3, r3, 10
+		oris	r3, r3, 0x3e40		/* RS = %r4 */
+		ori	r3, r3, 451		/* XO = 451 */
+		slwi	r3, r3, 1		/* CR = 0 */
+
+		mflr	r5
+		stw	r3, 0(r5)		/* Store instr in set_dcr() */
+		dcbst	r0, r5			/* Make sure val is written out */
+		sync				/* Wait for write to complete */
+		icbi	r0, r5			/* Make sure old instr is dumped */
+		isync				/* Wait for icbi to complete */
+
+		blr
+.Lfe2:		.size	 _create_MTDCR,.Lfe2-_create_MTDCR
+/* end _create_MTDCR() */
+
+
+/*
+ * unsigned long get_dcr(unsigned short dcrn)
+ *
+ * Return a given DCR's value.
+ */
+		/* */
+		/* XXX - This is self modifying code, hence */
+		/* it is in the data section. */
+		/* */
+		.section ".text"
+		.align	2
+		.globl	get_dcr
+		.type	get_dcr,@function
+get_dcr:
+		mflr	r0			/* Get link register */
+		stwu	r1, -32(r1)		/* Save back chain and move SP */
+		stw	r0, +36(r1)		/* Save link register */
+
+		bl	_create_MFDCR		/* Build following instruction */
+		/* XXX - we build this instuction up on the fly. */
+		.long	0			/* Get DCR's value */
+
+		lwz	r0, +36(r1)		/* Get saved link register */
+		mtlr	r0			/* Restore link register */
+		addi	r1, r1, +32		/* Remove frame from stack */
+		blr				/* Return to calling function */
+.Lfe3:		.size	get_dcr,.Lfe3-get_dcr
+/* end get_dcr() */
+
+
+/*
+ * unsigned void set_dcr(unsigned short dcrn, unsigned long value)
+ *
+ * Return a given DCR's value.
+ */
+		/*
+		 * XXX - This is self modifying code, hence
+		 * it is in the data section.
+		 */
+		.section ".text"
+		.align	2
+		.globl	set_dcr
+		.type	set_dcr,@function
+set_dcr:
+		mflr	r0			/* Get link register */
+		stwu	r1, -32(r1)		/* Save back chain and move SP */
+		stw	r0, +36(r1)		/* Save link register */
+
+		bl	_create_MTDCR		/* Build following instruction */
+		/* XXX - we build this instuction up on the fly. */
+		.long	0			/* Set DCR's value */
+
+		lwz	r0, +36(r1)		/* Get saved link register */
+		mtlr	r0			/* Restore link register */
+		addi	r1, r1, +32		/* Remove frame from stack */
+		blr				/* Return to calling function */
+.Lfe4:		.size	set_dcr,.Lfe4-set_dcr
+/* end set_dcr() */
+

libcpu/ppc/ppc405/include/asm/ppc4xx-intvec.h

+#ifndef _VECNUMS_H_
+#define _VECNUMS_H_
+
+#define VECNUM_U0           0           /* UART0                        */
+#define VECNUM_U1           1           /* UART1                        */
+#define VECNUM_D0           5           /* DMA channel 0                */
+#define VECNUM_D1           6           /* DMA channel 1                */
+#define VECNUM_D2           7           /* DMA channel 2                */
+#define VECNUM_D3           8           /* DMA channel 3                */
+#define VECNUM_EWU0         9           /* Ethernet wakeup              */
+#define VECNUM_MS           10          /* MAL SERR                     */
+#define VECNUM_MTE          11          /* MAL TXEOB                    */
+#define VECNUM_MRE          12          /* MAL RXEOB                    */
+#define VECNUM_TXDE         13          /* MAL TXDE                     */
+#define VECNUM_RXDE         14          /* MAL RXDE                     */
+#define VECNUM_ETH0         15          /* Ethernet interrupt status    */
+#define VECNUM_EIR0         25          /* External interrupt 0         */
+#define VECNUM_EIR1         26          /* External interrupt 1         */
+#define VECNUM_EIR2         27          /* External interrupt 2         */
+#define VECNUM_EIR3         28          /* External interrupt 3         */
+#define VECNUM_EIR4         29          /* External interrupt 4         */
+#define VECNUM_EIR5         30          /* External interrupt 5         */
+#define VECNUM_EIR6         31          /* External interrupt 6         */
+
+#endif /* _VECNUMS_H_ */

libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h

+#ifndef _PPC4xx_UIC_H_
+#define _PPC4xx_UIC_H_
+
+/*
+ * Define the number of UIC's
+ */
+#define UIC_MAX		1
+#define IRQ_MAX		UIC_MAX * 32
+
+/* UIC0 dcr base address */
+#define UIC0_DCR_BASE 0xc0
+
+/*
+ * UIC register
+ */
+#define UIC_SR	0x0			/* UIC status			*/
+#define UIC_ER	0x2			/* UIC enable			*/
+#define UIC_CR	0x3			/* UIC critical			*/
+#define UIC_PR	0x4			/* UIC polarity			*/
+#define UIC_TR	0x5			/* UIC triggering		*/
+#define UIC_MSR 0x6			/* UIC masked status		*/
+#define UIC_VR	0x7			/* UIC vector			*/
+#define UIC_VCR 0x8			/* UIC vector configuration	*/
+
+#define uic0sr	(UIC0_DCR_BASE+0x0)	/* UIC0 status			*/
+#define uic0er	(UIC0_DCR_BASE+0x2)	/* UIC0 enable			*/
+#define uic0cr	(UIC0_DCR_BASE+0x3)	/* UIC0 critical		*/
+#define uic0pr	(UIC0_DCR_BASE+0x4)	/* UIC0 polarity		*/
+#define uic0tr	(UIC0_DCR_BASE+0x5)	/* UIC0 triggering		*/
+#define uic0msr (UIC0_DCR_BASE+0x6)	/* UIC0 masked status		*/
+#define uic0vr	(UIC0_DCR_BASE+0x7)	/* UIC0 vector			*/
+#define uic0vcr (UIC0_DCR_BASE+0x8)	/* UIC0 vector configuration	*/
+
+/* The following is for compatibility with 405 code */
+#define uicsr	uic0sr
+#define uicer	uic0er
+#define uiccr	uic0cr
+#define uicpr	uic0pr
+#define uictr	uic0tr
+#define uicmsr	uic0msr
+#define uicvr	uic0vr
+#define uicvcr	uic0vcr
+
+/* the interrupt vector definitions */
+#define VECNUM_MAL_SERR		10
+#define VECNUM_MAL_TXEOB	11
+#define VECNUM_MAL_RXEOB	12
+#define VECNUM_MAL_TXDE		13
+#define VECNUM_MAL_RXDE		14
+#define VECNUM_ETH0			15
+#define VECNUM_ETH1_OFFS	2
+#define VECNUM_EIRQ6		29
+
+/*
+ * Mask definitions (used for example in 4xx_enet.c)
+ */
+#define UIC_MASK(vec)		(0x80000000 >> ((vec) & 0x1f))
+/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
+#define UIC_NR(vec)			((vec) >> 5)
+
+#endif /* _PPC4xx_UIC_H_ */

libcpu/ppc/ppc405/include/asm/ppc4xx.h

+/*----------------------------------------------------------------------------+
+|
+|       This source code has been made available to you by IBM on an AS-IS
+|       basis.  Anyone receiving this source is licensed under IBM
+|       copyrights to use it in any way he or she deems fit, including
+|       copying it, modifying it, compiling it, and redistributing it either
+|       with or without modifications.  No license under IBM patents or
+|       patent applications is to be implied by the copyright license.
+|
+|       Any user of this software should understand that IBM cannot provide
+|       technical support for this software and will not be responsible for
+|       any consequences resulting from the use of this software.
+|
+|       Any person who transfers this source code or any derivative work
+|       must include the IBM copyright notice, this paragraph, and the
+|       preceding two paragraphs in the transferred software.
+|
+|       COPYRIGHT   I B M   CORPORATION 1999
+|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef	__PPC4XX_H__
+#define __PPC4XX_H__
+
+/*
+ * Configure which SDRAM/DDR/DDR2 controller is equipped
+ */
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+
+#include <asm/ppc405.h>
+#include <asm/ppc4xx-uic.h>
+
+/*
+ * Macro for generating register field mnemonics
+ */
+#define	PPC_REG_BITS		32
+#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * Elide casts when assembling register mnemonics
+ */
+#ifndef __ASSEMBLY__
+#define	static_cast(type, val)	(type)(val)
+#else
+#define	static_cast(type, val)	(val)
+#endif
+
+/*
+ * Common stuff for 4xx (405 and 440)
+ */
+
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+#define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
+
+#define RESET_VECTOR	0xfffffffc
+#define CACHELINE_MASK	(CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
+						     line aligned data. */
+
+#define CPR0_DCR_BASE	0x0C
+#define cprcfga		(CPR0_DCR_BASE+0x0)
+#define cprcfgd		(CPR0_DCR_BASE+0x1)
+
+#define SDR_DCR_BASE	0x0E
+#define sdrcfga		(SDR_DCR_BASE+0x0)
+#define sdrcfgd		(SDR_DCR_BASE+0x1)
+
+#define SDRAM_DCR_BASE	0x10
+#define memcfga		(SDRAM_DCR_BASE+0x0)
+#define memcfgd		(SDRAM_DCR_BASE+0x1)
+
+#define EBC_DCR_BASE	0x12
+#define ebccfga		(EBC_DCR_BASE+0x0)
+#define ebccfgd		(EBC_DCR_BASE+0x1)
+
+/*
+ * Macros for indirect DCR access
+ */
+#define mtcpr(reg, d)	do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
+#define mfcpr(reg, d)	do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
+
+#define mtebc(reg, d)	do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
+#define mfebc(reg, d)	do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
+
+#define mtsdram(reg, d)	do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
+#define mfsdram(reg, d)	do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
+
+#define mtsdr(reg, d)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
+#define mfsdr(reg, d)	do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+	unsigned long freqDDR;
+	unsigned long freqEBC;
+	unsigned long freqOPB;
+	unsigned long freqPCI;
+	unsigned long freqPLB;
+	unsigned long freqTmrClk;
+	unsigned long freqUART;
+	unsigned long freqProcessor;
+	unsigned long freqVCOHz;
+	unsigned long freqVCOMhz;	/* in MHz                          */
+	unsigned long pciClkSync;	/* PCI clock is synchronous        */
+	unsigned long pciIntArbEn;	/* Internal PCI arbiter is enabled */
+	unsigned long pllExtBusDiv;
+	unsigned long pllFbkDiv;
+	unsigned long pllFwdDiv;
+	unsigned long pllFwdDivA;
+	unsigned long pllFwdDivB;
+	unsigned long pllOpbDiv;
+	unsigned long pllPciDiv;
+	unsigned long pllPlbDiv;
+} PPC4xx_SYS_INFO;
+
+static inline rt_uint32_t get_mcsr(void)
+{
+	rt_uint32_t val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static inline void set_mcsr(rt_uint32_t val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
+#endif	/* __ASSEMBLY__ */
+
+/* for multi-cpu support */
+#define NA_OR_UNKNOWN_CPU	-1
+
+#endif	/* __PPC4XX_H__ */

libcpu/ppc/ppc405/include/asm/ppc_defs.h

+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * WARNING! This file is automatically generated - DO NOT EDIT!
+ */
+#define	STACK_FRAME_OVERHEAD	16
+#define	INT_FRAME_SIZE	192
+#define	GPR0	16
+#define	GPR1	20
+#define	GPR2	24
+#define	GPR3	28
+#define	GPR4	32
+#define	GPR5	36
+#define	GPR6	40
+#define	GPR7	44
+#define	GPR8	48
+#define	GPR9	52
+#define	GPR10	56
+#define	GPR11	60
+#define	GPR12	64
+#define	GPR13	68
+#define	GPR14	72
+#define	GPR15	76
+#define	GPR16	80
+#define	GPR17	84
+#define	GPR18	88
+#define	GPR19	92
+#define	GPR20	96
+#define	GPR21	100
+#define	GPR22	104
+#define	GPR23	108
+#define	GPR24	112
+#define	GPR25	116
+#define	GPR26	120
+#define	GPR27	124
+#define	GPR28	128
+#define	GPR29	132
+#define	GPR30	136
+#define	GPR31	140
+#define	_NIP	144
+#define	_MSR	148
+#define	ORIG_GPR3	152
+#define	_CTR	156
+#define	_LINK	160
+#define	_XER	164
+#define	_CCR	168
+#define	_MQ	    172
+#define	TRAP	176
+#define	_DAR	180
+#define	_DSISR	184
+#define	RESULT	188
+

libcpu/ppc/ppc405/include/asm/ptrace.h

+#ifndef _PPC_PTRACE_H
+#define _PPC_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below.  This simplifies arch/ppc/kernel/ptrace.c.
+ */
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC64BRIDGE
+#define PPC_REG unsigned long /*long*/
+#else
+#define PPC_REG unsigned long
+#endif
+struct pt_regs {
+	PPC_REG gpr[32];
+	PPC_REG nip;
+	PPC_REG msr;
+	PPC_REG orig_gpr3;	/* Used for restarting system calls */
+	PPC_REG ctr;
+	PPC_REG link;
+	PPC_REG xer;
+	PPC_REG ccr;
+	PPC_REG mq;		/* 601 only (not used at present) */
+				    /* Used on APUS to hold IPL value. */
+	PPC_REG trap;		/* Reason for being here */
+	PPC_REG dar;		/* Fault registers */
+	PPC_REG dsisr;
+	PPC_REG result;		/* Result of a system call */
+}__attribute__((packed)) CELL_STACK_FRAME_t;
+#endif
+
+#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE	64
+
+#define instruction_pointer(regs) ((regs)->nip)
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+#define PT_R26	26
+#define PT_R27	27
+#define PT_R28	28
+#define PT_R29	29
+#define PT_R30	30
+#define PT_R31	31
+
+#define PT_NIP	32
+#define PT_MSR	33
+#ifdef __KERNEL__
+#define PT_ORIG_R3 34
+#endif
+#define PT_CTR	35
+#define PT_LNK	36
+#define PT_XER	37
+#define PT_CCR	38
+#define PT_MQ	39
+
+#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#endif

libcpu/ppc/ppc405/include/asm/types.h

+#ifndef _PPC_TYPES_H
+#define _PPC_TYPES_H
+
+
+#ifndef __ASSEMBLY__
+
+typedef enum bool
+    {
+    FALSE = 0,
+    TRUE = 1
+    }BOOL;
+
+typedef unsigned short umode_t;
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef struct {
+	__u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
+#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+typedef char INT8;
+typedef short INT16;
+typedef int INT32;
+typedef long long INT64;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned long long UINT64;
+
+#define BITS_PER_LONG 32
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif

libcpu/ppc/ppc405/include/config.h

+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+
+#define CONFIG_SYS_DCACHE_SIZE	(16 << 10)/* For AMCC 405 CPUs	*/
+#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* _must_ be 0		*/
+
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_CLK_RECFG	0	/* Config the sys clks */
+#define CONFIG_SYS_CLK_FREQ     33333333 /*3300000*//* external frequency to pll   */
+#define CONFIG_SYS_HZ           100
+#define CONFIG_SYS_PIT_RELOAD   (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)  
+
+/*
+ * UART
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_SYS_BASE_BAUD		691200
+#define CONFIG_UART1_CONSOLE		1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short
+
+#endif	/* __CONFIG_H */

libcpu/ppc/ppc405/interrupt.c

+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ */
+
+#include <rtthread.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/* interrupt nest */
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+#define MAX_HANDLERS 32
+rt_isr_handler_t isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrput_flag;
+
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
+{
+	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+	return RT_NULL;
+}
+
+void uic_irq_ack(unsigned int vec)
+{
+	mtdcr(uic0sr, UIC_MASK(vec));
+}
+
+void  uic_int_handler (unsigned int vec)
+{
+	rt_interrupt_enter();
+
+    /* Allow external interrupts to the CPU. */
+    if (isr_table [vec] != 0)
+    {
+       (*isr_table[vec])(vec);
+    }
+    uic_irq_ack(vec);
+	
+    rt_interrupt_leave();
+}
+
+/* handler for UIC interrupt */
+void uic_interrupt(rt_uint32_t uic_base, int vec_base)
+{
+	int vec;
+	rt_uint32_t uic_msr;
+	rt_uint32_t msr_shift;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic_msr = get_dcr(uic_base + UIC_MSR);
+	msr_shift = uic_msr;
+	vec = vec_base;
+
+	while (msr_shift != 0)
+	{
+		if (msr_shift & 0x80000000)
+			uic_int_handler(vec);
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+
+void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
+{
+    int	intVal;
+
+    if (((int)vector < 0)  || ((int) vector >= MAX_HANDLERS)) 
+	{
+        return;   /*  out of range  */
+	}
+   
+    /* install the handler in the system interrupt table  */
+    intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */
+
+	if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
+	if (new_handler != RT_NULL) isr_table[vector] = new_handler;
+
+    rt_hw_interrupt_enable (intVal);
+}
+
+void rt_hw_interrupt_mask(int vector)
+{
+	mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
+}
+
+void rt_hw_interrupt_unmask(int vector)
+{
+	mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
+}
+
+void rt_hw_interrupt_init()
+{
+	int vector;
+    rt_uint32_t pit_value;
+
+    pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ);
+
+    /* enable pit */
+	mtspr(SPRN_PIT, pit_value);
+	mtspr(SPRN_TCR, 0x4400000);
+
+	/* set default interrupt handler */
+    for (vector = 0; vector < MAX_HANDLERS; vector++)
+    {
+	    isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle;
+    }
+
+	/* initialize interrupt nest, and context in thread sp */
+	rt_interrupt_nest = 0;
+	rt_interrupt_from_thread = 0;
+	rt_interrupt_to_thread = 0;
+	rt_thread_switch_interrput_flag = 0;
+}
+
+/*@}*/

libcpu/ppc/ppc405/io.h

+#ifndef __IO_H__
+#define __IO_H__
+
+#define __iomem
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ *
+ * Read operations have additional twi & isync to make sure the read
+ * is actually performed (i.e. the data has come back) before we start
+ * executing any following instructions.
+ */
+static inline int in_8(const volatile unsigned char __iomem *addr)
+{
+	int ret;
+
+	__asm__ __volatile__(
+		"sync; lbz%U1%X1 %0,%1;\n"
+		"twi 0,%0,0;\n"
+		"isync" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_8(volatile unsigned char __iomem *addr, int val)
+{
+	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline int in_le16(const volatile unsigned short __iomem *addr)
+{
+	int ret;
+
+	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) :
+			      "r" (addr), "m" (*addr));
+	return ret;
+}
+
+extern inline int in_be16(const volatile unsigned short __iomem *addr)
+{
+	int ret;
+
+	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
+{
+	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
+			      "r" (val), "r" (addr));
+}
+
+extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
+{
+	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+}
+
+extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
+{
+	unsigned ret;
+
+	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) :
+			     "r" (addr), "m" (*addr));
+	return ret;
+}
+
+extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
+{
+	unsigned ret;
+
+	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+extern inline void out_le32(volatile unsigned __iomem *addr, int val)
+{
+	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
+			     "r" (val), "r" (addr));
+}
+
+extern inline void out_be32(volatile unsigned __iomem *addr, int val)
+{
+	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+}
+
+#endif

libcpu/ppc/ppc405/serial.c

+#include <rthw.h>
+#include <rtthread.h>
+
+#include "io.h"
+#include <asm/ppc4xx-intvec.h>
+
+#define UART0_BASE      0xef600300
+#define UART1_BASE      0xef600400
+#define UCR0_MASK       0x0000007f
+#define UCR1_MASK       0x00007f00
+#define UCR0_UDIV_POS   0
+#define UCR1_UDIV_POS   8
+#define UDIV_MAX        127
+
+#define UART_RBR		0x00
+#define UART_THR		0x00
+#define UART_IER		0x01
+#define UART_IIR		0x02
+#define UART_FCR		0x02
+#define UART_LCR		0x03
+#define UART_MCR		0x04
+#define UART_LSR		0x05
+#define UART_MSR		0x06
+#define UART_SCR		0x07
+#define UART_DLL		0x00
+#define UART_DLM		0x01
+
+/*-----------------------------------------------------------------------------+
+  | Line Status Register.
+  +-----------------------------------------------------------------------------*/
+#define asyncLSRDataReady1            0x01
+#define asyncLSROverrunError1         0x02
+#define asyncLSRParityError1          0x04
+#define asyncLSRFramingError1         0x08
+#define asyncLSRBreakInterrupt1       0x10
+#define asyncLSRTxHoldEmpty1          0x20
+#define asyncLSRTxShiftEmpty1         0x40
+#define asyncLSRRxFifoError1          0x80
+
+/* PPC405 serial device */
+struct rt_ppc405_serial
+{
+	/* inherit from device */
+	struct rt_device parent;
+
+	rt_uint32_t hw_base;
+	rt_uint32_t irqno;
+	rt_uint32_t baudrate;
+
+	/* reception field */
+	rt_uint16_t save_index, read_index;
+	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+};
+struct rt_ppc405_serial ppc405_serial;
+
+/* serial character device */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	struct rt_ppc405_serial* device;
+	device = (struct rt_ppc405_serial*) dev;
+	
+	RT_ASSERT(device != RT_NULL);
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* Enable "RX Data Available" Interrupt on UART */
+		out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
+		/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
+		out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
+
+	    /* init UART rx interrupt */
+	    rt_hw_interrupt_unmask(device->irqno);
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+	struct rt_ppc405_serial* device;
+	device = (struct rt_ppc405_serial*) dev;
+	
+	RT_ASSERT(device != RT_NULL);
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* mask UART rx interrupt */
+	    rt_hw_interrupt_mask(device->irqno);
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	struct rt_ppc405_serial* device;
+
+	device = (struct rt_ppc405_serial*) dev;
+	RT_ASSERT(device != RT_NULL);
+
+	/* point to buffer */
+	ptr = (rt_uint8_t*) buffer;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		while (size)
+		{
+			/* interrupt receive */
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+			if (device->read_index != device->save_index)
+			{
+				*ptr = device->rx_buffer[device->read_index];
+
+				device->read_index ++;
+				if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
+					device->read_index = 0;
+			}
+			else
+			{
+				/* no data in rx buffer */
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+
+			ptr ++; size --;
+		}
+
+		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+	{
+		/* not support right now */
+		RT_ASSERT(0);
+	}
+
+	/* polling mode */
+	RT_ASSERT(0);
+
+	return (rt_size_t)ptr - (rt_size_t)buffer;
+}
+
+static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	char *ptr;
+	struct rt_ppc405_serial* device;
+
+	device = (struct rt_ppc405_serial*) dev;
+	RT_ASSERT(device != RT_NULL);
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		/* not support */
+		RT_ASSERT(0);
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		/* not support */
+		RT_ASSERT(0);
+	}
+
+	/* polling write */
+	ptr = (char *)buffer;
+	
+	if (dev->flag & RT_DEVICE_FLAG_STREAM)
+	{
+		/* stream mode */
+		while (size)
+		{
+			if (*ptr == '\n')
+			{
+				while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
+				out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
+			}
+
+			while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
+			out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
+
+			ptr ++;
+			size --;
+		}
+	}
+	else
+	{
+		while (size)
+		{
+			while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
+			out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
+			
+			ptr ++;
+			size --;
+		}
+	}
+	
+	return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+void rt_serial_set_baudrate(struct rt_ppc405_serial* device)
+{
+	rt_uint32_t bdiv;
+
+	bdiv = 115200;
+	out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv);		/* set baudrate divisor */
+	out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+}
+
+void rt_serial_isr(int irqno)
+{
+	unsigned char status;
+	struct rt_ppc405_serial *device;
+
+	device = (struct rt_ppc405_serial*) &ppc405_serial;
+	status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
+
+	if (status & 0x01)
+	{
+		rt_base_t level;
+
+		while (status & 0x01)
+		{
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			/* read character */
+			device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
+			device->save_index ++;
+			if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
+				device->save_index = 0;
+			
+			/* if the next position is read index, discard this 'read char' */
+			if (device->save_index == device->read_index)
+			{
+				device->read_index ++;
+				if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
+					device->read_index = 0;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+
+			/* check error */
+			if ((status & ( asyncLSRFramingError1 |
+					asyncLSROverrunError1 |
+					asyncLSRParityError1  |
+					asyncLSRBreakInterrupt1 )) != 0)
+			{
+				out_8((rt_uint8_t *)device->hw_base + UART_LSR,
+					  asyncLSRFramingError1 |
+					  asyncLSROverrunError1 |
+					  asyncLSRParityError1  |
+					  asyncLSRBreakInterrupt1);
+			}
+
+			status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
+		}
+
+		/* invoke callback */
+		if(device->parent.rx_indicate != RT_NULL)
+		{
+		  device->parent.rx_indicate(&device->parent, 1);
+		}
+	}
+}
+
+void rt_hw_serial_init(void)
+{
+	volatile rt_uint8_t val;
+	struct rt_ppc405_serial* device;
+
+	device = (struct rt_ppc405_serial*) &ppc405_serial;
+	device->parent.type = RT_Device_Class_Char;
+	
+	device->hw_base = UART0_BASE;
+	device->baudrate = 115200;
+	device->irqno = VECNUM_U0;
+	rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */
+
+	rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
+	device->read_index = device->save_index = 0;
+
+	out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80);	/* set DLAB bit */
+	/* setup baudrate */
+	rt_serial_set_baudrate(device);
+	out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00);	/* disable FIFO */
+	out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in_8((rt_uint8_t *)device->hw_base + UART_LSR);	/* clear line status */
+	val = in_8((rt_uint8_t *)device->hw_base + UART_RBR);	/* read receive buffer */
+	out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00);	/* set scratchpad */
+	out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00);	/* set interrupt enable reg */
+
+	device->parent.type     = RT_Device_Class_Char;
+	device->parent.init 	= rt_serial_init;
+	device->parent.open 	= rt_serial_open;
+	device->parent.close    = rt_serial_close;
+	device->parent.read 	= rt_serial_read;
+	device->parent.write    = rt_serial_write;
+	device->parent.control  = rt_serial_control;
+	device->parent.user_data  = RT_NULL;
+
+	rt_device_register(&device->parent, 
+		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
+}

libcpu/ppc/ppc405/traps.c

+#include <rtthread.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-uic.h>
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+/* THIS NEEDS CHANGING to use the board info structure.
+ */
+#define END_OF_MEM	0x800000
+#define UICB0_ALL	0
+
+#define ESR_MCI 0x80000000
+#define ESR_PIL 0x08000000
+#define ESR_PPR 0x04000000
+#define ESR_PTR 0x02000000
+#define ESR_DST 0x00800000
+#define ESR_DIZ 0x00400000
+#define ESR_U0F 0x00008000
+
+rt_inline void set_tsr(unsigned long val)
+{
+    mtspr(SPRN_TSR, val);
+}
+
+rt_inline rt_uint32_t get_esr(void)
+{
+    rt_uint32_t val;
+
+    val = mfspr(SPRN_ESR);
+    return val;
+}
+
+/*
+ * Trap & Exception support
+ */
+
+void print_backtrace(unsigned long *sp)
+{
+    int cnt = 0;
+    unsigned long i;
+
+    rt_kprintf("Call backtrace: ");
+    while (sp) {
+        if ((rt_uint32_t)sp > END_OF_MEM)
+            break;
+
+        i = sp[1];
+        if (cnt++ % 7 == 0)
+            rt_kprintf("\n");
+        rt_kprintf("%08lX ", i);
+        if (cnt > 32) break;
+        sp = (unsigned long *)*sp;
+    }
+    rt_kprintf("\n");
+}
+
+void show_regs(struct pt_regs * regs)
+{
+    int i;
+
+    rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
+           regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+    rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+           regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+           regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+           regs->msr&MSR_IR ? 1 : 0,
+           regs->msr&MSR_DR ? 1 : 0);
+
+    rt_kprintf("\n");
+    for (i = 0;  i < 32;  i++) {
+        if ((i % 8) == 0) {
+            rt_kprintf("GPR%02d: ", i);
+        }
+
+        rt_kprintf("%08lX ", regs->gpr[i]);
+        if ((i % 8) == 7) {
+            rt_kprintf("\n");
+        }
+    }
+}
+
+void panic(const char *fmt, ...)
+{
+    while(1);
+}
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+    show_regs(regs);
+    print_backtrace((unsigned long *)regs->gpr[1]);
+    panic("Exception");
+}
+
+unsigned long
+search_exception_table(unsigned long addr)
+{
+        unsigned long ret = 0;
+
+        /* There is only the kernel to search.  */
+        // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr);
+        /* if the serial port does not hang in exception, rt_kprintf can be used */
+        if (ret) return ret;
+
+        return 0;
+}
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
+{
+    u32 uic_msr;
+
+    /*
+     * Read masked interrupt status register to determine interrupt source
+     */
+    uic_msr = mfdcr(uic0msr);
+
+    mtdcr(uic0sr, (uic_msr & UICB0_ALL));
+
+    if (uic_msr & ~(UICB0_ALL))
+    {
+        uic_interrupt(UIC0_DCR_BASE, 0);
+    }
+
+    return;
+}
+
+void MachineCheckException(struct pt_regs *regs)
+{
+    unsigned long fixup, val;
+
+    if ((fixup = search_exception_table(regs->nip)) != 0) {
+        regs->nip = fixup;
+        val = mfspr(MCSR);
+        /* Clear MCSR */
+        mtspr(SPRN_MCSR, val);
+        return;
+    }
+
+    rt_kprintf("Machine Check Exception.\n");
+    rt_kprintf("Caused by (from msr): ");
+    rt_kprintf("regs %p ", regs);
+
+    val = get_esr();
+
+    if (val& ESR_IMCP) {
+        rt_kprintf("Instruction");
+        mtspr(ESR, val & ~ESR_IMCP);
+    } else {
+        rt_kprintf("Data");
+    }
+    rt_kprintf(" machine check.\n");
+
+    show_regs(regs);
+    print_backtrace((unsigned long *)regs->gpr[1]);
+    panic("machine check");
+}
+
+void AlignmentException(struct pt_regs *regs)
+{
+    show_regs(regs);
+    print_backtrace((unsigned long *)regs->gpr[1]);
+    panic("Alignment Exception");
+}
+
+void ProgramCheckException(struct pt_regs *regs)
+{
+    long esr_val;
+
+    show_regs(regs);
+
+    esr_val = get_esr();
+    if( esr_val & ESR_PIL )
+        rt_kprintf( "** Illegal Instruction **\n" );
+    else if( esr_val & ESR_PPR )
+        rt_kprintf( "** Privileged Instruction **\n" );
+    else if( esr_val & ESR_PTR )
+        rt_kprintf( "** Trap Instruction **\n" );
+
+    print_backtrace((unsigned long *)regs->gpr[1]);
+    panic("Program Check Exception");
+}
+
+void DecrementerPITException(struct pt_regs *regs)
+{
+    /* reset PIT interrupt */
+    set_tsr(0x08000000);
+
+    /* increase a OS Tick */
+    rt_tick_increase();
+}
+
+void UnknownException(struct pt_regs *regs)
+{
+
+    rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+           regs->nip, regs->msr, regs->trap);
+    _exception(0, regs);
+}
+
+void DebugException(struct pt_regs *regs)
+{
+    rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs );
+    show_regs(regs);
+}