Skip to content

A
A-Tune

openeuler / A-Tune

通知 5
Star 0
Fork 0
A
A-Tune

前往新版Gitcode，体验更适合开发者的 AI 搜索 >>

提交 ff57a47f 编写于 作者: O openeuler-ci-bot 提交者： Gitee
浏览文件
操作

!62 atune: fix the error that is failed to get bandwidth in perf-memBW.sh 

Merge pull request !62 from hanxinke/test_hxk
上级 1007ebb6 b3bd0ae5
隐藏空白更改
内联 并排
Showing with 102 addition and 96 deletion
collection/collect/perf-memBW.sh
浏览文件 @ ff57a47f
...@@ -10,125 +10,131 @@ ...@@ -10,125 +10,131 @@
# See the Mulan PSL v1 for more details. # See the Mulan PSL v1 for more details.
# Create: 2019-10-29 # Create: 2019-10-29
function perf_Mem_bw () { function perf_Mem_bw() {
if dmidecode -t processor | grep -q -E 'Kunpeng|Hisilicon' ; then if dmidecode -t processor | grep -q -E 'Kunpeng|Hisilicon' ; then
CPU0_Die0_BW_R="hisi_sccl1_ddrc0/flux_rd/,hisi_sccl1_ddrc1/flux_rd/,hisi_sccl1_ddrc2/flux_rd/,hisi_sccl1_ddrc3/flux_rd/" CPU0_Die0_BW_R="hisi_sccl1_ddrc0/flux_rd/,hisi_sccl1_ddrc1/flux_rd/,hisi_sccl1_ddrc2/flux_rd/,hisi_sccl1_ddrc3/flux_rd/"
CPU0_Die0_BW_W="hisi_sccl1_ddrc0/flux_wr/,hisi_sccl1_ddrc1/flux_wr/,hisi_sccl1_ddrc2/flux_wr/,hisi_sccl1_ddrc3/flux_wr/" CPU0_Die0_BW_W="hisi_sccl1_ddrc0/flux_wr/,hisi_sccl1_ddrc1/flux_wr/,hisi_sccl1_ddrc2/flux_wr/,hisi_sccl1_ddrc3/flux_wr/"
CPU0_Die1_BW_R="hisi_sccl3_ddrc0/flux_rd/,hisi_sccl3_ddrc1/flux_rd/,hisi_sccl3_ddrc2/flux_rd/,hisi_sccl3_ddrc3/flux_rd/" CPU0_Die1_BW_R="hisi_sccl3_ddrc0/flux_rd/,hisi_sccl3_ddrc1/flux_rd/,hisi_sccl3_ddrc2/flux_rd/,hisi_sccl3_ddrc3/flux_rd/"
CPU0_Die1_BW_W="hisi_sccl3_ddrc0/flux_wr/,hisi_sccl3_ddrc1/flux_wr/,hisi_sccl3_ddrc2/flux_wr/,hisi_sccl3_ddrc3/flux_wr/" CPU0_Die1_BW_W="hisi_sccl3_ddrc0/flux_wr/,hisi_sccl3_ddrc1/flux_wr/,hisi_sccl3_ddrc2/flux_wr/,hisi_sccl3_ddrc3/flux_wr/"
CPU1_Die0_BW_R="hisi_sccl5_ddrc0/flux_rd/,hisi_sccl5_ddrc1/flux_rd/,hisi_sccl5_ddrc2/flux_rd/,hisi_sccl5_ddrc3/flux_rd/" CPU1_Die0_BW_R="hisi_sccl5_ddrc0/flux_rd/,hisi_sccl5_ddrc1/flux_rd/,hisi_sccl5_ddrc2/flux_rd/,hisi_sccl5_ddrc3/flux_rd/"
CPU1_Die0_BW_W="hisi_sccl5_ddrc0/flux_wr/,hisi_sccl5_ddrc1/flux_wr/,hisi_sccl5_ddrc2/flux_wr/,hisi_sccl5_ddrc3/flux_wr/" CPU1_Die0_BW_W="hisi_sccl5_ddrc0/flux_wr/,hisi_sccl5_ddrc1/flux_wr/,hisi_sccl5_ddrc2/flux_wr/,hisi_sccl5_ddrc3/flux_wr/"
CPU1_Die1_BW_R="hisi_sccl7_ddrc0/flux_rd/,hisi_sccl7_ddrc1/flux_rd/,hisi_sccl7_ddrc2/flux_rd/,hisi_sccl7_ddrc3/flux_rd/" CPU1_Die1_BW_R="hisi_sccl7_ddrc0/flux_rd/,hisi_sccl7_ddrc1/flux_rd/,hisi_sccl7_ddrc2/flux_rd/,hisi_sccl7_ddrc3/flux_rd/"
CPU1_Die1_BW_W="hisi_sccl7_ddrc0/flux_wr/,hisi_sccl7_ddrc1/flux_wr/,hisi_sccl7_ddrc2/flux_wr/,hisi_sccl7_ddrc3/flux_wr/" CPU1_Die1_BW_W="hisi_sccl7_ddrc0/flux_wr/,hisi_sccl7_ddrc1/flux_wr/,hisi_sccl7_ddrc2/flux_wr/,hisi_sccl7_ddrc3/flux_wr/"
BW_Events=" $CPU0_Die0_BW_R,$CPU0_Die0_BW_W,$CPU0_Die1_BW_R,$CPU0_Die1_BW_W,$CPU1_Die0_BW_R,$CPU1_Die0_BW_W,$CPU1_Die1_BW_R,$CPU1_Die1_BW_W" BW_Events=" $CPU0_Die0_BW_R,$CPU0_Die0_BW_W,$CPU0_Die1_BW_R,$CPU0_Die1_BW_W,$CPU1_Die0_BW_R,$CPU1_Die0_BW_W,$CPU1_Die1_BW_R,$CPU1_Die1_BW_W"
else
echo "not Support This CPU Architecture..." all_events=$(perf list | awk '{print $1}')
exit for event in $all_events; do
if [[ $BW_Events =~ $event ]]; then
aim_events=$aim_events,$event
fi
done
else
fi echo "not Support This CPU Architecture..."
exit
let interval=$interval*1000 fi
interval=$((interval * 1000))
timeout $ts perf stat -x ',' -a -I $interval -e $BW_Events 2>&1 | \ timeout "$ts" perf stat -x ',' -a -I $interval -e "$aim_events" 2>&1 | \
awk -F, ' awk -F, '
BEGIN { BEGIN {
tpre=-1; tpre=-1;
first=1; first=1;
} }
{ {
tcurr=$1; tcurr=$1;
if(first==1) if(first==1)
{ {
tpre=tcurr; tpre=tcurr;
first=0; first=0;
printf("#################################Start to monitor The System DDR Bandwidth##################################################\n"); printf("#################################Start to monitor The System DDR Bandwidth##################################################\n");
printf(" MEM_Total CPU0 CPU1 CPU0_Die0 CPU0_Die1 CPU1_Die0 CPU1_Die1 MEM_CPU0_Die0_R MEM_CPU0_Die1_R MEM_CPU1_Die0_R MEM_CPU1_Die1_R MEM_CPU0_Die0_W MEM_CPU0_Die1_W MEM_CPU1_Die0_W MEM_CPU1_Die1_W\n"); printf(" MEM_Total CPU0 CPU1 CPU0_Die0 CPU0_Die1 CPU1_Die0 CPU1_Die1 MEM_CPU0_Die0_R MEM_CPU0_Die1_R MEM_CPU1_Die0_R MEM_CPU1_Die1_R MEM_CPU0_Die0_W MEM_CPU0_Die1_W MEM_CPU1_Die0_W MEM_CPU1_Die1_W\n");
} }
if(tcurr != tpre) if(tcurr != tpre)
{ {
MEM_CPU0_Die0_R = CPU0_Die0_R*32/1024/1024; MEM_CPU0_Die0_R = CPU0_Die0_R*32/1024/1024;
MEM_CPU0_Die1_R = CPU0_Die1_R*32/1024/1024; MEM_CPU0_Die1_R = CPU0_Die1_R*32/1024/1024;
MEM_CPU1_Die0_R = CPU1_Die0_R*32/1024/1024; MEM_CPU1_Die0_R = CPU1_Die0_R*32/1024/1024;
MEM_CPU1_Die1_R = CPU1_Die1_R*32/1024/1024; MEM_CPU1_Die1_R = CPU1_Die1_R*32/1024/1024;
MEM_CPU0_Die0_W = CPU0_Die0_W*32/1024/1024;
MEM_CPU0_Die1_W = CPU0_Die1_W*32/1024/1024;
MEM_CPU1_Die0_W = CPU1_Die0_W*32/1024/1024;
MEM_CPU1_Die1_W = CPU1_Die1_W*32/1024/1024;
MEM_CPU0_Die0 = MEM_CPU0_Die0_R + MEM_CPU0_Die0_W; MEM_CPU0_Die0_W = CPU0_Die0_W*32/1024/1024;
MEM_CPU0_Die1 = MEM_CPU0_Die1_R + MEM_CPU0_Die1_W; MEM_CPU0_Die1_W = CPU0_Die1_W*32/1024/1024;
MEM_CPU1_Die0_W = CPU1_Die0_W*32/1024/1024;
MEM_CPU1_Die1_W = CPU1_Die1_W*32/1024/1024;
MEM_CPU0_Die0 = MEM_CPU0_Die0_R + MEM_CPU0_Die0_W;
MEM_CPU0_Die1 = MEM_CPU0_Die1_R + MEM_CPU0_Die1_W;
MEM_CPU1_Die0 = MEM_CPU1_Die0_R + MEM_CPU1_Die0_W; MEM_CPU1_Die0 = MEM_CPU1_Die0_R + MEM_CPU1_Die0_W;
MEM_CPU1_Die1 = MEM_CPU1_Die1_R + MEM_CPU1_Die1_W; MEM_CPU1_Die1 = MEM_CPU1_Die1_R + MEM_CPU1_Die1_W;
MEM_CPU0 = MEM_CPU0_Die0_R + MEM_CPU0_Die0_W + MEM_CPU0_Die1_R + MEM_CPU0_Die1_W; MEM_CPU0 = MEM_CPU0_Die0_R + MEM_CPU0_Die0_W + MEM_CPU0_Die1_R + MEM_CPU0_Die1_W;
MEM_CPU1 = MEM_CPU1_Die0_R + MEM_CPU1_Die0_W + MEM_CPU1_Die1_R + MEM_CPU1_Die1_W; MEM_CPU1 = MEM_CPU1_Die0_R + MEM_CPU1_Die0_W + MEM_CPU1_Die1_R + MEM_CPU1_Die1_W;
MEM_Total = MEM_CPU0 + MEM_CPU1; MEM_Total = MEM_CPU0 + MEM_CPU1;
printf("%10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f\n",MEM_Total,MEM_CPU0,MEM_CPU1,MEM_CPU0_Die0,MEM_CPU0_Die1,MEM_CPU1_Die0,MEM_CPU1_Die1,MEM_CPU0_Die0_R,MEM_CPU0_Die1_R,MEM_CPU1_Die0_R,MEM_CPU1_Die1_R,MEM_CPU0_Die0_W,MEM_CPU0_Die1_W,MEM_CPU1_Die0_W,MEM_CPU1_Die1_W); printf("%10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f %10.2f\n",MEM_Total,MEM_CPU0,MEM_CPU1,MEM_CPU0_Die0,MEM_CPU0_Die1,MEM_CPU1_Die0,MEM_CPU1_Die1,MEM_CPU0_Die0_R,MEM_CPU0_Die1_R,MEM_CPU1_Die0_R,MEM_CPU1_Die1_R,MEM_CPU0_Die0_W,MEM_CPU0_Die1_W,MEM_CPU1_Die0_W,MEM_CPU1_Die1_W);
CPU0_Die0_R=0; CPU0_Die0_R=0;
CPU0_Die0_W=0; CPU0_Die0_W=0;
CPU0_Die1_R=0; CPU0_Die1_R=0;
CPU0_Die1_W=0; CPU0_Die1_W=0;
CPU1_Die0_R=0; CPU1_Die0_R=0;
CPU1_Die0_W=0; CPU1_Die0_W=0;
CPU1_Die1_R=0; CPU1_Die1_R=0;
CPU1_Die1_W=0; CPU1_Die1_W=0;
tpre=tcurr; tpre=tcurr;
} }
switch ($4) switch ($4)
{ {
case /sccl1.*rd/: case /sccl1.*rd/:
CPU0_Die0_R += $2; CPU0_Die0_R += $2;
break; break;
case /sccl1.*wr/: case /sccl1.*wr/:
CPU0_Die0_W += $2; CPU0_Die0_W += $2;
break; break;
case /sccl3.*rd/: case /sccl3.*rd/:
CPU0_Die1_R += $2; CPU0_Die1_R += $2;
break; break;
case /sccl3.*wr/: case /sccl3.*wr/:
CPU0_Die1_W += $2; CPU0_Die1_W += $2;
break; break;
case /sccl5.*rd/: case /sccl5.*rd/:
CPU1_Die0_R += $2; CPU1_Die0_R += $2;
break; break;
case /sccl5.*wr/: case /sccl5.*wr/:
CPU1_Die0_W += $2; CPU1_Die0_W += $2;
break; break;
case /sccl7.*rd/: case /sccl7.*rd/:
CPU1_Die1_R += $2; CPU1_Die1_R += $2;
break; break;
case /sccl7.*wr/: case /sccl7.*wr/:
CPU1_Die1_W += $2; CPU1_Die1_W += $2;
break; break;
} }
} }
' '
} }
if [ ! $# == 1 ]; then if [ ! $# == 1 ]; then
echo "Usage: perf_mem.sh sample_interval" echo "Usage: perf_mem.sh sample_interval"
exit exit
fi fi
ts=0 ts=0
interval=$1 interval=$1
perf_Mem_bw perf_Mem_bw
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或