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    [libcpu] Refine MIPS common code · 7c665018
    Jiaxun Yang 提交于
    MIPS common code was highly duplicated, This commit
    is a attempt to clean-up and refine these code.
    
    The context and exception handle flow is mostly identical
    with Linux, but a notable difference is that when FPU enabled,
    we save FP registers in stackframe unconditionally.
    Signed-off-by: NJiaxun Yang <jiaxun.yang@flygoat.com>
    7c665018
mips_cache.c 3.6 KB