kernel: bump 5.4 to 5.4.86

include/kernel-version.mk

@@ -8,11 +8,11 @@ endif
 
 LINUX_VERSION-4.14 = .195
 LINUX_VERSION-4.19 = .138
-LINUX_VERSION-5.4 = .85
+LINUX_VERSION-5.4 = .86
 
 LINUX_KERNEL_HASH-4.14.195 = 394f28798670240baacd9e2cce521fbd79f8da5e1fc191695b0e11381445a021
 LINUX_KERNEL_HASH-4.19.138 = d15c27d05f6c527269b75b30cc72972748e55720e7e00ad8abbaa4fe3b1d5e02
-LINUX_KERNEL_HASH-5.4.85 = 1de3586d8e7a9a814726610745d80907a267590d2770ec1079ef2875c4984008
+LINUX_KERNEL_HASH-5.4.86 = eb36b5fc6ef7b953acba0a3e62d872e0330c4d34b38d58f5714493a4fe3b0e8b
 
 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
 sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

target/linux/ath25/patches-5.4/130-watchdog.patch

@@ -212,7 +212,7 @@
 +MODULE_ALIAS("platform:" DRIVER_NAME);
 --- a/drivers/watchdog/Kconfig
 +++ b/drivers/watchdog/Kconfig
-@@ -1830,6 +1830,13 @@ config PIC32_DMT
+@@ -1832,6 +1832,13 @@ config PIC32_DMT
  	  To compile this driver as a loadable module, choose M here.
  	  The module will be called pic32-dmt.
  

target/linux/ath79/patches-5.4/0001-MIPS-cmdline-Clean-up-boot_command_line-initializati.patch

@@ -44,11 +44,9 @@ Origin: upstream, https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
 Signed-off-by: Paul Burton <paul.burton@mips.com>
 Cc: linux-mips@vger.kernel.org
 
-diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
-index b8884de89c81e1b444b218a15519556b4a374089..e56dd6c25d46336fcb9af21326f697d0c37aac1c 100644
 --- a/arch/mips/kernel/setup.c
 +++ b/arch/mips/kernel/setup.c
-@@ -538,11 +538,88 @@ static void __init check_kernel_sections_mem(void)
+@@ -538,11 +538,88 @@ static void __init check_kernel_sections
  	}
  }
  
@@ -142,7 +140,7 @@ index b8884de89c81e1b444b218a15519556b4a374089..e56dd6c25d46336fcb9af21326f697d0
  
  /*
   * arch_mem_init - initialize memory management subsystem
-@@ -570,48 +647,12 @@ static void __init arch_mem_init(char **cmdline_p)
+@@ -570,48 +647,12 @@ static void __init arch_mem_init(char **
  {
  	extern void plat_mem_setup(void);
  

target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch

@@ -30,7 +30,7 @@ Signed-off-by: Sungbo Eo <mans0n@gorani.run>
  			uport->cons->cflag = 0;
  		}
  		/*
-@@ -2104,8 +2106,10 @@ uart_set_options(struct uart_port *port,
+@@ -2108,8 +2110,10 @@ uart_set_options(struct uart_port *port,
  	 * Allow the setting of the UART parameters with a NULL console
  	 * too:
  	 */

target/linux/bcm27xx/patches-5.4/950-0027-mm-Remove-the-PFN-busy-warning.patch

@@ -14,7 +14,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -8489,8 +8489,6 @@ int alloc_contig_range(unsigned long sta
+@@ -8512,8 +8512,6 @@ int alloc_contig_range(unsigned long sta
  
  	/* Make sure the range is really isolated. */
  	if (test_pages_isolated(outer_start, end, false)) {

target/linux/bcm27xx/patches-5.4/950-0084-hci_h5-Don-t-send-conf_req-when-ACTIVE.patch

@@ -11,7 +11,7 @@ other with conf_req and conf_rsp messages, in a demented game of tag.
 
 --- a/drivers/bluetooth/hci_h5.c
 +++ b/drivers/bluetooth/hci_h5.c
-@@ -339,7 +339,8 @@ static void h5_handle_internal_rx(struct
+@@ -342,7 +342,8 @@ static void h5_handle_internal_rx(struct
  		h5_link_control(hu, conf_req, 3);
  	} else if (memcmp(data, conf_req, 2) == 0) {
  		h5_link_control(hu, conf_rsp, 2);

target/linux/bcm27xx/patches-5.4/950-0653-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch

@@ -23,7 +23,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -3058,6 +3058,7 @@ static int __spi_validate_bits_per_word(
+@@ -3115,6 +3115,7 @@ static int __spi_validate_bits_per_word(
   */
  int spi_setup(struct spi_device *spi)
  {
@@ -31,7 +31,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	unsigned	bad_bits, ugly_bits;
  	int		status;
  
-@@ -3075,6 +3076,14 @@ int spi_setup(struct spi_device *spi)
+@@ -3132,6 +3133,14 @@ int spi_setup(struct spi_device *spi)
  		(SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
  		 SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
  		return -EINVAL;

target/linux/bcm27xx/patches-5.4/950-0672-spi-use_gpio_descriptor-fixup-moved-to-spi_setup.patch

@@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -1792,15 +1792,6 @@ static int of_spi_parse_dt(struct spi_co
+@@ -1793,15 +1793,6 @@ static int of_spi_parse_dt(struct spi_co
  	}
  	spi->chip_select = value;
  

target/linux/bcm27xx/patches-5.4/950-0697-SQUASH-spi-Demote-SPI_CS_HIGH-warning-to-KERN_DEBUG.patch

@@ -15,7 +15,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -3070,8 +3070,8 @@ int spi_setup(struct spi_device *spi)
+@@ -3127,8 +3127,8 @@ int spi_setup(struct spi_device *spi)
  
  	if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
  	    ctlr->cs_gpiods[spi->chip_select] && !(spi->mode & SPI_CS_HIGH)) {

target/linux/bcm47xx/patches-5.4/831-old_gpio_wdt.patch

@@ -4,7 +4,7 @@ Signed-off-by: Mathias Adam <m.adam--openwrt@adamis.de>
 
 --- a/drivers/watchdog/Kconfig
 +++ b/drivers/watchdog/Kconfig
-@@ -1655,6 +1655,15 @@ config WDT_MTX1
+@@ -1657,6 +1657,15 @@ config WDT_MTX1
  	  Hardware driver for the MTX-1 boards. This is a watchdog timer that
  	  will reboot the machine after a 100 seconds timer expired.
  

target/linux/bcm53xx/patches-5.4/905-BCM53573-minor-hacks.patch

@@ -61,7 +61,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  #include <linux/clockchips.h>
  #include <linux/clocksource.h>
  #include <linux/interrupt.h>
-@@ -910,6 +911,16 @@ static void arch_timer_of_configure_rate
+@@ -919,6 +920,16 @@ static void arch_timer_of_configure_rate
  	if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
  		arch_timer_rate = rate;
  

target/linux/generic/hack-5.4/221-module_exports.patch

@@ -98,7 +98,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/scripts/Makefile.build
 +++ b/scripts/Makefile.build
-@@ -353,7 +353,7 @@ targets += $(extra-y) $(MAKECMDGOALS) $(
+@@ -349,7 +349,7 @@ targets += $(extra-y) $(MAKECMDGOALS) $(
  # Linker scripts preprocessor (.lds.S -> .lds)
  # ---------------------------------------------------------------------------
  quiet_cmd_cpp_lds_S = LDS     $@

target/linux/generic/pending-5.4/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch

@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -6883,7 +6883,7 @@ static void __ref alloc_node_mem_map(str
+@@ -6884,7 +6884,7 @@ static void __ref alloc_node_mem_map(str
  		mem_map = NODE_DATA(0)->node_mem_map;
  #if defined(CONFIG_HAVE_MEMBLOCK_NODE_MAP) || defined(CONFIG_FLATMEM)
  		if (page_to_pfn(mem_map) != pgdat->node_start_pfn)

target/linux/generic/pending-5.4/190-rtc-rs5c372-support_alarms_up_to_1_week.patch

@@ -12,11 +12,9 @@ Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
  drivers/rtc/rtc-rs5c372.c | 48 ++++++++++++++++++++++++++++++++++-----
  1 file changed, 42 insertions(+), 6 deletions(-)
 
-diff --git a/drivers/rtc/rtc-rs5c372.c b/drivers/rtc/rtc-rs5c372.c
-index 3bd6eaa0d..94b778c6e 100644
 --- a/drivers/rtc/rtc-rs5c372.c
 +++ b/drivers/rtc/rtc-rs5c372.c
-@@ -393,7 +393,9 @@ static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t)
+@@ -393,7 +393,9 @@ static int rs5c_read_alarm(struct device
  {
  	struct i2c_client	*client = to_i2c_client(dev);
  	struct rs5c372		*rs5c = i2c_get_clientdata(client);
@@ -27,7 +25,7 @@ index 3bd6eaa0d..94b778c6e 100644
  
  	status = rs5c_get_regs(rs5c);
  	if (status < 0)
-@@ -403,6 +405,30 @@ static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t)
+@@ -403,6 +405,30 @@ static int rs5c_read_alarm(struct device
  	t->time.tm_sec = 0;
  	t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f);
  	t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]);
@@ -58,7 +56,7 @@ index 3bd6eaa0d..94b778c6e 100644
  
  	/* ... and status */
  	t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE);
-@@ -417,12 +443,20 @@ static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t)
+@@ -417,12 +443,20 @@ static int rs5c_set_alarm(struct device
  	struct rs5c372		*rs5c = i2c_get_clientdata(client);
  	int			status, addr, i;
  	unsigned char		buf[3];
@@ -83,7 +81,7 @@ index 3bd6eaa0d..94b778c6e 100644
  
  	/* REVISIT: round up tm_sec */
  
-@@ -443,7 +477,9 @@ static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t)
+@@ -443,7 +477,9 @@ static int rs5c_set_alarm(struct device
  	/* set alarm */
  	buf[0] = bin2bcd(t->time.tm_min);
  	buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour);

target/linux/generic/pending-5.4/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch

@@ -15,11 +15,9 @@ Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
  drivers/rtc/rtc-rs5c372.c | 16 ++++++++++++++++
  1 file changed, 16 insertions(+)
 
-diff --git a/drivers/rtc/rtc-rs5c372.c b/drivers/rtc/rtc-rs5c372.c
-index 94b778c6e..76775d66e 100644
 --- a/drivers/rtc/rtc-rs5c372.c
 +++ b/drivers/rtc/rtc-rs5c372.c
-@@ -654,6 +654,7 @@ static int rs5c372_probe(struct i2c_client *client,
+@@ -654,6 +654,7 @@ static int rs5c372_probe(struct i2c_clie
  	int err = 0;
  	int smbus_mode = 0;
  	struct rs5c372 *rs5c372;
@@ -27,7 +25,7 @@ index 94b778c6e..76775d66e 100644
  
  	dev_dbg(&client->dev, "%s\n", __func__);
  
-@@ -689,6 +690,12 @@ static int rs5c372_probe(struct i2c_client *client,
+@@ -689,6 +690,12 @@ static int rs5c372_probe(struct i2c_clie
  	else
  		rs5c372->type = id->driver_data;
  
@@ -40,7 +38,7 @@ index 94b778c6e..76775d66e 100644
  	/* we read registers 0x0f then 0x00-0x0f; skip the first one */
  	rs5c372->regs = &rs5c372->buf[1];
  	rs5c372->smbus = smbus_mode;
-@@ -722,6 +729,8 @@ static int rs5c372_probe(struct i2c_client *client,
+@@ -722,6 +729,8 @@ static int rs5c372_probe(struct i2c_clie
  		goto exit;
  	}
  
@@ -49,7 +47,7 @@ index 94b778c6e..76775d66e 100644
  	/* if the oscillator lost power and no other software (like
  	 * the bootloader) set it up, do it here.
  	 *
-@@ -748,6 +757,10 @@ static int rs5c372_probe(struct i2c_client *client,
+@@ -748,6 +757,10 @@ static int rs5c372_probe(struct i2c_clie
  			);
  
  	/* REVISIT use client->irq to register alarm irq ... */
@@ -60,7 +58,7 @@ index 94b778c6e..76775d66e 100644
  	rs5c372->rtc = devm_rtc_device_register(&client->dev,
  					rs5c372_driver.driver.name,
  					&rs5c372_rtc_ops, THIS_MODULE);
-@@ -761,6 +774,9 @@ static int rs5c372_probe(struct i2c_client *client,
+@@ -761,6 +774,9 @@ static int rs5c372_probe(struct i2c_clie
  	if (err)
  		goto exit;
  

target/linux/generic/pending-5.4/499-mtd-parser-cmdline-Fix-parsing-of-part-names-with-co.patch

-From: Sven Eckelmann <sven@narfation.org>
-Date: Sun, 22 Nov 2020 00:48:33 +0100
-Subject: [PATCH RFC] mtd: parser: cmdline: Fix parsing of part-names with colons
-
-Some devices (especially QCA ones) are already using hardcoded partition
-names with colons in it. The OpenMesh A62 for example provides following
-mtd relevant information via cmdline:
-
-  root=31:11 mtdparts=spi0.0:256k(0:SBL1),128k(0:MIBIB),384k(0:QSEE),64k(0:CDT),64k(0:DDRPARAMS),64k(0:APPSBLENV),512k(0:APPSBL),64k(0:ART),64k(custom),64k(0:KEYS),0x002b0000(kernel),0x00c80000(rootfs),15552k(inactive) rootfsname=rootfs rootwait
-
-The change to split only on the last colon between mtd-id and partitions
-will cause newpart to see following string for the first partition:
-
-  KEYS),0x002b0000(kernel),0x00c80000(rootfs),15552k(inactive)
-
-Such a partition list cannot be parsed and thus the device fails to boot.
-
-Avoid this behavior by making sure that the start of the first part-name
-("(") will also be the last byte the mtd-id split algorithm is using for
-its colon search.
-
-Forwarded: https://patchwork.ozlabs.org/project/linux-mtd/patch/20201122001533.985641-1-sven@narfation.org/
-Fixes: eb13fa022741 ("mtd: parser: cmdline: Support MTD names containing one or more colons")
-Signed-off-by: Sven Eckelmann <sven@narfation.org>
-
---- a/drivers/mtd/parsers/cmdlinepart.c
-+++ b/drivers/mtd/parsers/cmdlinepart.c
-@@ -218,7 +218,7 @@ static int mtdpart_setup_real(char *s)
- 		struct cmdline_mtd_partition *this_mtd;
- 		struct mtd_partition *parts;
- 		int mtd_id_len, num_parts;
--		char *p, *mtd_id, *semicol;
-+		char *p, *mtd_id, *semicol, *open_parenth;
- 
- 		/*
- 		 * Replace the first ';' by a NULL char so strrchr can work
-@@ -228,6 +228,13 @@ static int mtdpart_setup_real(char *s)
- 		if (semicol)
- 			*semicol = '\0';
- 
-+		/* make sure that part-names with ":" will not be handled as
-+		 * part of the mtd-id with an ":"
-+		 */
-+		open_parenth = strchr(s, '(');
-+		if (open_parenth)
-+			*open_parenth = '\0';
-+
- 		mtd_id = s;
- 
- 		/*
-@@ -237,6 +244,10 @@ static int mtdpart_setup_real(char *s)
- 		 */
- 		p = strrchr(s, ':');
- 
-+		/* Restore the '(' now. */
-+		if (open_parenth)
-+			*open_parenth = '(';
-+
- 		/* Restore the ';' now. */
- 		if (semicol)
- 			*semicol = ';';

target/linux/generic/pending-5.4/530-jffs2_make_lzma_available.patch

@@ -244,7 +244,7 @@ Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
 +}
 --- a/fs/jffs2/super.c
 +++ b/fs/jffs2/super.c
-@@ -360,14 +360,41 @@ static int __init init_jffs2_fs(void)
+@@ -377,14 +377,41 @@ static int __init init_jffs2_fs(void)
  	BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68);
  	BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32);
  

target/linux/generic/pending-5.4/610-netfilter_match_bypass_default_checks.patch

@@ -69,7 +69,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		return -ENOMEM;
  
 @@ -818,6 +846,7 @@ copy_entries_to_user(unsigned int total_
- 	const struct xt_table_info *private = table->private;
+ 	const struct xt_table_info *private = xt_table_get_private_protected(table);
  	int ret = 0;
  	const void *loc_cpu_entry;
 +	u8 flags;

target/linux/generic/pending-5.4/611-netfilter_match_bypass_default_table.patch

@@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* Initialization */
 +	WARN_ON(!(table->valid_hooks & (1 << hook)));
 +	local_bh_disable();
-+	private = READ_ONCE(table->private); /* Address dependency. */
++	private = rcu_access_pointer(table->private);
 +	cpu        = smp_processor_id();
 +	table_base = private->entries;
 +
@@ -80,7 +80,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 -	WARN_ON(!(table->valid_hooks & (1 << hook)));
 -	local_bh_disable();
  	addend = xt_write_recseq_begin();
--	private = READ_ONCE(table->private); /* Address dependency. */
+-	private = rcu_access_pointer(table->private);
 -	cpu        = smp_processor_id();
 -	table_base = private->entries;
  	jumpstack  = (struct ipt_entry **)private->jumpstack[cpu];

target/linux/ipq40xx/patches-5.4/0013-v5.6-crypto-qce-allow-building-only-hashes-ciphers.patch

+From 59e056cda4beb5412e3653e6360c2eb0fa770baa Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Fri, 20 Dec 2019 16:02:18 -0300
+Subject: [PATCH 07/11] crypto: qce - allow building only hashes/ciphers
+
+Allow the user to choose whether to build support for all algorithms
+(default), hashes-only, or skciphers-only.
+
+The QCE engine does not appear to scale as well as the CPU to handle
+multiple crypto requests.  While the ipq40xx chips have 4-core CPUs, the
+QCE handles only 2 requests in parallel.
+
+Ipsec throughput seems to improve when disabling either family of
+algorithms, sharing the load with the CPU.  Enabling skciphers-only
+appears to work best.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -617,6 +617,14 @@ config CRYPTO_DEV_QCE
+ 	tristate "Qualcomm crypto engine accelerator"
+ 	depends on ARCH_QCOM || COMPILE_TEST
+ 	depends on HAS_IOMEM
++	help
++	  This driver supports Qualcomm crypto engine accelerator
++	  hardware. To compile this driver as a module, choose M here. The
++	  module will be called qcrypto.
++
++config CRYPTO_DEV_QCE_SKCIPHER
++	bool
++	depends on CRYPTO_DEV_QCE
+ 	select CRYPTO_AES
+ 	select CRYPTO_LIB_DES
+ 	select CRYPTO_ECB
+@@ -624,10 +632,57 @@ config CRYPTO_DEV_QCE
+ 	select CRYPTO_XTS
+ 	select CRYPTO_CTR
+ 	select CRYPTO_BLKCIPHER
++
++config CRYPTO_DEV_QCE_SHA
++	bool
++	depends on CRYPTO_DEV_QCE
++
++choice
++	prompt "Algorithms enabled for QCE acceleration"
++	default CRYPTO_DEV_QCE_ENABLE_ALL
++	depends on CRYPTO_DEV_QCE
+ 	help
+-	  This driver supports Qualcomm crypto engine accelerator
+-	  hardware. To compile this driver as a module, choose M here. The
+-	  module will be called qcrypto.
++	  This option allows to choose whether to build support for all algorihtms
++	  (default), hashes-only, or skciphers-only.
++
++	  The QCE engine does not appear to scale as well as the CPU to handle
++	  multiple crypto requests.  While the ipq40xx chips have 4-core CPUs, the
++	  QCE handles only 2 requests in parallel.
++
++	  Ipsec throughput seems to improve when disabling either family of
++	  algorithms, sharing the load with the CPU.  Enabling skciphers-only
++	  appears to work best.
++
++	config CRYPTO_DEV_QCE_ENABLE_ALL
++		bool "All supported algorithms"
++		select CRYPTO_DEV_QCE_SKCIPHER
++		select CRYPTO_DEV_QCE_SHA
++		help
++		  Enable all supported algorithms:
++			- AES (CBC, CTR, ECB, XTS)
++			- 3DES (CBC, ECB)
++			- DES (CBC, ECB)
++			- SHA1, HMAC-SHA1
++			- SHA256, HMAC-SHA256
++
++	config CRYPTO_DEV_QCE_ENABLE_SKCIPHER
++		bool "Symmetric-key ciphers only"
++		select CRYPTO_DEV_QCE_SKCIPHER
++		help
++		  Enable symmetric-key ciphers only:
++			- AES (CBC, CTR, ECB, XTS)
++			- 3DES (ECB, CBC)
++			- DES (ECB, CBC)
++
++	config CRYPTO_DEV_QCE_ENABLE_SHA
++		bool "Hash/HMAC only"
++		select CRYPTO_DEV_QCE_SHA
++		help
++		  Enable hashes/HMAC algorithms only:
++			- SHA1, HMAC-SHA1
++			- SHA256, HMAC-SHA256
++
++endchoice
+ 
+ config CRYPTO_DEV_QCOM_RNG
+ 	tristate "Qualcomm Random Number Generator Driver"
+--- a/drivers/crypto/qce/Makefile
++++ b/drivers/crypto/qce/Makefile
+@@ -2,6 +2,7 @@
+ obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
+ qcrypto-objs := core.o \
+ 		common.o \
+-		dma.o \
+-		sha.o \
+-		skcipher.o
++		dma.o
++
++qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o
++qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o
+--- a/drivers/crypto/qce/common.c
++++ b/drivers/crypto/qce/common.c
+@@ -45,52 +45,56 @@ qce_clear_array(struct qce_device *qce,
+ 		qce_write(qce, offset + i * sizeof(u32), 0);
+ }
+ 
+-static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
++static u32 qce_config_reg(struct qce_device *qce, int little)
+ {
+-	u32 cfg = 0;
++	u32 beats = (qce->burst_size >> 3) - 1;
++	u32 pipe_pair = qce->pipe_pair_id;
++	u32 config;
+ 
+-	if (IS_AES(flags)) {
+-		if (aes_key_size == AES_KEYSIZE_128)
+-			cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
+-		else if (aes_key_size == AES_KEYSIZE_256)
+-			cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
+-	}
++	config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
++	config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
++		  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
++	config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
++	config &= ~HIGH_SPD_EN_N_SHIFT;
+ 
+-	if (IS_AES(flags))
+-		cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
+-	else if (IS_DES(flags) || IS_3DES(flags))
+-		cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
++	if (little)
++		config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
+ 
+-	if (IS_DES(flags))
+-		cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
++	return config;
++}
+ 
+-	if (IS_3DES(flags))
+-		cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
++void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
++{
++	__be32 *d = dst;
++	const u8 *s = src;
++	unsigned int n;
+ 
+-	switch (flags & QCE_MODE_MASK) {
+-	case QCE_MODE_ECB:
+-		cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_CBC:
+-		cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_CTR:
+-		cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_XTS:
+-		cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
+-		break;
+-	case QCE_MODE_CCM:
+-		cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
+-		cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
+-		break;
+-	default:
+-		return ~0;
++	n = len / sizeof(u32);
++	for (; n > 0; n--) {
++		*d = cpu_to_be32p((const __u32 *) s);
++		s += sizeof(__u32);
++		d++;
+ 	}
++}
+ 
+-	return cfg;
++static void qce_setup_config(struct qce_device *qce)
++{
++	u32 config;
++
++	/* get big endianness */
++	config = qce_config_reg(qce, 0);
++
++	/* clear status */
++	qce_write(qce, REG_STATUS, 0);
++	qce_write(qce, REG_CONFIG, config);
++}
++
++static inline void qce_crypto_go(struct qce_device *qce)
++{
++	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
+ }
+ 
++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
+ static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
+ {
+ 	u32 cfg = 0;
+@@ -137,88 +141,6 @@ static u32 qce_auth_cfg(unsigned long fl
+ 	return cfg;
+ }
+ 
+-static u32 qce_config_reg(struct qce_device *qce, int little)
+-{
+-	u32 beats = (qce->burst_size >> 3) - 1;
+-	u32 pipe_pair = qce->pipe_pair_id;
+-	u32 config;
+-
+-	config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
+-	config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
+-		  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
+-	config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
+-	config &= ~HIGH_SPD_EN_N_SHIFT;
+-
+-	if (little)
+-		config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
+-
+-	return config;
+-}
+-
+-void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
+-{
+-	__be32 *d = dst;
+-	const u8 *s = src;
+-	unsigned int n;
+-
+-	n = len / sizeof(u32);
+-	for (; n > 0; n--) {
+-		*d = cpu_to_be32p((const __u32 *) s);
+-		s += sizeof(__u32);
+-		d++;
+-	}
+-}
+-
+-static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
+-{
+-	u8 swap[QCE_AES_IV_LENGTH];
+-	u32 i, j;
+-
+-	if (ivsize > QCE_AES_IV_LENGTH)
+-		return;
+-
+-	memset(swap, 0, QCE_AES_IV_LENGTH);
+-
+-	for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
+-	     i < QCE_AES_IV_LENGTH; i++, j--)
+-		swap[i] = src[j];
+-
+-	qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
+-}
+-
+-static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
+-		       unsigned int enckeylen, unsigned int cryptlen)
+-{
+-	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
+-	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
+-	unsigned int xtsdusize;
+-
+-	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
+-			       enckeylen / 2);
+-	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
+-
+-	/* xts du size 512B */
+-	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
+-	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
+-}
+-
+-static void qce_setup_config(struct qce_device *qce)
+-{
+-	u32 config;
+-
+-	/* get big endianness */
+-	config = qce_config_reg(qce, 0);
+-
+-	/* clear status */
+-	qce_write(qce, REG_STATUS, 0);
+-	qce_write(qce, REG_CONFIG, config);
+-}
+-
+-static inline void qce_crypto_go(struct qce_device *qce)
+-{
+-	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
+-}
+-
+ static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
+ 				u32 totallen, u32 offset)
+ {
+@@ -303,6 +225,87 @@ go_proc:
+ 
+ 	return 0;
+ }
++#endif
++
++#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
++static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
++{
++	u32 cfg = 0;
++
++	if (IS_AES(flags)) {
++		if (aes_key_size == AES_KEYSIZE_128)
++			cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
++		else if (aes_key_size == AES_KEYSIZE_256)
++			cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
++	}
++
++	if (IS_AES(flags))
++		cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
++	else if (IS_DES(flags) || IS_3DES(flags))
++		cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
++
++	if (IS_DES(flags))
++		cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
++
++	if (IS_3DES(flags))
++		cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
++
++	switch (flags & QCE_MODE_MASK) {
++	case QCE_MODE_ECB:
++		cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_CBC:
++		cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_CTR:
++		cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_XTS:
++		cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
++		break;
++	case QCE_MODE_CCM:
++		cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
++		cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
++		break;
++	default:
++		return ~0;
++	}
++
++	return cfg;
++}
++
++static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
++{
++	u8 swap[QCE_AES_IV_LENGTH];
++	u32 i, j;
++
++	if (ivsize > QCE_AES_IV_LENGTH)
++		return;
++
++	memset(swap, 0, QCE_AES_IV_LENGTH);
++
++	for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
++	     i < QCE_AES_IV_LENGTH; i++, j--)
++		swap[i] = src[j];
++
++	qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
++}
++
++static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
++		       unsigned int enckeylen, unsigned int cryptlen)
++{
++	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
++	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
++	unsigned int xtsdusize;
++
++	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
++			       enckeylen / 2);
++	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
++
++	/* xts du size 512B */
++	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
++	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
++}
+ 
+ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
+ 				     u32 totallen, u32 offset)
+@@ -384,15 +387,20 @@ static int qce_setup_regs_skcipher(struc
+ 
+ 	return 0;
+ }
++#endif
+ 
+ int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
+ 	      u32 offset)
+ {
+ 	switch (type) {
++#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
+ 	case CRYPTO_ALG_TYPE_SKCIPHER:
+ 		return qce_setup_regs_skcipher(async_req, totallen, offset);
++#endif
++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
+ 	case CRYPTO_ALG_TYPE_AHASH:
+ 		return qce_setup_regs_ahash(async_req, totallen, offset);
++#endif
+ 	default:
+ 		return -EINVAL;
+ 	}
+--- a/drivers/crypto/qce/core.c
++++ b/drivers/crypto/qce/core.c
+@@ -22,8 +22,12 @@
+ #define QCE_QUEUE_LENGTH	1
+ 
+ static const struct qce_algo_ops *qce_ops[] = {
++#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
+ 	&skcipher_ops,
++#endif
++#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
+ 	&ahash_ops,
++#endif
+ };
+ 
+ static void qce_unregister_algs(struct qce_device *qce)

target/linux/ipq40xx/patches-5.4/0015-v5.7-crypto-qce-use-AES-fallback-for-small-requests.patch

+From ce163ba0bf298f1707321ac025ef639f88e62801 Mon Sep 17 00:00:00 2001
+From: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Date: Fri, 7 Feb 2020 12:02:26 -0300
+Subject: [PATCH 10/11] crypto: qce - use AES fallback for small requests
+
+Process small blocks using the fallback cipher, as a workaround for an
+observed failure (DMA-related, apparently) when computing the GCM ghash
+key.  This brings a speed gain as well, since it avoids the latency of
+using the hardware engine to process small blocks.
+
+Using software for all 16-byte requests would be enough to make GCM
+work, but to increase performance, a larger threshold would be better.
+Measuring the performance of supported ciphers with openssl speed,
+software matches hardware at around 768-1024 bytes.
+
+Considering the 256-bit ciphers, software is 2-3 times faster than qce
+at 256-bytes, 30% faster at 512, and about even at 768-bytes.  With
+128-bit keys, the break-even point would be around 1024-bytes.
+
+This adds the 'aes_sw_max_len' parameter, to set the largest request
+length processed by the software fallback.  Its default is being set to
+512 bytes, a little lower than the break-even point, to balance the cost
+in CPU usage.
+
+Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -684,6 +684,29 @@ choice
+ 
+ endchoice
+ 
++config CRYPTO_DEV_QCE_SW_MAX_LEN
++	int "Default maximum request size to use software for AES"
++	depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER
++	default 512
++	help
++	  This sets the default maximum request size to perform AES requests
++	  using software instead of the crypto engine.  It can be changed by
++	  setting the aes_sw_max_len parameter.
++
++	  Small blocks are processed faster in software than hardware.
++	  Considering the 256-bit ciphers, software is 2-3 times faster than
++	  qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
++	  With 128-bit keys, the break-even point would be around 1024-bytes.
++
++	  The default is set a little lower, to 512 bytes, to balance the
++	  cost in CPU usage.  The minimum recommended setting is 16-bytes
++	  (1 AES block), since AES-GCM will fail if you set it lower.
++	  Setting this to zero will send all requests to the hardware.
++
++	  Note that 192-bit keys are not supported by the hardware and are
++	  always processed by the software fallback, and all DES requests
++	  are done by the hardware.
++
+ config CRYPTO_DEV_QCOM_RNG
+ 	tristate "Qualcomm Random Number Generator Driver"
+ 	depends on ARCH_QCOM || COMPILE_TEST
+--- a/drivers/crypto/qce/skcipher.c
++++ b/drivers/crypto/qce/skcipher.c
+@@ -5,6 +5,7 @@
+ 
+ #include <linux/device.h>
+ #include <linux/interrupt.h>
++#include <linux/moduleparam.h>
+ #include <linux/types.h>
+ #include <crypto/aes.h>
+ #include <crypto/internal/des.h>
+@@ -12,6 +13,13 @@
+ 
+ #include "cipher.h"
+ 
++static unsigned int aes_sw_max_len = CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN;
++module_param(aes_sw_max_len, uint, 0644);
++MODULE_PARM_DESC(aes_sw_max_len,
++		 "Only use hardware for AES requests larger than this "
++		 "[0=always use hardware; anything <16 breaks AES-GCM; default="
++		 __stringify(CONFIG_CRYPTO_DEV_QCE_SOFT_THRESHOLD)"]");
++
+ static LIST_HEAD(skcipher_algs);
+ 
+ static void qce_skcipher_done(void *data)
+@@ -166,15 +174,10 @@ static int qce_skcipher_setkey(struct cr
+ 	switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
+ 	case AES_KEYSIZE_128:
+ 	case AES_KEYSIZE_256:
++		memcpy(ctx->enc_key, key, keylen);
+ 		break;
+-	default:
+-		goto fallback;
+ 	}
+ 
+-	ctx->enc_keylen = keylen;
+-	memcpy(ctx->enc_key, key, keylen);
+-	return 0;
+-fallback:
+ 	ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
+ 	if (!ret)
+ 		ctx->enc_keylen = keylen;
+@@ -224,8 +227,9 @@ static int qce_skcipher_crypt(struct skc
+ 	rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
+ 	keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
+ 
+-	if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 &&
+-	    keylen != AES_KEYSIZE_256) {
++	if (IS_AES(rctx->flags) &&
++	    ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
++	     req->cryptlen <= aes_sw_max_len)) {
+ 		SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
+ 
+ 		skcipher_request_set_sync_tfm(subreq, ctx->fallback);

target/linux/ipq806x/patches-5.4/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch

@@ -358,4 +358,4 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
 +	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
  	{},
  };
- 
+ MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);

target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch

+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1838,6 +1838,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
+ 	  Only command line ATAG will be processed, the rest of the ATAGs
+ 	  sent by bootloader will be ignored.
+ 
++config CMDLINE_OVERRIDE
++    bool "Use alternative cmdline from device tree"
++    help
++      Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++      be used, this is not a good option for kernels that are shared across
++      devices. This setting enables using "chosen/cmdline-override" as the
++      cmdline if it exists in the device tree.
++
+ endchoice
+ 
+ config CMDLINE
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1060,6 +1060,17 @@ int __init early_init_dt_scan_chosen(uns
+ 	if (p != NULL && l > 0)
+ 		strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
+ 
++    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++     * device tree option of chosen/bootargs-override. This is
++     * helpful on boards where u-boot sets bootargs, and is unable
++     * to be modified.
++     */
++#ifdef CONFIG_CMDLINE_OVERRIDE
++	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++	if (p != NULL && l > 0)
++		strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
++#endif
++
+ 	/*
+ 	 * CONFIG_CMDLINE is meant to be a default in case nothing else
+ 	 * managed to set the command line, unless CONFIG_CMDLINE_FORCE

target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch

@@ -48,7 +48,7 @@ Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
  			ethernet@0,4 {
  				compatible = "fsl,enetc-ptp";
  				reg = <0x000400 0 0 0 0>;
- 				clocks = <&clockgen 4 0>;
+ 				clocks = <&clockgen 2 3>;
  				little-endian;
  			};
 +			switch@0,5 {

target/linux/layerscape/patches-5.4/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch

@@ -386,7 +386,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
 @@ -774,30 +774,39 @@
- 				clocks = <&clockgen 4 0>;
+ 				clocks = <&clockgen 2 3>;
  				little-endian;
  			};
 -			switch@0,5 {

target/linux/layerscape/patches-5.4/701-net-0142-bus-fsl-mc-Some-apis-are-made-public-for-vfio.patch

@@ -18,7 +18,7 @@ Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
 
 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c
 +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c
-@@ -547,6 +547,7 @@ void fsl_mc_init_all_resource_pools(stru
+@@ -549,6 +549,7 @@ void fsl_mc_init_all_resource_pools(stru
  		mutex_init(&res_pool->mutex);
  	}
  }
@@ -26,7 +26,7 @@ Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
  
  static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev,
  					 enum fsl_mc_pool_type pool_type)
-@@ -571,6 +572,7 @@ void fsl_mc_cleanup_all_resource_pools(s
+@@ -573,6 +574,7 @@ void fsl_mc_cleanup_all_resource_pools(s
  	for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++)
  		fsl_mc_cleanup_resource_pool(mc_bus_dev, pool_type);
  }

target/linux/mediatek/patches-5.4/0001-v5.7-spi-make-spi-max-frequency-optional.patch

@@ -20,7 +20,7 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -1802,13 +1802,8 @@ static int of_spi_parse_dt(struct spi_co
+@@ -1803,13 +1803,8 @@ static int of_spi_parse_dt(struct spi_co
  		spi->mode |= SPI_CS_HIGH;
  
  	/* Device speed */

target/linux/mediatek/patches-5.4/0303-mtd-spinand-disable-on-die-ECC.patch

@@ -11,7 +11,7 @@ Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
 
 --- a/drivers/mtd/nand/spi/core.c
 +++ b/drivers/mtd/nand/spi/core.c
-@@ -491,7 +491,7 @@ static int spinand_mtd_read(struct mtd_i
+@@ -495,7 +495,7 @@ static int spinand_mtd_read(struct mtd_i
  	int ret = 0;
  
  	if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
@@ -20,7 +20,7 @@ Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
  
  	mutex_lock(&spinand->lock);
  
-@@ -539,7 +539,7 @@ static int spinand_mtd_write(struct mtd_
+@@ -543,7 +543,7 @@ static int spinand_mtd_write(struct mtd_
  	int ret = 0;
  
  	if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)

target/linux/mediatek/patches-5.4/0600-net-phylink-propagate-resolved-link-config-via-mac_l.patch

@@ -95,7 +95,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	netif_tx_start_all_queues(port->dev);
-@@ -5125,8 +5129,11 @@ static void mvpp2_mac_config(struct phyl
+@@ -5126,8 +5130,11 @@ static void mvpp2_mac_config(struct phyl
  	mvpp2_port_enable(port);
  }
  
@@ -107,8 +107,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +			      int speed, int duplex,
 +			      bool tx_pause, bool rx_pause)
  {
- 	struct net_device *dev = to_net_dev(config->dev);
- 	struct mvpp2_port *port = netdev_priv(dev);
+ 	struct mvpp2_port *port = mvpp2_phylink_to_port(config);
+ 	u32 val;
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 @@ -449,9 +449,10 @@ static void mtk_mac_link_down(struct phy

target/linux/mvebu/patches-5.4/007-gpio-mvebu-avoid_error_message_for_optional_IRQ.patch

@@ -18,11 +18,9 @@ Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
  drivers/gpio/gpio-mvebu.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
-diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
-index d2b999c7987f1..3c9f4fb3d5a28 100644
 --- a/drivers/gpio/gpio-mvebu.c
 +++ b/drivers/gpio/gpio-mvebu.c
-@@ -1245,7 +1245,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
+@@ -1253,7 +1253,7 @@ static int mvebu_gpio_probe(struct platf
  	 * pins.
  	 */
  	for (i = 0; i < 4; i++) {