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未验证 提交 92beddf3 编写于 作者: B Bernard Xiong 提交者： GitHub
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Merge pull request #4737 from mysterywolf/3,1,xformat 

[lts 3.1.x] format codes
上级 b18a99b4 03f4d40e
展开全部 隐藏空白更改
内联 并排
Showing with 32218 addition and 32218 deletion

要显示的变更太多。

To preserve performance only 1000 of 1000+ files are displayed.
文本差异 电子邮件补丁
bsp/CME_M7/applications/application.c
浏览文件 @ 92beddf3
...@@ -28,10 +28,10 @@ int rt_application_init() ...@@ -28,10 +28,10 @@ int rt_application_init()
tid = rt_thread_create("init", tid = rt_thread_create("init",
rt_init_thread_entry, rt_init_thread_entry,
RT_NULL, RT_NULL,
2048, 2048,
RT_THREAD_PRIORITY_MAX/3, RT_THREAD_PRIORITY_MAX/3,
20); 20);
if (tid != RT_NULL) if (tid != RT_NULL)
rt_thread_startup(tid); rt_thread_startup(tid);
......
bsp/CME_M7/applications/startup.c
浏览文件 @ 92beddf3
/* /*
* File : startup.c * File : startup.c
* This file is part of RT-Thread RTOS * This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2014, RT-Thread Develop Team * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
......
bsp/CME_M7/drivers/board.h
浏览文件 @ 92beddf3
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#include "cmem7_includes.h" #include "cmem7_includes.h"
//#include "cmem7_retarget.h" //#include "cmem7_retarget.h"
#define SRAM_SIZE 64 // KB #define SRAM_SIZE 64 // KB
#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) #define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
//#define RT_USING_UART0 //#define RT_USING_UART0
......
bsp/CME_M7/drivers/emac.c
浏览文件 @ 92beddf3
/* /*
* File : emac.c * File : emac.c
* This file is part of RT-Thread RTOS * This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2014, RT-Thread Develop Team * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
...@@ -38,7 +38,7 @@ struct rt_cme_eth ...@@ -38,7 +38,7 @@ struct rt_cme_eth
struct eth_device parent; struct eth_device parent;
/* interface address info. */ /* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
uint32_t ETH_Speed; uint32_t ETH_Speed;
uint32_t ETH_Mode; uint32_t ETH_Mode;
...@@ -95,8 +95,8 @@ uint32_t txTotalMemory = 0x2000; ...@@ -95,8 +95,8 @@ uint32_t txTotalMemory = 0x2000;
BOOL isRxNoBuf = FALSE; BOOL isRxNoBuf = FALSE;
#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ #define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_RXBUFNB 4 #define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2 #define ETH_TXBUFNB 2
struct eth_rx_buffer struct eth_rx_buffer
{ {
......
bsp/CME_M7/rtconfig.h
浏览文件 @ 92beddf3
...@@ -3,16 +3,16 @@ ...@@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__ #define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/ /* RT_NAME_MAX*/
#define RT_NAME_MAX 8 #define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/ /* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4 #define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */ /* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32 #define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second */ /* Tick per Second */
#define RT_TICK_PER_SECOND 100 #define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */ /* SECTION: RT_DEBUG */
/* Thread Debug */ /* Thread Debug */
...@@ -61,8 +61,8 @@ ...@@ -61,8 +61,8 @@
/* SECTION: Console options */ /* SECTION: Console options */
#define RT_USING_CONSOLE #define RT_USING_CONSOLE
/* the buffer size of console*/ /* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart2" #define RT_CONSOLE_DEVICE_NAME "uart2"
/* SECTION: finsh, a C-Express shell */ /* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH #define RT_USING_FINSH
...@@ -79,15 +79,15 @@ ...@@ -79,15 +79,15 @@
#define RT_USING_DFS_ELMFAT #define RT_USING_DFS_ELMFAT
#define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_WORD_ACCESS #define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_DRIVES 1 #define RT_DFS_ELM_DRIVES 1
#define RT_DFS_ELM_USE_LFN 2 #define RT_DFS_ELM_USE_LFN 2
#define RT_DFS_ELM_MAX_LFN 255 #define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* the max number of mounted filesystem */ /* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */ /* the max number of opened files */
#define DFS_FD_MAX 4 #define DFS_FD_MAX 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* SECTION: lwip, a lighwight TCP/IP protocol stack */
#define RT_USING_LWIP #define RT_USING_LWIP
...@@ -121,13 +121,13 @@ ...@@ -121,13 +121,13 @@
#define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_MSKADDR "255.255.255.0"
/* tcp thread options */ /* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12 #define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 #define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_PRIORITY 15 #define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512 #define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" /> // <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
// #define RT_USING_CMSIS_OS // #define RT_USING_CMSIS_OS
......
bsp/allwinner_tina/drivers/drv_clock.c
浏览文件 @ 92beddf3
...@@ -527,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) ...@@ -527,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
*mmc_clk &= ~(0x1 << 31); *mmc_clk &= ~(0x1 << 31);
return RT_EOK; return RT_EOK;
} }
if (hz <= 24000000) if (hz <= 24000000)
{ {
pll = (0x0 << 24); pll = (0x0 << 24);
...@@ -579,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) ...@@ -579,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
oclk_dly = 1; oclk_dly = 1;
sclk_dly = 4; sclk_dly = 4;
} }
*mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \ *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
(n << 16) | (oclk_dly << 8) | (div - 1); (n << 16) | (oclk_dly << 8) | (div - 1);
......
bsp/allwinner_tina/drivers/drv_clock.h
浏览文件 @ 92beddf3
...@@ -238,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate); ...@@ -238,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate); rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz); rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
#endif #endif
\ No newline at end of file
bsp/allwinner_tina/drivers/drv_gpio.h
浏览文件 @ 92beddf3
...@@ -227,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler); ...@@ -227,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler);
void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg); void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg);
int rt_hw_gpio_init(void); int rt_hw_gpio_init(void);
#endif /* __DRV_GPIO_H__ */ #endif /* __DRV_GPIO_H__ */
\ No newline at end of file
bsp/allwinner_tina/drivers/drv_sdio.c
浏览文件 @ 92beddf3
...@@ -20,10 +20,10 @@ ...@@ -20,10 +20,10 @@
#define DBG_TAG "MMC" #define DBG_TAG "MMC"
// #define DBG_LVL DBG_LOG // #define DBG_LVL DBG_LOG
// #define DBG_LVL DBG_INFO // #define DBG_LVL DBG_INFO
#define DBG_LVL DBG_WARNING #define DBG_LVL DBG_WARNING
// #define DBG_LVL DBG_ERROR // #define DBG_LVL DBG_ERROR
#include <rtdbg.h> #include <rtdbg.h>
#ifdef RT_USING_SDIO #ifdef RT_USING_SDIO
...@@ -33,12 +33,12 @@ ...@@ -33,12 +33,12 @@
struct mmc_xfe_des struct mmc_xfe_des
{ {
rt_uint32_t size; /* block size */ rt_uint32_t size; /* block size */
rt_uint32_t num; /* block num */ rt_uint32_t num; /* block num */
rt_uint8_t *buff; /* buff addr */ rt_uint8_t *buff; /* buff addr */
rt_uint32_t flag; /* write or read or stream */ rt_uint32_t flag; /* write or read or stream */
#define MMC_DATA_WRITE (1 << 0) #define MMC_DATA_WRITE (1 << 0)
#define MMC_DATA_READ (1 << 1) #define MMC_DATA_READ (1 << 1)
#define MMC_DATA_STREAM (1 << 2) #define MMC_DATA_STREAM (1 << 2)
}; };
struct mmc_flag struct mmc_flag
...@@ -57,7 +57,7 @@ struct sdio_drv ...@@ -57,7 +57,7 @@ struct sdio_drv
tina_mmc_t mmc_des; tina_mmc_t mmc_des;
rt_uint8_t *mmc_buf; rt_uint8_t *mmc_buf;
rt_uint8_t usedma; rt_uint8_t usedma;
}; };
#ifdef CONFIG_MMC_USE_DMA #ifdef CONFIG_MMC_USE_DMA
...@@ -122,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc) ...@@ -122,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc)
mmc->risr_reg = mmc->risr_reg; mmc->risr_reg = mmc->risr_reg;
return RT_EOK; return RT_EOK;
} }
static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
{ {
ALIGN(32) static struct mmc_des_v4p1 pdes[128]; // mast ALIGN(32) ALIGN(32) static struct mmc_des_v4p1 pdes[128]; // mast ALIGN(32)
...@@ -131,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) ...@@ -131,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
unsigned length = xfe->size * xfe->num; unsigned length = xfe->size * xfe->num;
unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT; unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT;
unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1); unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1);
if (remain) if (remain)
{ {
buff_frag_num ++; buff_frag_num ++;
...@@ -142,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) ...@@ -142,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
} }
memset(pdes, 0, sizeof(pdes)); memset(pdes, 0, sizeof(pdes));
mmu_clean_dcache((rt_uint32_t)(xfe->buff), length); mmu_clean_dcache((rt_uint32_t)(xfe->buff), length);
for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++)
{ {
// memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1)); // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
pdes[des_idx].des_chain = 1; pdes[des_idx].des_chain = 1;
...@@ -168,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) ...@@ -168,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
pdes[des_idx].last_des = 1; pdes[des_idx].last_des = 1;
pdes[des_idx].end_of_ring = 1; pdes[des_idx].end_of_ring = 1;
pdes[des_idx].buf_addr_ptr2 = 0; pdes[des_idx].buf_addr_ptr2 = 0;
} }
else else
{ {
pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1]; pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1];
} }
...@@ -203,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) ...@@ -203,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
mmc->dmac_reg = (1 << 1) | (1 << 7); /* idma on */ mmc->dmac_reg = (1 << 1) | (1 << 7); /* idma on */
rval = mmc->idie_reg & (~3); rval = mmc->idie_reg & (~3);
if (xfe->flag == MMC_DATA_WRITE) if (xfe->flag == MMC_DATA_WRITE)
rval |= (1 << 0); rval |= (1 << 0);
else else
rval |= (1 << 1); rval |= (1 << 1);
mmc->idie_reg = rval; mmc->idie_reg = rval;
...@@ -222,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) ...@@ -222,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
if (xfe->flag == MMC_DATA_WRITE) if (xfe->flag == MMC_DATA_WRITE)
{ {
for (i = 0; i < (byte_cnt >> 2); i++) for (i = 0; i < (byte_cnt >> 2); i++)
{ {
while(--timeout && (mmc->star_reg & (1 << 3))); while(--timeout && (mmc->star_reg & (1 << 3)));
...@@ -237,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) ...@@ -237,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
} }
else else
{ {
for (i = 0; i < (byte_cnt >> 2); i++) for (i = 0; i < (byte_cnt >> 2); i++)
{ {
while(--timeout && (mmc->star_reg & (1 << 2))); while(--timeout && (mmc->star_reg & (1 << 2)));
...@@ -276,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) ...@@ -276,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
{ {
mmc_set_clk(SDMMC1, clk); mmc_set_clk(SDMMC1, clk);
} }
/* Re-enable card clock */ /* Re-enable card clock */
rval = mmc->ckcr_reg; rval = mmc->ckcr_reg;
rval |= (0x1 << 16); //(3 << 16); rval |= (0x1 << 16); //(3 << 16);
...@@ -369,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) ...@@ -369,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
cmdval |= (1 << 7); cmdval |= (1 << 7);
if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4)) if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4))
cmdval |= (1 << 8); cmdval |= (1 << 8);
if (data) if (data)
{ {
cmdval |= (1 << 9) | (1 << 13); cmdval |= (1 << 9) | (1 << 13);
...@@ -592,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r ...@@ -592,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
memset(&sdio->flag, 0, sizeof(struct mmc_flag)); memset(&sdio->flag, 0, sizeof(struct mmc_flag));
mmc_send_cmd(host, req->cmd); mmc_send_cmd(host, req->cmd);
return; return;
} }
......
bsp/allwinner_tina/drivers/drv_sdio.h
浏览文件 @ 92beddf3
...@@ -119,8 +119,8 @@ REG[31] : Load cmd ...@@ -119,8 +119,8 @@ REG[31] : Load cmd
#define SDXC_UPDATE_CLOCK_CMD BIT(21) #define SDXC_UPDATE_CLOCK_CMD BIT(21)
#define SDXC_LOAD_CMD BIT(31) #define SDXC_LOAD_CMD BIT(31)
/* /*
SD status reg SD status reg
REG[0] : FIFO_RX_LEVEL REG[0] : FIFO_RX_LEVEL
REG[1] : FIFO_TX_LEVEL REG[1] : FIFO_TX_LEVEL
REG[2] : FIFO_EMPTY REG[2] : FIFO_EMPTY
...@@ -129,7 +129,7 @@ REG[4-7] : FSM_STA ...@@ -129,7 +129,7 @@ REG[4-7] : FSM_STA
REG[8] : CARD_PRESENT REG[8] : CARD_PRESENT
REG[9] : CARD_BUSY REG[9] : CARD_BUSY
REG[10] : FSM_BUSY REG[10] : FSM_BUSY
REG[11-16]: RESP_IDX REG[11-16]: RESP_IDX
REG[17-21]: FIFO_LEVEL REG[17-21]: FIFO_LEVEL
REG[31] : DMA_REQ REG[31] : DMA_REQ
*/ */
......
bsp/allwinner_tina/drivers/drv_uart.c
浏览文件 @ 92beddf3
...@@ -310,4 +310,4 @@ void uart_irq_handler(int irqno, void *param) ...@@ -310,4 +310,4 @@ void uart_irq_handler(int irqno, void *param)
} }
#endif #endif
\ No newline at end of file
bsp/allwinner_tina/drivers/spi/drv_spi_flash.c
浏览文件 @ 92beddf3
...@@ -51,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init); ...@@ -51,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init);
#endif #endif
#endif #endif
\ No newline at end of file
bsp/amebaz/drivers/board.c
浏览文件 @ 92beddf3
...@@ -40,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...) ...@@ -40,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...)
* length. */ * length. */
length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args);
if (length > RT_CONSOLEBUF_SIZE - 1) if (length > RT_CONSOLEBUF_SIZE - 1)
length = RT_CONSOLEBUF_SIZE - 1; length = RT_CONSOLEBUF_SIZE - 1;
rt_kprintf("%s", rt_log_buf); rt_kprintf("%s", rt_log_buf);
va_end(args); va_end(args);
} }
...@@ -85,11 +85,11 @@ void rt_hw_board_init(void) ...@@ -85,11 +85,11 @@ void rt_hw_board_init(void)
#ifdef RT_USING_HEAP #ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif #endif
#ifdef RT_USING_COMPONENTS_INIT #ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init(); rt_components_board_init();
#endif #endif
#ifdef RT_USING_CONSOLE #ifdef RT_USING_CONSOLE
rt_hw_uart_init(); rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME); rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
......
bsp/amebaz/drivers/drv_uart.c
浏览文件 @ 92beddf3
...@@ -111,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial) ...@@ -111,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial)
{ {
struct device_uart* uart = serial->parent.user_data; struct device_uart* uart = serial->parent.user_data;
if(!serial_readable(&uart->serial)) if(!serial_readable(&uart->serial))
return -1; return -1;
/* Receive Data Available */ /* Receive Data Available */
...@@ -126,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui ...@@ -126,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui
static void ameba_uart_irq(uint32_t id, SerialIrq event) static void ameba_uart_irq(uint32_t id, SerialIrq event)
{ {
struct rt_serial_device *serial = (struct rt_serial_device *)id; struct rt_serial_device *serial = (struct rt_serial_device *)id;
if(event == RxIrq) if(event == RxIrq)
{ {
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
} }
else if(event == TxIrq) else if(event == TxIrq)
{ {
} }
} }
static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg); static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
...@@ -141,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c); ...@@ -141,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c);
static int dbg_getc(struct rt_serial_device *serial); static int dbg_getc(struct rt_serial_device *serial);
static struct rt_serial_device ameba_dbg_serial; static struct rt_serial_device ameba_dbg_serial;
const struct rt_uart_ops _ambed_dbg_ops = const struct rt_uart_ops _ambed_dbg_ops =
{ {
dbg_configure, dbg_configure,
dbg_control, dbg_control,
...@@ -163,7 +163,7 @@ void dbg_uart_irq_handler(void * data) ...@@ -163,7 +163,7 @@ void dbg_uart_irq_handler(void * data)
DiagSetIsrEnReg(0); DiagSetIsrEnReg(0);
rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND); rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND);
DiagSetIsrEnReg(IrqEn); DiagSetIsrEnReg(IrqEn);
} }
...@@ -178,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg) ...@@ -178,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg)
case RT_DEVICE_CTRL_SET_INT: case RT_DEVICE_CTRL_SET_INT:
/* install interrupt */ /* install interrupt */
DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
/* Enable the UART Interrupt */ /* Enable the UART Interrupt */
NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
break; break;
} }
...@@ -200,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial) ...@@ -200,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial)
if(!UART_Readable(UART2_DEV)) if(!UART_Readable(UART2_DEV))
return -1; return -1;
c = DiagGetChar(_FALSE); c = DiagGetChar(_FALSE);
return c; return c;
} }
/* /*
* UART Initiation * UART Initiation
*/ */
...@@ -217,7 +217,7 @@ int rt_hw_uart_init(void) ...@@ -217,7 +217,7 @@ int rt_hw_uart_init(void)
#ifdef BSP_USING_UART0 #ifdef BSP_USING_UART0
{ {
struct device_uart *uart; struct device_uart *uart;
serial = &serial0; serial = &serial0;
uart = &uart0; uart = &uart0;
...@@ -242,7 +242,7 @@ int rt_hw_uart_init(void) ...@@ -242,7 +242,7 @@ int rt_hw_uart_init(void)
serial->ops = &_ambed_dbg_ops; serial->ops = &_ambed_dbg_ops;
serial->config = config; serial->config = config;
rt_hw_serial_register(serial, rt_hw_serial_register(serial,
RT_CONSOLE_DEVICE_NAME, RT_CONSOLE_DEVICE_NAME,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
......
bsp/amebaz/drivers/wlan/drv_wifi.c
浏览文件 @ 92beddf3
...@@ -101,7 +101,7 @@ void netif_pre_sleep_processing(void) ...@@ -101,7 +101,7 @@ void netif_pre_sleep_processing(void)
} }
unsigned char *rltk_wlan_get_ip(int idx) unsigned char *rltk_wlan_get_ip(int idx)
{ {
struct ameba_wifi *wifi; struct ameba_wifi *wifi;
wifi = rthw_wifi_get_dev(idx); wifi = rthw_wifi_get_dev(idx);
...@@ -116,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx) ...@@ -116,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx)
int netif_is_valid_IP(int idx, unsigned char *ip_dest) int netif_is_valid_IP(int idx, unsigned char *ip_dest)
{ {
LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__,
ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]); ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]);
return 1; return 1;
} }
...@@ -362,9 +362,9 @@ static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, str ...@@ -362,9 +362,9 @@ static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, str
ssid = &sta_info->ssid.val[0]; ssid = &sta_info->ssid.val[0];
if (sta_info->key.len > 0) if (sta_info->key.len > 0)
key = &sta_info->key.val[0]; key = &sta_info->key.val[0];
LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d",
sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5], sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5],
ssid, ssid,
sta_info->ssid.len, sta_info->ssid.len,
key, key,
sta_info->key.len sta_info->key.len
...@@ -594,7 +594,7 @@ exit: ...@@ -594,7 +594,7 @@ exit:
return RT_EOK; return RT_EOK;
} }
static const struct rt_wlan_dev_ops ops = static const struct rt_wlan_dev_ops ops =
{ {
.wlan_init = rthw_wlan_init , .wlan_init = rthw_wlan_init ,
.wlan_mode = rthw_wlan_mode , .wlan_mode = rthw_wlan_mode ,
......
bsp/amebaz/drivers/wlan/drv_wifi.h
浏览文件 @ 92beddf3
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Date Author Notes * Date Author Notes
* 2017-5-30 Bernard the first version * 2017-5-30 Bernard the first version
*/ */
#ifndef __DRV_WIFI_H__ #ifndef __DRV_WIFI_H__
#define __DRV_WIFI_H__ #define __DRV_WIFI_H__
......
bsp/amebaz/drivers/wlan/drv_wlan.c
浏览文件 @ 92beddf3
...@@ -137,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel) ...@@ -137,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel)
return -1; return -1;
} }
while(1) while(1)
{ {
char essid[33]; char essid[33];
if(wext_get_ssid(name, (unsigned char *) essid) > 0) if(wext_get_ssid(name, (unsigned char *) essid) > 0)
{ {
if(strcmp((const char *) essid, (const char *)ssid) == 0) if(strcmp((const char *) essid, (const char *)ssid) == 0)
{ {
rt_kprintf("%s started\n", ssid); rt_kprintf("%s started\n", ssid);
break; break;
} }
} }
if(timeout == 0) if(timeout == 0)
{ {
rt_kprintf("Start AP timeout\n"); rt_kprintf("Start AP timeout\n");
return -1; return -1;
} }
rt_thread_delay(1 * RT_TICK_PER_SECOND); rt_thread_delay(1 * RT_TICK_PER_SECOND);
...@@ -169,7 +169,7 @@ static int rthw_wifi_disconnect(char *name) ...@@ -169,7 +169,7 @@ static int rthw_wifi_disconnect(char *name)
if (name == RT_NULL) if (name == RT_NULL)
return -1; return -1;
if (wext_get_ssid(name, (unsigned char *) essid) < 0) if (wext_get_ssid(name, (unsigned char *) essid) < 0)
{ {
rt_kprintf("\nWIFI disconnected!\n"); rt_kprintf("\nWIFI disconnected!\n");
return -1; return -1;
...@@ -189,7 +189,7 @@ static int rthw_wifi_disconnect(char *name) ...@@ -189,7 +189,7 @@ static int rthw_wifi_disconnect(char *name)
break; break;
} }
if(timeout == 0) if(timeout == 0)
{ {
rt_kprintf("ERROR: Deassoc timeout!\n"); rt_kprintf("ERROR: Deassoc timeout!\n");
return -1; return -1;
...@@ -245,7 +245,7 @@ int rthw_wifi_ap_disconnect(void) ...@@ -245,7 +245,7 @@ int rthw_wifi_ap_disconnect(void)
int rthw_wifi_rssi_get(void) int rthw_wifi_rssi_get(void)
{ {
int rssi = 0; int rssi = 0;
wifi_get_rssi(&rssi); wifi_get_rssi(&rssi);
return rssi; return rssi;
} }
......
bsp/amebaz/drivers/wlan/drv_wlan.h
浏览文件 @ 92beddf3
...@@ -11,14 +11,14 @@ ...@@ -11,14 +11,14 @@
#ifndef __DRV_WLAN_H__ #ifndef __DRV_WLAN_H__
#define __DRV_WLAN_H__ #define __DRV_WLAN_H__
typedef enum typedef enum
{ {
RTHW_MODE_NONE = 0, RTHW_MODE_NONE = 0,
RTHW_MODE_STA, RTHW_MODE_STA,
RTHW_MODE_AP, RTHW_MODE_AP,
RTHW_MODE_STA_AP, RTHW_MODE_STA_AP,
RTHW_MODE_PROMISC, RTHW_MODE_PROMISC,
RTHW_MODE_P2P RTHW_MODE_P2P
}rthw_mode_t; }rthw_mode_t;
#define SHARED_ENABLED 0x00008000 #define SHARED_ENABLED 0x00008000
...@@ -52,7 +52,7 @@ typedef enum { ...@@ -52,7 +52,7 @@ typedef enum {
typedef enum { typedef enum {
RTHW_WIFI_EVENT_CONNECT = 0, RTHW_WIFI_EVENT_CONNECT = 0,
RTHW_WIFI_EVENT_DISCONNECT = 1, RTHW_WIFI_EVENT_DISCONNECT = 1,
RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3, RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3,
RTHW_WIFI_EVENT_SCAN_DONE = 4, RTHW_WIFI_EVENT_SCAN_DONE = 4,
RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5, RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5,
......
bsp/apollo2/board/adc.c
浏览文件 @ 92beddf3
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
struct rt_messagequeue adcbat_mq; struct rt_messagequeue adcbat_mq;
#define BATTERY_GPIO 35 /* Battery */ #define BATTERY_GPIO 35 /* Battery */
#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 #define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7
#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */ #define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */
#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */ #define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */
...@@ -38,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz ...@@ -38,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz
if (channel == BATTERY_ADC_CHANNELNUM) if (channel == BATTERY_ADC_CHANNELNUM)
{ {
/* wait adc message forever */ /* wait adc message forever */
rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER); rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER);
} }
......
bsp/apollo2/board/gpio.c
浏览文件 @ 92beddf3
...@@ -56,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) ...@@ -56,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
else if (value == PIN_HIGH) else if (value == PIN_HIGH)
{ {
am_hal_gpio_out_bit_set(pin); am_hal_gpio_out_bit_set(pin);
} }
} }
int am_pin_read(rt_device_t dev, rt_base_t pin) int am_pin_read(rt_device_t dev, rt_base_t pin)
......
bsp/apollo2/board/gpio.h
浏览文件 @ 92beddf3
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Date Author Notes * Date Author Notes
* 2017-09-16 Haley the first version * 2017-09-16 Haley the first version
*/ */
#ifndef __GPIO_H #ifndef __GPIO_H
#define __GPIO_H #define __GPIO_H
......
bsp/apollo2/board/i2c.c
浏览文件 @ 92beddf3
...@@ -119,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops = ...@@ -119,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops =
}; };
#ifdef RT_USING_I2C0 #ifdef RT_USING_I2C0
static struct am_i2c_bus am_i2c_bus_0 = static struct am_i2c_bus am_i2c_bus_0 =
{ {
{0}, {0},
AM_I2C0_IOM_INST AM_I2C0_IOM_INST
...@@ -127,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 = ...@@ -127,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 =
#endif #endif
#ifdef RT_USING_I2C1 #ifdef RT_USING_I2C1
static struct am_i2c_bus am_i2c_bus_1 = static struct am_i2c_bus am_i2c_bus_1 =
{ {
{1}, {1},
AM_I2C1_IOM_INST AM_I2C1_IOM_INST
...@@ -135,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 = ...@@ -135,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 =
#endif #endif
#ifdef RT_USING_I2C2 #ifdef RT_USING_I2C2
static struct am_i2c_bus am_i2c_bus_2 = static struct am_i2c_bus am_i2c_bus_2 =
{ {
{2}, {2},
AM_I2C2_IOM_INST AM_I2C2_IOM_INST
...@@ -143,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 = ...@@ -143,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 =
#endif #endif
#ifdef RT_USING_I2C3 #ifdef RT_USING_I2C3
static struct am_i2c_bus am_i2c_bus_3 = static struct am_i2c_bus am_i2c_bus_3 =
{ {
{3}, {3},
AM_I2C3_IOM_INST AM_I2C3_IOM_INST
...@@ -151,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 = ...@@ -151,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 =
#endif #endif
#ifdef RT_USING_I2C4 #ifdef RT_USING_I2C4
static struct am_i2c_bus am_i2c_bus_4 = static struct am_i2c_bus am_i2c_bus_4 =
{ {
{4}, {4},
AM_I2C4_IOM_INST AM_I2C4_IOM_INST
......
bsp/apollo2/board/pdm.c
浏览文件 @ 92beddf3
...@@ -52,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) ...@@ -52,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size)
{ {
rt_uint8_t pdm_rbufftemp[340]; rt_uint8_t pdm_rbufftemp[340];
/* wait pdm message forever */ /* wait pdm message forever */
rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER); rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER);
/* copy the data */ /* copy the data */
......
bsp/apollo2/board/rtc.c
浏览文件 @ 92beddf3
...@@ -101,7 +101,7 @@ int rt_hw_rtc_init(void) ...@@ -101,7 +101,7 @@ int rt_hw_rtc_init(void)
/* Select LFRC for RTC clock source */ /* Select LFRC for RTC clock source */
am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC); am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC);
#endif #endif
#if RTC_CLK_SRC == XT #if RTC_CLK_SRC == XT
/* Enable the XT for the RTC */ /* Enable the XT for the RTC */
am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT); am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT);
...@@ -114,12 +114,12 @@ int rt_hw_rtc_init(void) ...@@ -114,12 +114,12 @@ int rt_hw_rtc_init(void)
am_hal_rtc_osc_enable(); am_hal_rtc_osc_enable();
/* register rtc device */ /* register rtc device */
rtc.type = RT_Device_Class_RTC; rtc.type = RT_Device_Class_RTC;
rtc.init = RT_NULL; rtc.init = RT_NULL;
rtc.open = rt_rtc_open; rtc.open = rt_rtc_open;
rtc.close = RT_NULL; rtc.close = RT_NULL;
rtc.read = rt_rtc_read; rtc.read = rt_rtc_read;
rtc.write = RT_NULL; rtc.write = RT_NULL;
rtc.control = rt_rtc_control; rtc.control = rt_rtc_control;
/* no private */ /* no private */
......
bsp/apollo2/board/rtc.h
浏览文件 @ 92beddf3
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Date Author Notes * Date Author Notes
* 2017-09-14 Haley the first version * 2017-09-14 Haley the first version
*/ */
#ifndef __RTC_H #ifndef __RTC_H
#define __RTC_H #define __RTC_H
......
bsp/apollo2/board/smbus.c
浏览文件 @ 92beddf3
...@@ -28,8 +28,8 @@ ...@@ -28,8 +28,8 @@
#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ #define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */
#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ #define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */
#define ACK 0 #define ACK 0
#define NACK 1 #define NACK 1
/* SCL keep time */ /* SCL keep time */
static void keep_delay(void) static void keep_delay(void)
...@@ -46,7 +46,7 @@ static void few_delay(void) ...@@ -46,7 +46,7 @@ static void few_delay(void)
} }
static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit) static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit)
{ {
mSDA_OUT(); mSDA_OUT();
few_delay(); few_delay();
...@@ -114,7 +114,7 @@ static void am_smbus_stop_bit(void) ...@@ -114,7 +114,7 @@ static void am_smbus_stop_bit(void)
static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte) static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte)
{ {
int i; int i;
rt_uint8_t ack_bit; rt_uint8_t ack_bit;
rt_uint8_t bit_out; rt_uint8_t bit_out;
...@@ -162,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u ...@@ -162,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u
int i; int i;
am_smbus_start_bit(); /* Start condition */ am_smbus_start_bit(); /* Start condition */
if(am_smbus_tx_byte(SlaveAddress)) /* Send SlaveAddress and write */ if(am_smbus_tx_byte(SlaveAddress)) /* Send SlaveAddress and write */
return 1; return 1;
......
bsp/apollo2/board/spi.c
浏览文件 @ 92beddf3
...@@ -211,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes ...@@ -211,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
u32TransferSize = 64; u32TransferSize = 64;
am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW);
} }
else else
{ {
...@@ -243,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops = ...@@ -243,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops =
}; };
#ifdef RT_USING_SPI0 #ifdef RT_USING_SPI0
static struct am_spi_bus am_spi_bus_0 = static struct am_spi_bus am_spi_bus_0 =
{ {
{0}, {0},
AM_SPI0_IOM_INST AM_SPI0_IOM_INST
......
bsp/apollo2/board/uart.c
浏览文件 @ 92beddf3
...@@ -150,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf ...@@ -150,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf
else if (cfg->stop_bits == STOP_BITS_2) else if (cfg->stop_bits == STOP_BITS_2)
uart_cfg.bTwoStopBits = true; uart_cfg.bTwoStopBits = true;
if (cfg->parity == PARITY_NONE) if (cfg->parity == PARITY_NONE)
uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE; uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE;
else if (cfg->parity == PARITY_ODD) else if (cfg->parity == PARITY_ODD)
uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD; uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD;
else if (cfg->parity == PARITY_EVEN) else if (cfg->parity == PARITY_EVEN)
uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN; uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN;
uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE; uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE;
......
bsp/asm9260t/applications/application.c
浏览文件 @ 92beddf3
...@@ -4,8 +4,8 @@ ...@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2011-01-13 weety first version * 2011-01-13 weety first version
* 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
*/ */
......
bsp/asm9260t/drivers/usart.c
浏览文件 @ 92beddf3
...@@ -58,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial, ...@@ -58,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial,
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL); RT_ASSERT(cfg != RT_NULL);
uart = (asm_uart_t *)serial->parent.user_data; uart = (asm_uart_t *)serial->parent.user_data;
Hw_UartDisable(uart->port); Hw_UartDisable(uart->port);
Hw_UartReset(uart->port); Hw_UartReset(uart->port);
Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits,
cfg->stop_bits, cfg->parity); cfg->stop_bits, cfg->parity);
Hw_UartEnable(uart->port); Hw_UartEnable(uart->port);
......
bsp/asm9260t/platform/gpio.c
浏览文件 @ 92beddf3
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Date Author Notes * Date Author Notes
* 2015-04-14 ArdaFu first version * 2015-04-14 ArdaFu first version
*/ */
#include "asm9260t.h" #include "asm9260t.h"
#include "rtthread.h" #include "rtthread.h"
......
bsp/asm9260t/platform/interrupt.h
浏览文件 @ 92beddf3
...@@ -15,69 +15,69 @@ ...@@ -15,69 +15,69 @@
// IRQ Source // IRQ Source
#define INT_ARM_COMMRX 0 #define INT_ARM_COMMRX 0
#define INT_ARM_COMMTX 1 #define INT_ARM_COMMTX 1
#define INT_RTC 2 #define INT_RTC 2
#define INT_GPIO0 3 #define INT_GPIO0 3
#define INT_GPIO1 4 #define INT_GPIO1 4
#define INT_GPIO2 5 #define INT_GPIO2 5
#define INT_GPIO3 6 #define INT_GPIO3 6
#define INT_GPIO4_IIS1 7 #define INT_GPIO4_IIS1 7
#define INT_USB0 8 #define INT_USB0 8
#define INT_USB1 9 #define INT_USB1 9
#define INT_USB0_DMA 10 #define INT_USB0_DMA 10
#define INT_USB1_DMA 11 #define INT_USB1_DMA 11
#define INT_MAC 12 #define INT_MAC 12
#define INT_MAC_PMT 13 #define INT_MAC_PMT 13
#define INT_NAND 14 #define INT_NAND 14
#define INT_UART0 15 #define INT_UART0 15
#define INT_UART1 16 #define INT_UART1 16
#define INT_UART2 17 #define INT_UART2 17
#define INT_UART3 18 #define INT_UART3 18
#define INT_UART4 19 #define INT_UART4 19
#define INT_UART5 20 #define INT_UART5 20
#define INT_UART6 21 #define INT_UART6 21
#define INT_UART7 22 #define INT_UART7 22
#define INT_UART8 23 #define INT_UART8 23
#define INT_UART9 24 #define INT_UART9 24
#define INT_I2S0 25 #define INT_I2S0 25
#define INT_I2C0 26 #define INT_I2C0 26
#define INT_I2C1 27 #define INT_I2C1 27
#define INT_CAMIF 28 #define INT_CAMIF 28
#define INT_TIMER0 29 #define INT_TIMER0 29
#define INT_TIMER1 30 #define INT_TIMER1 30
#define INT_TIMER2 31 #define INT_TIMER2 31
#define INT_TIMER3 32 #define INT_TIMER3 32
#define INT_ADC0 33 #define INT_ADC0 33
#define INT_DAC0 34 #define INT_DAC0 34
#define INT_USB0_RESUME_HOSTDISCONNECT 35 #define INT_USB0_RESUME_HOSTDISCONNECT 35
#define INT_USB0_VBUSVALID 36 #define INT_USB0_VBUSVALID 36
#define INT_USB1_RESUME_HOSTDISCONNECT 37 #define INT_USB1_RESUME_HOSTDISCONNECT 37
#define INT_USB1_VBUSVALID 38 #define INT_USB1_VBUSVALID 38
#define INT_DMA0_CH0 39 #define INT_DMA0_CH0 39
#define INT_DMA0_CH1 40 #define INT_DMA0_CH1 40
#define INT_DMA0_CH2 41 #define INT_DMA0_CH2 41
#define INT_DMA0_CH3 42 #define INT_DMA0_CH3 42
#define INT_DMA0_CH4 43 #define INT_DMA0_CH4 43
#define INT_DMA0_CH5 44 #define INT_DMA0_CH5 44
#define INT_DMA0_CH6 45 #define INT_DMA0_CH6 45
#define INT_DMA0_CH7 46 #define INT_DMA0_CH7 46
#define INT_DMA1_CH0 47 #define INT_DMA1_CH0 47
#define INT_DMA1_CH1 48 #define INT_DMA1_CH1 48
#define INT_DMA1_CH2 49 #define INT_DMA1_CH2 49
#define INT_DMA1_CH3 50 #define INT_DMA1_CH3 50
#define INT_DMA1_CH4 51 #define INT_DMA1_CH4 51
#define INT_DMA1_CH5 52 #define INT_DMA1_CH5 52
#define INT_DMA1_CH6 53 #define INT_DMA1_CH6 53
#define INT_DMA1_CH7 54 #define INT_DMA1_CH7 54
#define INT_WATCHDOG 55 #define INT_WATCHDOG 55
#define INT_CAN0 56 #define INT_CAN0 56
#define INT_CAN1 57 #define INT_CAN1 57
#define INT_QEI 58 #define INT_QEI 58
#define INT_MCPWM 59 #define INT_MCPWM 59
#define INT_SPI0 60 #define INT_SPI0 60
#define INT_SPI1 61 #define INT_SPI1 61
#define INT_QUADSPI0 62 #define INT_QUADSPI0 62
#define INT_SSP0 63 #define INT_SSP0 63
#endif #endif
bsp/asm9260t/platform/rt_low_level_init.h
浏览文件 @ 92beddf3
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
*/ */
#ifndef __RT_LOW_LEVEL_INIT_H__ #ifndef __RT_LOW_LEVEL_INIT_H__
#define __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__
/*-------- Stack size of CPU modes -------------------------------------------*/ /*-------- Stack size of CPU modes -------------------------------------------*/
#define UND_STK_SIZE 512 #define UND_STK_SIZE 512
#define SVC_STK_SIZE 4096 #define SVC_STK_SIZE 4096
......
bsp/asm9260t/platform/system_clock.c
浏览文件 @ 92beddf3
...@@ -14,269 +14,269 @@ ...@@ -14,269 +14,269 @@
static rt_list_t clocks; static rt_list_t clocks;
struct clk { struct clk {
char name[32]; char name[32];
rt_uint32_t rate_hz; rt_uint32_t rate_hz;
struct clk *parent; struct clk *parent;
rt_list_t node; rt_list_t node;
}; };
static struct clk clk32k = { static struct clk clk32k = {
"clk32k", "clk32k",
AT91_SLOW_CLOCK, AT91_SLOW_CLOCK,
RT_NULL, RT_NULL,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk main_clk = { static struct clk main_clk = {
"main", "main",
0, 0,
RT_NULL, RT_NULL,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk plla = { static struct clk plla = {
"plla", "plla",
0, 0,
RT_NULL, RT_NULL,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk mck = { static struct clk mck = {
"mck", "mck",
0, 0,
RT_NULL, RT_NULL,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk uhpck = { static struct clk uhpck = {
"uhpck", "uhpck",
0, 0,
RT_NULL, RT_NULL,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk pllb = { static struct clk pllb = {
"pllb", "pllb",
0, 0,
&main_clk, &main_clk,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk udpck = { static struct clk udpck = {
"udpck", "udpck",
0, 0,
&pllb, &pllb,
{RT_NULL, RT_NULL}, {RT_NULL, RT_NULL},
}; };
static struct clk *const standard_pmc_clocks[] = { static struct clk *const standard_pmc_clocks[] = {
// four primary clocks // four primary clocks
&clk32k, &clk32k,
&main_clk, &main_clk,
&plla, &plla,
// MCK // MCK
&mck &mck
}; };
// clocks cannot be de-registered no refcounting necessary // clocks cannot be de-registered no refcounting necessary
struct clk *clk_get(const char *id) struct clk *clk_get(const char *id)
{ {
struct clk *clk; struct clk *clk;
rt_list_t *list; rt_list_t *list;
for (list = (&clocks)->next; list != &clocks; list = list->next) for (list = (&clocks)->next; list != &clocks; list = list->next)
{ {
clk = (struct clk *)rt_list_entry(list, struct clk, node); clk = (struct clk *)rt_list_entry(list, struct clk, node);
if (rt_strcmp(id, clk->name) == 0) if (rt_strcmp(id, clk->name) == 0)
return clk; return clk;
} }
return RT_NULL; return RT_NULL;
} }
rt_uint32_t clk_get_rate(struct clk *clk) rt_uint32_t clk_get_rate(struct clk *clk)
{ {
rt_uint32_t rate; rt_uint32_t rate;
for (;;) { for (;;) {
rate = clk->rate_hz; rate = clk->rate_hz;
if (rate || !clk->parent) if (rate || !clk->parent)
break; break;
clk = clk->parent; clk = clk->parent;
} }
return rate; return rate;
} }
static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
{ {
unsigned mul, div; unsigned mul, div;
div = reg & 0xff; div = reg & 0xff;
mul = (reg >> 16) & 0x7ff; mul = (reg >> 16) & 0x7ff;
if (div && mul) { if (div && mul) {
freq /= div; freq /= div;
freq *= mul + 1; freq *= mul + 1;
} else } else
freq = 0; freq = 0;
return freq; return freq;
} }
static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
{ {
unsigned i, div = 0, mul = 0, diff = 1 << 30; unsigned i, div = 0, mul = 0, diff = 1 << 30;
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
//PLL output max 240 MHz (or 180 MHz per errata) //PLL output max 240 MHz (or 180 MHz per errata)
if (out_freq > 240000000) if (out_freq > 240000000)
goto fail; goto fail;
for (i = 1; i < 256; i++) { for (i = 1; i < 256; i++) {
int diff1; int diff1;
unsigned input, mul1; unsigned input, mul1;
// //
// PLL input between 1MHz and 32MHz per spec, but lower // PLL input between 1MHz and 32MHz per spec, but lower
// frequences seem necessary in some cases so allow 100K. // frequences seem necessary in some cases so allow 100K.
// Warning: some newer products need 2MHz min. // Warning: some newer products need 2MHz min.
// //
input = main_freq / i; input = main_freq / i;
if (input < 100000) if (input < 100000)
continue; continue;
if (input > 32000000) if (input > 32000000)
continue; continue;
mul1 = out_freq / input; mul1 = out_freq / input;
if (mul1 > 2048) if (mul1 > 2048)
continue; continue;
if (mul1 < 2) if (mul1 < 2)
goto fail; goto fail;
diff1 = out_freq - input * mul1; diff1 = out_freq - input * mul1;
if (diff1 < 0) if (diff1 < 0)
diff1 = -diff1; diff1 = -diff1;
if (diff > diff1) { if (diff > diff1) {
diff = diff1; diff = diff1;
div = i; div = i;
mul = mul1; mul = mul1;
if (diff == 0) if (diff == 0)
break; break;
} }
} }
if (i == 256 && diff > (out_freq >> 5)) if (i == 256 && diff > (out_freq >> 5))
goto fail; goto fail;
return ret | ((mul - 1) << 16) | div; return ret | ((mul - 1) << 16) | div;
fail: fail:
return 0; return 0;
} }
static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
{ {
if (pll == &pllb && (reg & AT91_PMC_USB96M)) if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2; return freq / 2;
else else
return freq; return freq;
} }
// PLLB generated USB full speed clock init // PLLB generated USB full speed clock init
static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
{ {
rt_uint32_t at91_pllb_usb_init; rt_uint32_t at91_pllb_usb_init;
// //
// USB clock init: choose 48 MHz PLLB value, // USB clock init: choose 48 MHz PLLB value,
// disable 48MHz clock during usb peripheral suspend. // disable 48MHz clock during usb peripheral suspend.
// //
// REVISIT: assumes MCK doesn't derive from PLLB! // REVISIT: assumes MCK doesn't derive from PLLB!
// //
uhpck.parent = &pllb; uhpck.parent = &pllb;
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
at91_sys_write(AT91_CKGR_PLLBR, 0); at91_sys_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
} }
static struct clk *at91_css_to_clk(unsigned long css) static struct clk *at91_css_to_clk(unsigned long css)
{ {
switch (css) { switch (css) {
case AT91_PMC_CSS_SLOW: case AT91_PMC_CSS_SLOW:
return &clk32k; return &clk32k;
case AT91_PMC_CSS_MAIN: case AT91_PMC_CSS_MAIN:
return &main_clk; return &main_clk;
case AT91_PMC_CSS_PLLA: case AT91_PMC_CSS_PLLA:
return &plla; return &plla;
case AT91_PMC_CSS_PLLB: case AT91_PMC_CSS_PLLB:
return &pllb; return &pllb;
} }
return RT_NULL; return RT_NULL;
} }
#define false 0 #define false 0
#define true 1 #define true 1
int at91_clock_init(rt_uint32_t main_clock) int at91_clock_init(rt_uint32_t main_clock)
{ {
unsigned tmp, freq, mckr; unsigned tmp, freq, mckr;
int i; int i;
int pll_overclock = false; int pll_overclock = false;
// //
// When the bootloader initialized the main oscillator correctly, // When the bootloader initialized the main oscillator correctly,
// there's no problem using the cycle counter. But if it didn't, // there's no problem using the cycle counter. But if it didn't,
// or when using oscillator bypass mode, we must be told the speed // or when using oscillator bypass mode, we must be told the speed
// of the main clock. // of the main clock.
// //
if (!main_clock) { if (!main_clock) {
do { do {
tmp = at91_sys_read(AT91_CKGR_MCFR); tmp = at91_sys_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY)); } while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
} }
main_clk.rate_hz = main_clock; main_clk.rate_hz = main_clock;
// report if PLLA is more than mildly overclocked // report if PLLA is more than mildly overclocked
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
if (plla.rate_hz > 209000000) if (plla.rate_hz > 209000000)
pll_overclock = true; pll_overclock = true;
if (pll_overclock) if (pll_overclock)
;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
at91_pllb_usbfs_clock_init(main_clock); at91_pllb_usbfs_clock_init(main_clock);
// //
// MCK and CPU derive from one of those primary clocks. // MCK and CPU derive from one of those primary clocks.
// For now, assume this parentage won't change. // For now, assume this parentage won't change.
// //
mckr = at91_sys_read(AT91_PMC_MCKR); mckr = at91_sys_read(AT91_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
freq = mck.parent->rate_hz; freq = mck.parent->rate_hz;
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv
// Register the PMC's standard clocks // Register the PMC's standard clocks
rt_list_init(&clocks); rt_list_init(&clocks);
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
rt_list_insert_after(&clocks, &pllb.node); rt_list_insert_after(&clocks, &pllb.node);
rt_list_insert_after(&clocks, &uhpck.node); rt_list_insert_after(&clocks, &uhpck.node);
rt_list_insert_after(&clocks, &udpck.node); rt_list_insert_after(&clocks, &udpck.node);
// MCK and CPU clock are "always on" // MCK and CPU clock are "always on"
//clk_enable(&mck); //clk_enable(&mck);
//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
// freq / 1000000, (unsigned) mck.rate_hz / 1000000, // freq / 1000000, (unsigned) mck.rate_hz / 1000000,
// (unsigned) main_clock / 1000000, // (unsigned) main_clock / 1000000,
// ((unsigned) main_clock % 1000000) / 1000); //cause blocked // ((unsigned) main_clock % 1000000) / 1000); //cause blocked
return 0; return 0;
} }
*/ */
...@@ -284,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock) ...@@ -284,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock)
void rt_hw_clock_init(void) void rt_hw_clock_init(void)
{ {
//at91_clock_init(18432000); //at91_clock_init(18432000);
} }
bsp/asm9260t/platform/uart.c
浏览文件 @ 92beddf3
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Date Author Notes * Date Author Notes
* 2015-04-14 ArdaFu first version * 2015-04-14 ArdaFu first version
*/ */
#include "asm9260t.h" #include "asm9260t.h"
#include "rtthread.h" #include "rtthread.h"
#include "uart.h" #include "uart.h"
......
bsp/asm9260t/platform/uart.h
浏览文件 @ 92beddf3
...@@ -36,16 +36,16 @@ typedef struct ...@@ -36,16 +36,16 @@ typedef struct
volatile rt_uint32_t ISO7816STATUS[4]; volatile rt_uint32_t ISO7816STATUS[4];
} HW_USART_TypeDef; } HW_USART_TypeDef;
#define USART0 ((HW_USART_TypeDef *)UART0_BASE) #define USART0 ((HW_USART_TypeDef *)UART0_BASE)
#define USART1 ((HW_USART_TypeDef *)UART1_BASE) #define USART1 ((HW_USART_TypeDef *)UART1_BASE)
#define USART2 ((HW_USART_TypeDef *)UART2_BASE) #define USART2 ((HW_USART_TypeDef *)UART2_BASE)
#define USART3 ((HW_USART_TypeDef *)UART3_BASE) #define USART3 ((HW_USART_TypeDef *)UART3_BASE)
#define USART4 ((HW_USART_TypeDef *)UART4_BASE) #define USART4 ((HW_USART_TypeDef *)UART4_BASE)
#define USART5 ((HW_USART_TypeDef *)UART5_BASE) #define USART5 ((HW_USART_TypeDef *)UART5_BASE)
#define USART6 ((HW_USART_TypeDef *)UART6_BASE) #define USART6 ((HW_USART_TypeDef *)UART6_BASE)
#define USART7 ((HW_USART_TypeDef *)UART7_BASE) #define USART7 ((HW_USART_TypeDef *)UART7_BASE)
#define USART8 ((HW_USART_TypeDef *)UART8_BASE) #define USART8 ((HW_USART_TypeDef *)UART8_BASE)
#define USART9 ((HW_USART_TypeDef *)UART9_BASE) #define USART9 ((HW_USART_TypeDef *)UART9_BASE)
#define ASM_UART_INTR_RXIS (1UL << 4) #define ASM_UART_INTR_RXIS (1UL << 4)
...@@ -91,7 +91,7 @@ typedef struct ...@@ -91,7 +91,7 @@ typedef struct
extern void Hw_UartDisable(HW_USART_TypeDef* uartBase); extern void Hw_UartDisable(HW_USART_TypeDef* uartBase);
extern void Hw_UartEnable(HW_USART_TypeDef* uartBase); extern void Hw_UartEnable(HW_USART_TypeDef* uartBase);
extern void Hw_UartReset(HW_USART_TypeDef* uartBase); extern void Hw_UartReset(HW_USART_TypeDef* uartBase);
extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate,
int dataBits, int stopBits, int parity); int dataBits, int stopBits, int parity);
extern void Hw_UartInit(int index); extern void Hw_UartInit(int index);
#endif #endif
bsp/at91sam9260/applications/application.c
浏览文件 @ 92beddf3
...@@ -4,8 +4,8 @@ ...@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2011-01-13 weety first version * 2011-01-13 weety first version
*/ */
/** /**
...@@ -34,106 +34,106 @@ static int rt_led_app_init(void); ...@@ -34,106 +34,106 @@ static int rt_led_app_init(void);
int main(void) int main(void)
{ {
int timeout = 0; int timeout = 0;
/* Filesystem Initialization */ /* Filesystem Initialization */
#ifdef RT_USING_DFS #ifdef RT_USING_DFS
{ {
#if defined(RT_USING_DFS_ROMFS) #if defined(RT_USING_DFS_ROMFS)
if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
{ {
rt_kprintf("ROM File System initialized!\n"); rt_kprintf("ROM File System initialized!\n");
} }
else else
rt_kprintf("ROM File System initialzation failed!\n"); rt_kprintf("ROM File System initialzation failed!\n");
#endif #endif
#if defined(RT_USING_DFS_UFFS) #if defined(RT_USING_DFS_UFFS)
{ {
/* mount flash device as flash directory */ /* mount flash device as flash directory */
if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
rt_kprintf("UFFS File System initialized!\n"); rt_kprintf("UFFS File System initialized!\n");
else else
rt_kprintf("UFFS File System initialzation failed!\n"); rt_kprintf("UFFS File System initialzation failed!\n");
} }
#endif #endif
#ifdef RT_USING_SDIO #ifdef RT_USING_SDIO
timeout = 0; timeout = 0;
while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
{ {
rt_thread_delay(1); rt_thread_delay(1);
} }
if (timeout < RT_TICK_PER_SECOND*2) if (timeout < RT_TICK_PER_SECOND*2)
{ {
/* mount sd card fat partition 1 as root directory */ /* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{ {
rt_kprintf("File System initialized!\n"); rt_kprintf("File System initialized!\n");
} }
else else
rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
} }
else else
{ {
rt_kprintf("No SD card found.\n"); rt_kprintf("No SD card found.\n");
} }
#endif #endif
} }
#endif #endif
#ifdef RT_USING_LED #ifdef RT_USING_LED
rt_led_app_init(); rt_led_app_init();
#endif #endif
} }
#ifdef RT_USING_LED #ifdef RT_USING_LED
void rt_led_thread_entry(void* parameter) void rt_led_thread_entry(void* parameter)
{ {
rt_uint8_t cnt = 0; rt_uint8_t cnt = 0;
led_init(); led_init();
while(1) while(1)
{ {
/* light on leds for one second */ /* light on leds for one second */
rt_thread_delay(40); rt_thread_delay(40);
cnt++; cnt++;
if (cnt&0x01) if (cnt&0x01)
led_on(1); led_on(1);
else else
led_off(1); led_off(1);
if (cnt&0x02) if (cnt&0x02)
led_on(2); led_on(2);
else else
led_off(2); led_off(2);
if (cnt&0x04) if (cnt&0x04)
led_on(3); led_on(3);
else else
led_off(3); led_off(3);
} }
} }
#endif #endif
static int rt_led_app_init(void) static int rt_led_app_init(void)
{ {
#ifdef RT_USING_LED #ifdef RT_USING_LED
rt_thread_t led_thread; rt_thread_t led_thread;
#if (RT_THREAD_PRIORITY_MAX == 32) #if (RT_THREAD_PRIORITY_MAX == 32)
led_thread = rt_thread_create("led", led_thread = rt_thread_create("led",
rt_led_thread_entry, RT_NULL, rt_led_thread_entry, RT_NULL,
512, 20, 20); 512, 20, 20);
#else #else
led_thread = rt_thread_create("led", led_thread = rt_thread_create("led",
rt_led_thread_entry, RT_NULL, rt_led_thread_entry, RT_NULL,
512, 200, 20); 512, 200, 20);
#endif #endif
if(led_thread != RT_NULL) if(led_thread != RT_NULL)
rt_thread_startup(led_thread); rt_thread_startup(led_thread);
#endif #endif
return 0; return 0;
} }
/* NFSv3 Initialization */ /* NFSv3 Initialization */
...@@ -141,14 +141,14 @@ static int rt_led_app_init(void) ...@@ -141,14 +141,14 @@ static int rt_led_app_init(void)
#include <dfs_nfs.h> #include <dfs_nfs.h>
void nfs_start(void) void nfs_start(void)
{ {
nfs_init(); nfs_init();
if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
{ {
rt_kprintf("NFSv3 File System initialized!\n"); rt_kprintf("NFSv3 File System initialized!\n");
} }
else else
rt_kprintf("NFSv3 File System initialzation failed!\n"); rt_kprintf("NFSv3 File System initialzation failed!\n");
} }
#include "finsh.h" #include "finsh.h"
......
bsp/at91sam9260/drivers/at91_i2c_gpio.c
浏览文件 @ 92beddf3
...@@ -4,8 +4,8 @@ ...@@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2012-04-25 weety first version * 2012-04-25 weety first version
*/ */
#include <rtdevice.h> #include <rtdevice.h>
...@@ -15,101 +15,101 @@ ...@@ -15,101 +15,101 @@
static void at91_i2c_gpio_init() static void at91_i2c_gpio_init()
{ {
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
} }
static void at91_set_sda(void *data, rt_int32_t state) static void at91_set_sda(void *data, rt_int32_t state)
{ {
if (state) if (state)
{ {
at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
} }
else else
{ {
at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
} }
} }
static void at91_set_scl(void *data, rt_int32_t state) static void at91_set_scl(void *data, rt_int32_t state)
{ {
if (state) if (state)
{ {
at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
} }
else else
{ {
at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
} }
} }
static rt_int32_t at91_get_sda(void *data) static rt_int32_t at91_get_sda(void *data)
{ {
return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
} }
static rt_int32_t at91_get_scl(void *data) static rt_int32_t at91_get_scl(void *data)
{ {
return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
} }
static void at91_udelay (rt_uint32_t us) static void at91_udelay (rt_uint32_t us)
{ {
rt_int32_t i; rt_int32_t i;
for (; us > 0; us--) for (; us > 0; us--)
{ {
i = 50000; i = 50000;
while(i > 0) while(i > 0)
{ {
i--; i--;
} }
} }
} }
static const struct rt_i2c_bit_ops bit_ops = { static const struct rt_i2c_bit_ops bit_ops = {
RT_NULL, RT_NULL,
at91_set_sda, at91_set_sda,
at91_set_scl, at91_set_scl,
at91_get_sda, at91_get_sda,
at91_get_scl, at91_get_scl,
at91_udelay, at91_udelay,
5, 5,
100 100
}; };
int at91_i2c_init(void) int at91_i2c_init(void)
{ {
struct rt_i2c_bus_device *bus; struct rt_i2c_bus_device *bus;
bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
if (bus == RT_NULL)
{
rt_kprintf("rt_malloc failed\n");
return -RT_ENOMEM;
}
bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
if (bus == RT_NULL)
{
rt_kprintf("rt_malloc failed\n");
return -RT_ENOMEM;
}
rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
bus->priv = (void *)&bit_ops; bus->priv = (void *)&bit_ops;
at91_i2c_gpio_init(); at91_i2c_gpio_init();
rt_i2c_bit_add_bus(bus, "i2c0"); rt_i2c_bit_add_bus(bus, "i2c0");
return 0; return 0;
} }
INIT_DEVICE_EXPORT(at91_i2c_init); INIT_DEVICE_EXPORT(at91_i2c_init);
......
bsp/at91sam9260/drivers/at91_mci.c
浏览文件 @ 92beddf3
此差异已折叠。
bsp/at91sam9260/drivers/at91_mci.h
浏览文件 @ 92beddf3
...@@ -11,99 +11,99 @@ ...@@ -11,99 +11,99 @@
#ifndef __AT91_MCI_H__ #ifndef __AT91_MCI_H__
#define __AT91_MCI_H__ #define __AT91_MCI_H__
#define AT91_MCI_CR 0x00 /* Control Register */ #define AT91_MCI_CR 0x00 /* Control Register */
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ #define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ #define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ #define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ #define AT91_MCI_SWRST (1 << 7) /* Software Reset */
#define AT91_MCI_MR 0x04 /* Mode Register */ #define AT91_MCI_MR 0x04 /* Mode Register */
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ #define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ #define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ #define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ #define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
#define AT91_MCI_DTOMUL_1 (0 << 4) #define AT91_MCI_DTOMUL_1 (0 << 4)
#define AT91_MCI_DTOMUL_16 (1 << 4) #define AT91_MCI_DTOMUL_16 (1 << 4)
#define AT91_MCI_DTOMUL_128 (2 << 4) #define AT91_MCI_DTOMUL_128 (2 << 4)
#define AT91_MCI_DTOMUL_256 (3 << 4) #define AT91_MCI_DTOMUL_256 (3 << 4)
#define AT91_MCI_DTOMUL_1K (4 << 4) #define AT91_MCI_DTOMUL_1K (4 << 4)
#define AT91_MCI_DTOMUL_4K (5 << 4) #define AT91_MCI_DTOMUL_4K (5 << 4)
#define AT91_MCI_DTOMUL_64K (6 << 4) #define AT91_MCI_DTOMUL_64K (6 << 4)
#define AT91_MCI_DTOMUL_1M (7 << 4) #define AT91_MCI_DTOMUL_1M (7 << 4)
#define AT91_MCI_SDCR 0x0c /* SD Card Register */ #define AT91_MCI_SDCR 0x0c /* SD Card Register */
#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91_MCI_ARGR 0x10 /* Argument Register */ #define AT91_MCI_ARGR 0x10 /* Argument Register */
#define AT91_MCI_CMDR 0x14 /* Command Register */ #define AT91_MCI_CMDR 0x14 /* Command Register */
#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ #define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ #define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
#define AT91_MCI_RSPTYP_NONE (0 << 6) #define AT91_MCI_RSPTYP_NONE (0 << 6)
#define AT91_MCI_RSPTYP_48 (1 << 6) #define AT91_MCI_RSPTYP_48 (1 << 6)
#define AT91_MCI_RSPTYP_136 (2 << 6) #define AT91_MCI_RSPTYP_136 (2 << 6)
#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ #define AT91_MCI_SPCMD (7 << 8) /* Special Command */
#define AT91_MCI_SPCMD_NONE (0 << 8) #define AT91_MCI_SPCMD_NONE (0 << 8)
#define AT91_MCI_SPCMD_INIT (1 << 8) #define AT91_MCI_SPCMD_INIT (1 << 8)
#define AT91_MCI_SPCMD_SYNC (2 << 8) #define AT91_MCI_SPCMD_SYNC (2 << 8)
#define AT91_MCI_SPCMD_ICMD (4 << 8) #define AT91_MCI_SPCMD_ICMD (4 << 8)
#define AT91_MCI_SPCMD_IRESP (5 << 8) #define AT91_MCI_SPCMD_IRESP (5 << 8)
#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ #define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ #define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ #define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
#define AT91_MCI_TRCMD_NONE (0 << 16) #define AT91_MCI_TRCMD_NONE (0 << 16)
#define AT91_MCI_TRCMD_START (1 << 16) #define AT91_MCI_TRCMD_START (1 << 16)
#define AT91_MCI_TRCMD_STOP (2 << 16) #define AT91_MCI_TRCMD_STOP (2 << 16)
#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ #define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ #define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
#define AT91_MCI_TRTYP_BLOCK (0 << 19) #define AT91_MCI_TRTYP_BLOCK (0 << 19)
#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) #define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
#define AT91_MCI_TRTYP_STREAM (2 << 19) #define AT91_MCI_TRTYP_STREAM (2 << 19)
#define AT91_MCI_BLKR 0x18 /* Block Register */ #define AT91_MCI_BLKR 0x18 /* Block Register */
#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ #define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ #define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
#define AT91_MCR_RDR 0x30 /* Receive Data Register */ #define AT91_MCR_RDR 0x30 /* Receive Data Register */
#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ #define AT91_MCR_TDR 0x34 /* Transmit Data Register */
#define AT91_MCI_SR 0x40 /* Status Register */ #define AT91_MCI_SR 0x40 /* Status Register */
#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ #define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */
#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ #define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */
#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ #define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */
#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ #define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */
#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ #define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */
#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ #define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */
#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ #define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */
#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ #define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */
#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ #define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */
#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ #define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */
#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ #define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */
#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ #define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */
#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ #define AT91_MCI_RINDE (1U << 16) /* Response Index Error */
#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ #define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */
#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ #define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */
#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ #define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */
#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ #define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */
#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ #define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */
#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ #define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */
#define AT91_MCI_OVRE (1U << 30) /* Overrun */ #define AT91_MCI_OVRE (1U << 30) /* Overrun */
#define AT91_MCI_UNRE (1U << 31) /* Underrun */ #define AT91_MCI_UNRE (1U << 31) /* Underrun */
#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ #define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ #define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ #define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
extern int at91_mci_init(void); extern int at91_mci_init(void);
......
bsp/at91sam9260/drivers/board.c
浏览文件 @ 92beddf3
...@@ -40,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); ...@@ -40,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
extern void rt_dbgu_isr(void); extern void rt_dbgu_isr(void);
static struct mem_desc at91_mem_desc[] = { static struct mem_desc at91_mem_desc[] = {
{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */
{ 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */
{ 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */
}; };
#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
static rt_uint32_t pit_cycle; /* write-once */ static rt_uint32_t pit_cycle; /* write-once */
static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
/** /**
* This function will handle rtos timer * This function will handle rtos timer
*/ */
void rt_timer_handler(int vector, void *param) void rt_timer_handler(int vector, void *param)
{ {
#ifdef RT_USING_DBGU #ifdef RT_USING_DBGU
if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
{ {
rt_dbgu_isr(); rt_dbgu_isr();
} }
#endif #endif
if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
{ {
unsigned nr_ticks; unsigned nr_ticks;
/* Get number of ticks performed before irq, and ack it */ /* Get number of ticks performed before irq, and ack it */
nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
rt_tick_increase(); rt_tick_increase();
} }
} }
static void at91sam926x_pit_reset(void) static void at91sam926x_pit_reset(void)
{ {
/* Disable timer and irqs */ /* Disable timer and irqs */
at91_sys_write(AT91_PIT_MR, 0); at91_sys_write(AT91_PIT_MR, 0);
/* Clear any pending interrupts, wait for PIT to stop counting */ /* Clear any pending interrupts, wait for PIT to stop counting */
while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
; ;
/* Start PIT but don't enable IRQ */ /* Start PIT but don't enable IRQ */
//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
| AT91_PIT_PITIEN); | AT91_PIT_PITIEN);
rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
} }
/* /*
...@@ -97,19 +97,19 @@ static void at91sam926x_pit_reset(void) ...@@ -97,19 +97,19 @@ static void at91sam926x_pit_reset(void)
*/ */
static void at91sam926x_pit_init(void) static void at91sam926x_pit_init(void)
{ {
rt_uint32_t pit_rate; rt_uint32_t pit_rate;
rt_uint32_t bits; rt_uint32_t bits;
/* /*
* Use our actual MCK to figure out how many MCK/16 ticks per * Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH). * 1/HZ period (instead of a compile-time constant LATCH).
*/ */
pit_rate = clk_get_rate(clk_get("mck")) / 16; pit_rate = clk_get_rate(clk_get("mck")) / 16;
rt_kprintf("pit_rate=%dHZ\n", pit_rate); rt_kprintf("pit_rate=%dHZ\n", pit_rate);
pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
/* Initialize and enable the timer */ /* Initialize and enable the timer */
at91sam926x_pit_reset(); at91sam926x_pit_reset();
} }
...@@ -118,69 +118,69 @@ static void at91sam926x_pit_init(void) ...@@ -118,69 +118,69 @@ static void at91sam926x_pit_init(void)
*/ */
void rt_hw_timer_init() void rt_hw_timer_init()
{ {
at91sam926x_pit_init(); at91sam926x_pit_init();
/* install interrupt handler */ /* install interrupt handler */
rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
RT_NULL, "system"); RT_NULL, "system");
rt_hw_interrupt_umask(AT91_ID_SYS); rt_hw_interrupt_umask(AT91_ID_SYS);
} }
void at91_tc1_init() void at91_tc1_init()
{ {
at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0); at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR); writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR); writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR); writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV); writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
} }
#define RXRDY 0x01 #define RXRDY 0x01
#define TXRDY (1 << 1) #define TXRDY (1 << 1)
#define BPS 115200 /* serial baudrate */ #define BPS 115200 /* serial baudrate */
typedef struct uartport typedef struct uartport
{ {
volatile rt_uint32_t CR; volatile rt_uint32_t CR;
volatile rt_uint32_t MR; volatile rt_uint32_t MR;
volatile rt_uint32_t IER; volatile rt_uint32_t IER;
volatile rt_uint32_t IDR; volatile rt_uint32_t IDR;
volatile rt_uint32_t IMR; volatile rt_uint32_t IMR;
volatile rt_uint32_t CSR; volatile rt_uint32_t CSR;
volatile rt_uint32_t RHR; volatile rt_uint32_t RHR;
volatile rt_uint32_t THR; volatile rt_uint32_t THR;
volatile rt_uint32_t BRGR; volatile rt_uint32_t BRGR;
volatile rt_uint32_t RTOR; volatile rt_uint32_t RTOR;
volatile rt_uint32_t TTGR; volatile rt_uint32_t TTGR;
volatile rt_uint32_t reserved0[5]; volatile rt_uint32_t reserved0[5];
volatile rt_uint32_t FIDI; volatile rt_uint32_t FIDI;
volatile rt_uint32_t NER; volatile rt_uint32_t NER;
volatile rt_uint32_t reserved1; volatile rt_uint32_t reserved1;
volatile rt_uint32_t IFR; volatile rt_uint32_t IFR;
volatile rt_uint32_t reserved2[44]; volatile rt_uint32_t reserved2[44];
volatile rt_uint32_t RPR; volatile rt_uint32_t RPR;
volatile rt_uint32_t RCR; volatile rt_uint32_t RCR;
volatile rt_uint32_t TPR; volatile rt_uint32_t TPR;
volatile rt_uint32_t TCR; volatile rt_uint32_t TCR;
volatile rt_uint32_t RNPR; volatile rt_uint32_t RNPR;
volatile rt_uint32_t RNCR; volatile rt_uint32_t RNCR;
volatile rt_uint32_t TNPR; volatile rt_uint32_t TNPR;
volatile rt_uint32_t TNCR; volatile rt_uint32_t TNCR;
volatile rt_uint32_t PTCR; volatile rt_uint32_t PTCR;
volatile rt_uint32_t PTSR; volatile rt_uint32_t PTSR;
}uartport; }uartport;
#define CIDR FIDI #define CIDR FIDI
#define EXID NER #define EXID NER
#define FNR reserved1 #define FNR reserved1
#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) #define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU)
static void at91_usart_putc(char c) static void at91_usart_putc(char c)
{ {
while (!(DBGU->CSR & TXRDY)); while (!(DBGU->CSR & TXRDY));
DBGU->THR = c; DBGU->THR = c;
} }
/** /**
...@@ -191,33 +191,33 @@ static void at91_usart_putc(char c) ...@@ -191,33 +191,33 @@ static void at91_usart_putc(char c)
*/ */
void rt_hw_console_output(const char* str) void rt_hw_console_output(const char* str)
{ {
while (*str) while (*str)
{ {
if (*str=='\n') if (*str=='\n')
{ {
at91_usart_putc('\r'); at91_usart_putc('\r');
} }
at91_usart_putc(*str++); at91_usart_putc(*str++);
} }
} }
static void rt_hw_console_init(void) static void rt_hw_console_init(void)
{ {
int div; int div;
int mode = 0; int mode = 0;
DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
AT91_US_RXDIS | AT91_US_TXDIS; AT91_US_RXDIS | AT91_US_TXDIS;
mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
AT91_US_CHMODE_NORMAL; AT91_US_CHMODE_NORMAL;
mode |= AT91_US_CHRL_8; mode |= AT91_US_CHRL_8;
mode |= AT91_US_NBSTOP_1; mode |= AT91_US_NBSTOP_1;
mode |= AT91_US_PAR_NONE; mode |= AT91_US_PAR_NONE;
DBGU->MR = mode; DBGU->MR = mode;
div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
DBGU->BRGR = div; DBGU->BRGR = div;
DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
} }
...@@ -226,31 +226,31 @@ static void rt_hw_console_init(void) ...@@ -226,31 +226,31 @@ static void rt_hw_console_init(void)
*/ */
void rt_hw_board_init() void rt_hw_board_init()
{ {
/* initialize the system clock */ /* initialize the system clock */
rt_hw_clock_init(); rt_hw_clock_init();
/* initialize console */ /* initialize console */
rt_hw_console_init(); rt_hw_console_init();
/* initialize mmu */ /* initialize mmu */
rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
/* initialize hardware interrupt */ /* initialize hardware interrupt */
rt_hw_interrupt_init(); rt_hw_interrupt_init();
/* initialize early device */ /* initialize early device */
#ifdef RT_USING_COMPONENTS_INIT #ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init(); rt_components_board_init();
#endif #endif
#ifdef RT_USING_CONSOLE #ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME); rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif #endif
/* initialize timer0 */ /* initialize timer0 */
rt_hw_timer_init(); rt_hw_timer_init();
/* initialize board */ /* initialize board */
#ifdef RT_USING_HEAP #ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif #endif
} }
......
bsp/at91sam9260/drivers/led.c
浏览文件 @ 92beddf3
...@@ -14,59 +14,59 @@ ...@@ -14,59 +14,59 @@
#if 1 #if 1
// GB9260 board // GB9260 board
#define PIO_LED AT91_PIOB #define PIO_LED AT91_PIOB
#define LED1 (1 << 25) // LED_SYS #define LED1 (1 << 25) // LED_SYS
#define LED2 (0) #define LED2 (0)
#define LED3 (1 << 23) // LED_USR #define LED3 (1 << 23) // LED_USR
#define LED_ALL (LED1 | LED2 | LED3) #define LED_ALL (LED1 | LED2 | LED3)
#else #else
#define PIO_LED AT91_PIOC #define PIO_LED AT91_PIOC
#define LED1 (1 << 8) #define LED1 (1 << 8)
#define LED2 (1 << 11) #define LED2 (1 << 11)
#define LED3 (1 << 6) #define LED3 (1 << 6)
#define LED_ALL (LED1 | LED2 | LED3) #define LED_ALL (LED1 | LED2 | LED3)
#endif #endif
void led_init(void) void led_init(void)
{ {
at91_sys_write(PIO_LED+0x00, LED_ALL); at91_sys_write(PIO_LED+0x00, LED_ALL);
at91_sys_write(PIO_LED+0x10, LED_ALL); at91_sys_write(PIO_LED+0x10, LED_ALL);
at91_sys_write(PIO_LED+0x64, LED_ALL); at91_sys_write(PIO_LED+0x64, LED_ALL);
at91_sys_write(PIO_LED+0x30, LED_ALL); at91_sys_write(PIO_LED+0x30, LED_ALL);
} }
void led_on(int num) void led_on(int num)
{ {
switch(num) switch(num)
{ {
case 1: case 1:
at91_sys_write(PIO_LED+0x34, LED1); at91_sys_write(PIO_LED+0x34, LED1);
break; break;
case 2: case 2:
at91_sys_write(PIO_LED+0x34, LED2); at91_sys_write(PIO_LED+0x34, LED2);
break; break;
case 3: case 3:
at91_sys_write(PIO_LED+0x34, LED3); at91_sys_write(PIO_LED+0x34, LED3);
break; break;
default: default:
break; break;
} }
} }
void led_off(int num) void led_off(int num)
{ {
switch(num) switch(num)
{ {
case 1: case 1:
at91_sys_write(PIO_LED+0x30, LED1); at91_sys_write(PIO_LED+0x30, LED1);
break; break;
case 2: case 2:
at91_sys_write(PIO_LED+0x30, LED2); at91_sys_write(PIO_LED+0x30, LED2);
break; break;
case 3: case 3:
at91_sys_write(PIO_LED+0x30, LED3); at91_sys_write(PIO_LED+0x30, LED3);
break; break;
default: default:
break; break;
} }
} }
bsp/at91sam9260/drivers/macb.c
浏览文件 @ 92beddf3
此差异已折叠。
bsp/at91sam9260/drivers/macb.h
浏览文件 @ 92beddf3
...@@ -12,319 +12,319 @@ ...@@ -12,319 +12,319 @@
#include <mii.h> #include <mii.h>
/* MACB register offsets */ /* MACB register offsets */
#define MACB_NCR 0x0000 #define MACB_NCR 0x0000
#define MACB_NCFGR 0x0004 #define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008 #define MACB_NSR 0x0008
#define MACB_TSR 0x0014 #define MACB_TSR 0x0014
#define MACB_RBQP 0x0018 #define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c #define MACB_TBQP 0x001c
#define MACB_RSR 0x0020 #define MACB_RSR 0x0020
#define MACB_ISR 0x0024 #define MACB_ISR 0x0024
#define MACB_IER 0x0028 #define MACB_IER 0x0028
#define MACB_IDR 0x002c #define MACB_IDR 0x002c
#define MACB_IMR 0x0030 #define MACB_IMR 0x0030
#define MACB_MAN 0x0034 #define MACB_MAN 0x0034
#define MACB_PTR 0x0038 #define MACB_PTR 0x0038
#define MACB_PFR 0x003c #define MACB_PFR 0x003c
#define MACB_FTO 0x0040 #define MACB_FTO 0x0040
#define MACB_SCF 0x0044 #define MACB_SCF 0x0044
#define MACB_MCF 0x0048 #define MACB_MCF 0x0048
#define MACB_FRO 0x004c #define MACB_FRO 0x004c
#define MACB_FCSE 0x0050 #define MACB_FCSE 0x0050
#define MACB_ALE 0x0054 #define MACB_ALE 0x0054
#define MACB_DTF 0x0058 #define MACB_DTF 0x0058
#define MACB_LCOL 0x005c #define MACB_LCOL 0x005c
#define MACB_EXCOL 0x0060 #define MACB_EXCOL 0x0060
#define MACB_TUND 0x0064 #define MACB_TUND 0x0064
#define MACB_CSE 0x0068 #define MACB_CSE 0x0068
#define MACB_RRE 0x006c #define MACB_RRE 0x006c
#define MACB_ROVR 0x0070 #define MACB_ROVR 0x0070
#define MACB_RSE 0x0074 #define MACB_RSE 0x0074
#define MACB_ELE 0x0078 #define MACB_ELE 0x0078
#define MACB_RJA 0x007c #define MACB_RJA 0x007c
#define MACB_USF 0x0080 #define MACB_USF 0x0080
#define MACB_STE 0x0084 #define MACB_STE 0x0084
#define MACB_RLE 0x0088 #define MACB_RLE 0x0088
#define MACB_TPF 0x008c #define MACB_TPF 0x008c
#define MACB_HRB 0x0090 #define MACB_HRB 0x0090
#define MACB_HRT 0x0094 #define MACB_HRT 0x0094
#define MACB_SA1B 0x0098 #define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c #define MACB_SA1T 0x009c
#define MACB_SA2B 0x00a0 #define MACB_SA2B 0x00a0
#define MACB_SA2T 0x00a4 #define MACB_SA2T 0x00a4
#define MACB_SA3B 0x00a8 #define MACB_SA3B 0x00a8
#define MACB_SA3T 0x00ac #define MACB_SA3T 0x00ac
#define MACB_SA4B 0x00b0 #define MACB_SA4B 0x00b0
#define MACB_SA4T 0x00b4 #define MACB_SA4T 0x00b4
#define MACB_TID 0x00b8 #define MACB_TID 0x00b8
#define MACB_TPQ 0x00bc #define MACB_TPQ 0x00bc
#define MACB_USRIO 0x00c0 #define MACB_USRIO 0x00c0
#define MACB_WOL 0x00c4 #define MACB_WOL 0x00c4
/* Bitfields in NCR */ /* Bitfields in NCR */
#define MACB_LB_OFFSET 0 #define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1 #define MACB_LB_SIZE 1
#define MACB_LLB_OFFSET 1 #define MACB_LLB_OFFSET 1
#define MACB_LLB_SIZE 1 #define MACB_LLB_SIZE 1
#define MACB_RE_OFFSET 2 #define MACB_RE_OFFSET 2
#define MACB_RE_SIZE 1 #define MACB_RE_SIZE 1
#define MACB_TE_OFFSET 3 #define MACB_TE_OFFSET 3
#define MACB_TE_SIZE 1 #define MACB_TE_SIZE 1
#define MACB_MPE_OFFSET 4 #define MACB_MPE_OFFSET 4
#define MACB_MPE_SIZE 1 #define MACB_MPE_SIZE 1
#define MACB_CLRSTAT_OFFSET 5 #define MACB_CLRSTAT_OFFSET 5
#define MACB_CLRSTAT_SIZE 1 #define MACB_CLRSTAT_SIZE 1
#define MACB_INCSTAT_OFFSET 6 #define MACB_INCSTAT_OFFSET 6
#define MACB_INCSTAT_SIZE 1 #define MACB_INCSTAT_SIZE 1
#define MACB_WESTAT_OFFSET 7 #define MACB_WESTAT_OFFSET 7
#define MACB_WESTAT_SIZE 1 #define MACB_WESTAT_SIZE 1
#define MACB_BP_OFFSET 8 #define MACB_BP_OFFSET 8
#define MACB_BP_SIZE 1 #define MACB_BP_SIZE 1
#define MACB_TSTART_OFFSET 9 #define MACB_TSTART_OFFSET 9
#define MACB_TSTART_SIZE 1 #define MACB_TSTART_SIZE 1
#define MACB_THALT_OFFSET 10 #define MACB_THALT_OFFSET 10
#define MACB_THALT_SIZE 1 #define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11 #define MACB_NCR_TPF_OFFSET 11
#define MACB_NCR_TPF_SIZE 1 #define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12 #define MACB_TZQ_OFFSET 12
#define MACB_TZQ_SIZE 1 #define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */ /* Bitfields in NCFGR */
#define MACB_SPD_OFFSET 0 #define MACB_SPD_OFFSET 0
#define MACB_SPD_SIZE 1 #define MACB_SPD_SIZE 1
#define MACB_FD_OFFSET 1 #define MACB_FD_OFFSET 1
#define MACB_FD_SIZE 1 #define MACB_FD_SIZE 1
#define MACB_BIT_RATE_OFFSET 2 #define MACB_BIT_RATE_OFFSET 2
#define MACB_BIT_RATE_SIZE 1 #define MACB_BIT_RATE_SIZE 1
#define MACB_JFRAME_OFFSET 3 #define MACB_JFRAME_OFFSET 3
#define MACB_JFRAME_SIZE 1 #define MACB_JFRAME_SIZE 1
#define MACB_CAF_OFFSET 4 #define MACB_CAF_OFFSET 4
#define MACB_CAF_SIZE 1 #define MACB_CAF_SIZE 1
#define MACB_NBC_OFFSET 5 #define MACB_NBC_OFFSET 5
#define MACB_NBC_SIZE 1 #define MACB_NBC_SIZE 1
#define MACB_NCFGR_MTI_OFFSET 6 #define MACB_NCFGR_MTI_OFFSET 6
#define MACB_NCFGR_MTI_SIZE 1 #define MACB_NCFGR_MTI_SIZE 1
#define MACB_UNI_OFFSET 7 #define MACB_UNI_OFFSET 7
#define MACB_UNI_SIZE 1 #define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8 #define MACB_BIG_OFFSET 8
#define MACB_BIG_SIZE 1 #define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9 #define MACB_EAE_OFFSET 9
#define MACB_EAE_SIZE 1 #define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10 #define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2 #define MACB_CLK_SIZE 2
#define MACB_RTY_OFFSET 12 #define MACB_RTY_OFFSET 12
#define MACB_RTY_SIZE 1 #define MACB_RTY_SIZE 1
#define MACB_PAE_OFFSET 13 #define MACB_PAE_OFFSET 13
#define MACB_PAE_SIZE 1 #define MACB_PAE_SIZE 1
#define MACB_RBOF_OFFSET 14 #define MACB_RBOF_OFFSET 14
#define MACB_RBOF_SIZE 2 #define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16 #define MACB_RLCE_OFFSET 16
#define MACB_RLCE_SIZE 1 #define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17 #define MACB_DRFCS_OFFSET 17
#define MACB_DRFCS_SIZE 1 #define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18 #define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1 #define MACB_EFRHD_SIZE 1
#define MACB_IRXFCS_OFFSET 19 #define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1 #define MACB_IRXFCS_SIZE 1
/* Bitfields in NSR */ /* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 #define MACB_NSR_LINK_OFFSET 0
#define MACB_NSR_LINK_SIZE 1 #define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1 #define MACB_MDIO_OFFSET 1
#define MACB_MDIO_SIZE 1 #define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2 #define MACB_IDLE_OFFSET 2
#define MACB_IDLE_SIZE 1 #define MACB_IDLE_SIZE 1
/* Bitfields in TSR */ /* Bitfields in TSR */
#define MACB_UBR_OFFSET 0 #define MACB_UBR_OFFSET 0
#define MACB_UBR_SIZE 1 #define MACB_UBR_SIZE 1
#define MACB_COL_OFFSET 1 #define MACB_COL_OFFSET 1
#define MACB_COL_SIZE 1 #define MACB_COL_SIZE 1
#define MACB_TSR_RLE_OFFSET 2 #define MACB_TSR_RLE_OFFSET 2
#define MACB_TSR_RLE_SIZE 1 #define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3 #define MACB_TGO_OFFSET 3
#define MACB_TGO_SIZE 1 #define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4 #define MACB_BEX_OFFSET 4
#define MACB_BEX_SIZE 1 #define MACB_BEX_SIZE 1
#define MACB_COMP_OFFSET 5 #define MACB_COMP_OFFSET 5
#define MACB_COMP_SIZE 1 #define MACB_COMP_SIZE 1
#define MACB_UND_OFFSET 6 #define MACB_UND_OFFSET 6
#define MACB_UND_SIZE 1 #define MACB_UND_SIZE 1
/* Bitfields in RSR */ /* Bitfields in RSR */
#define MACB_BNA_OFFSET 0 #define MACB_BNA_OFFSET 0
#define MACB_BNA_SIZE 1 #define MACB_BNA_SIZE 1
#define MACB_REC_OFFSET 1 #define MACB_REC_OFFSET 1
#define MACB_REC_SIZE 1 #define MACB_REC_SIZE 1
#define MACB_OVR_OFFSET 2 #define MACB_OVR_OFFSET 2
#define MACB_OVR_SIZE 1 #define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */ /* Bitfields in ISR/IER/IDR/IMR */
#define MACB_MFD_OFFSET 0 #define MACB_MFD_OFFSET 0
#define MACB_MFD_SIZE 1 #define MACB_MFD_SIZE 1
#define MACB_RCOMP_OFFSET 1 #define MACB_RCOMP_OFFSET 1
#define MACB_RCOMP_SIZE 1 #define MACB_RCOMP_SIZE 1
#define MACB_RXUBR_OFFSET 2 #define MACB_RXUBR_OFFSET 2
#define MACB_RXUBR_SIZE 1 #define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3 #define MACB_TXUBR_OFFSET 3
#define MACB_TXUBR_SIZE 1 #define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4 #define MACB_ISR_TUND_OFFSET 4
#define MACB_ISR_TUND_SIZE 1 #define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5 #define MACB_ISR_RLE_OFFSET 5
#define MACB_ISR_RLE_SIZE 1 #define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6 #define MACB_TXERR_OFFSET 6
#define MACB_TXERR_SIZE 1 #define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7 #define MACB_TCOMP_OFFSET 7
#define MACB_TCOMP_SIZE 1 #define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9 #define MACB_ISR_LINK_OFFSET 9
#define MACB_ISR_LINK_SIZE 1 #define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10 #define MACB_ISR_ROVR_OFFSET 10
#define MACB_ISR_ROVR_SIZE 1 #define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11 #define MACB_HRESP_OFFSET 11
#define MACB_HRESP_SIZE 1 #define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12 #define MACB_PFR_OFFSET 12
#define MACB_PFR_SIZE 1 #define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13 #define MACB_PTZ_OFFSET 13
#define MACB_PTZ_SIZE 1 #define MACB_PTZ_SIZE 1
/* Bitfields in MAN */ /* Bitfields in MAN */
#define MACB_DATA_OFFSET 0 #define MACB_DATA_OFFSET 0
#define MACB_DATA_SIZE 16 #define MACB_DATA_SIZE 16
#define MACB_CODE_OFFSET 16 #define MACB_CODE_OFFSET 16
#define MACB_CODE_SIZE 2 #define MACB_CODE_SIZE 2
#define MACB_REGA_OFFSET 18 #define MACB_REGA_OFFSET 18
#define MACB_REGA_SIZE 5 #define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23 #define MACB_PHYA_OFFSET 23
#define MACB_PHYA_SIZE 5 #define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28 #define MACB_RW_OFFSET 28
#define MACB_RW_SIZE 2 #define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30 #define MACB_SOF_OFFSET 30
#define MACB_SOF_SIZE 2 #define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */ /* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0 #define MACB_MII_OFFSET 0
#define MACB_MII_SIZE 1 #define MACB_MII_SIZE 1
#define MACB_EAM_OFFSET 1 #define MACB_EAM_OFFSET 1
#define MACB_EAM_SIZE 1 #define MACB_EAM_SIZE 1
#define MACB_TX_PAUSE_OFFSET 2 #define MACB_TX_PAUSE_OFFSET 2
#define MACB_TX_PAUSE_SIZE 1 #define MACB_TX_PAUSE_SIZE 1
#define MACB_TX_PAUSE_ZERO_OFFSET 3 #define MACB_TX_PAUSE_ZERO_OFFSET 3
#define MACB_TX_PAUSE_ZERO_SIZE 1 #define MACB_TX_PAUSE_ZERO_SIZE 1
/* Bitfields in USRIO (AT91) */ /* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0 #define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1 #define MACB_RMII_SIZE 1
#define MACB_CLKEN_OFFSET 1 #define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1 #define MACB_CLKEN_SIZE 1
/* Bitfields in WOL */ /* Bitfields in WOL */
#define MACB_IP_OFFSET 0 #define MACB_IP_OFFSET 0
#define MACB_IP_SIZE 16 #define MACB_IP_SIZE 16
#define MACB_MAG_OFFSET 16 #define MACB_MAG_OFFSET 16
#define MACB_MAG_SIZE 1 #define MACB_MAG_SIZE 1
#define MACB_ARP_OFFSET 17 #define MACB_ARP_OFFSET 17
#define MACB_ARP_SIZE 1 #define MACB_ARP_SIZE 1
#define MACB_SA1_OFFSET 18 #define MACB_SA1_OFFSET 18
#define MACB_SA1_SIZE 1 #define MACB_SA1_SIZE 1
#define MACB_WOL_MTI_OFFSET 19 #define MACB_WOL_MTI_OFFSET 19
#define MACB_WOL_MTI_SIZE 1 #define MACB_WOL_MTI_SIZE 1
/* Constants for CLK */ /* Constants for CLK */
#define MACB_CLK_DIV8 0 #define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1 #define MACB_CLK_DIV16 1
#define MACB_CLK_DIV32 2 #define MACB_CLK_DIV32 2
#define MACB_CLK_DIV64 3 #define MACB_CLK_DIV64 3
/* Constants for MAN register */ /* Constants for MAN register */
#define MACB_MAN_SOF 1 #define MACB_MAN_SOF 1
#define MACB_MAN_WRITE 1 #define MACB_MAN_WRITE 1
#define MACB_MAN_READ 2 #define MACB_MAN_READ 2
#define MACB_MAN_CODE 2 #define MACB_MAN_CODE 2
/* Bit manipulation macros */ /* Bit manipulation macros */
#define MACB_BIT(name) \ #define MACB_BIT(name) \
(1 << MACB_##name##_OFFSET) (1 << MACB_##name##_OFFSET)
#define MACB_BF(name,value) \ #define MACB_BF(name,value) \
(((value) & ((1 << MACB_##name##_SIZE) - 1)) \ (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
<< MACB_##name##_OFFSET) << MACB_##name##_OFFSET)
#define MACB_BFEXT(name,value)\ #define MACB_BFEXT(name,value)\
(((value) >> MACB_##name##_OFFSET) \ (((value) >> MACB_##name##_OFFSET) \
& ((1 << MACB_##name##_SIZE) - 1)) & ((1 << MACB_##name##_SIZE) - 1))
#define MACB_BFINS(name,value,old) \ #define MACB_BFINS(name,value,old) \
(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
<< MACB_##name##_OFFSET)) \ << MACB_##name##_OFFSET)) \
| MACB_BF(name,value)) | MACB_BF(name,value))
/* Register access macros */ /* Register access macros */
#define macb_readl(port,reg) \ #define macb_readl(port,reg) \
readl((port)->regs + MACB_##reg) readl((port)->regs + MACB_##reg)
#define macb_writel(port,reg,value) \ #define macb_writel(port,reg,value) \
writel((value), (port)->regs + MACB_##reg) writel((value), (port)->regs + MACB_##reg)
struct dma_desc { struct dma_desc {
rt_uint32_t addr; rt_uint32_t addr;
rt_uint32_t ctrl; rt_uint32_t ctrl;
}; };
/* DMA descriptor bitfields */ /* DMA descriptor bitfields */
#define MACB_RX_USED_OFFSET 0 #define MACB_RX_USED_OFFSET 0
#define MACB_RX_USED_SIZE 1 #define MACB_RX_USED_SIZE 1
#define MACB_RX_WRAP_OFFSET 1 #define MACB_RX_WRAP_OFFSET 1
#define MACB_RX_WRAP_SIZE 1 #define MACB_RX_WRAP_SIZE 1
#define MACB_RX_WADDR_OFFSET 2 #define MACB_RX_WADDR_OFFSET 2
#define MACB_RX_WADDR_SIZE 30 #define MACB_RX_WADDR_SIZE 30
#define MACB_RX_FRMLEN_OFFSET 0 #define MACB_RX_FRMLEN_OFFSET 0
#define MACB_RX_FRMLEN_SIZE 12 #define MACB_RX_FRMLEN_SIZE 12
#define MACB_RX_OFFSET_OFFSET 12 #define MACB_RX_OFFSET_OFFSET 12
#define MACB_RX_OFFSET_SIZE 2 #define MACB_RX_OFFSET_SIZE 2
#define MACB_RX_SOF_OFFSET 14 #define MACB_RX_SOF_OFFSET 14
#define MACB_RX_SOF_SIZE 1 #define MACB_RX_SOF_SIZE 1
#define MACB_RX_EOF_OFFSET 15 #define MACB_RX_EOF_OFFSET 15
#define MACB_RX_EOF_SIZE 1 #define MACB_RX_EOF_SIZE 1
#define MACB_RX_CFI_OFFSET 16 #define MACB_RX_CFI_OFFSET 16
#define MACB_RX_CFI_SIZE 1 #define MACB_RX_CFI_SIZE 1
#define MACB_RX_VLAN_PRI_OFFSET 17 #define MACB_RX_VLAN_PRI_OFFSET 17
#define MACB_RX_VLAN_PRI_SIZE 3 #define MACB_RX_VLAN_PRI_SIZE 3
#define MACB_RX_PRI_TAG_OFFSET 20 #define MACB_RX_PRI_TAG_OFFSET 20
#define MACB_RX_PRI_TAG_SIZE 1 #define MACB_RX_PRI_TAG_SIZE 1
#define MACB_RX_VLAN_TAG_OFFSET 21 #define MACB_RX_VLAN_TAG_OFFSET 21
#define MACB_RX_VLAN_TAG_SIZE 1 #define MACB_RX_VLAN_TAG_SIZE 1
#define MACB_RX_TYPEID_MATCH_OFFSET 22 #define MACB_RX_TYPEID_MATCH_OFFSET 22
#define MACB_RX_TYPEID_MATCH_SIZE 1 #define MACB_RX_TYPEID_MATCH_SIZE 1
#define MACB_RX_SA4_MATCH_OFFSET 23 #define MACB_RX_SA4_MATCH_OFFSET 23
#define MACB_RX_SA4_MATCH_SIZE 1 #define MACB_RX_SA4_MATCH_SIZE 1
#define MACB_RX_SA3_MATCH_OFFSET 24 #define MACB_RX_SA3_MATCH_OFFSET 24
#define MACB_RX_SA3_MATCH_SIZE 1 #define MACB_RX_SA3_MATCH_SIZE 1
#define MACB_RX_SA2_MATCH_OFFSET 25 #define MACB_RX_SA2_MATCH_OFFSET 25
#define MACB_RX_SA2_MATCH_SIZE 1 #define MACB_RX_SA2_MATCH_SIZE 1
#define MACB_RX_SA1_MATCH_OFFSET 26 #define MACB_RX_SA1_MATCH_OFFSET 26
#define MACB_RX_SA1_MATCH_SIZE 1 #define MACB_RX_SA1_MATCH_SIZE 1
#define MACB_RX_EXT_MATCH_OFFSET 28 #define MACB_RX_EXT_MATCH_OFFSET 28
#define MACB_RX_EXT_MATCH_SIZE 1 #define MACB_RX_EXT_MATCH_SIZE 1
#define MACB_RX_UHASH_MATCH_OFFSET 29 #define MACB_RX_UHASH_MATCH_OFFSET 29
#define MACB_RX_UHASH_MATCH_SIZE 1 #define MACB_RX_UHASH_MATCH_SIZE 1
#define MACB_RX_MHASH_MATCH_OFFSET 30 #define MACB_RX_MHASH_MATCH_OFFSET 30
#define MACB_RX_MHASH_MATCH_SIZE 1 #define MACB_RX_MHASH_MATCH_SIZE 1
#define MACB_RX_BROADCAST_OFFSET 31 #define MACB_RX_BROADCAST_OFFSET 31
#define MACB_RX_BROADCAST_SIZE 1 #define MACB_RX_BROADCAST_SIZE 1
#define MACB_TX_FRMLEN_OFFSET 0 #define MACB_TX_FRMLEN_OFFSET 0
#define MACB_TX_FRMLEN_SIZE 11 #define MACB_TX_FRMLEN_SIZE 11
#define MACB_TX_LAST_OFFSET 15 #define MACB_TX_LAST_OFFSET 15
#define MACB_TX_LAST_SIZE 1 #define MACB_TX_LAST_SIZE 1
#define MACB_TX_NOCRC_OFFSET 16 #define MACB_TX_NOCRC_OFFSET 16
#define MACB_TX_NOCRC_SIZE 1 #define MACB_TX_NOCRC_SIZE 1
#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
#define MACB_TX_BUF_EXHAUSTED_SIZE 1 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
#define MACB_TX_UNDERRUN_OFFSET 28 #define MACB_TX_UNDERRUN_OFFSET 28
#define MACB_TX_UNDERRUN_SIZE 1 #define MACB_TX_UNDERRUN_SIZE 1
#define MACB_TX_ERROR_OFFSET 29 #define MACB_TX_ERROR_OFFSET 29
#define MACB_TX_ERROR_SIZE 1 #define MACB_TX_ERROR_SIZE 1
#define MACB_TX_WRAP_OFFSET 30 #define MACB_TX_WRAP_OFFSET 30
#define MACB_TX_WRAP_SIZE 1 #define MACB_TX_WRAP_SIZE 1
#define MACB_TX_USED_OFFSET 31 #define MACB_TX_USED_OFFSET 31
#define MACB_TX_USED_SIZE 1 #define MACB_TX_USED_SIZE 1
extern int rt_hw_macb_init(); extern int rt_hw_macb_init();
......
bsp/at91sam9260/drivers/mii.h
浏览文件 @ 92beddf3
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
#define MII_EXPANSION 0x06 /* Expansion register */ #define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */ #define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
/* Basic mode control register. */ /* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */ #define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
...@@ -56,7 +56,7 @@ ...@@ -56,7 +56,7 @@
#define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */ #define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
...@@ -85,7 +85,7 @@ ...@@ -85,7 +85,7 @@
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA) ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL) ADVERTISE_100HALF | ADVERTISE_100FULL)
...@@ -107,8 +107,8 @@ ...@@ -107,8 +107,8 @@
#define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */ #define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */ /* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
...@@ -118,8 +118,8 @@ ...@@ -118,8 +118,8 @@
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */ #define EXPANSION_RESV 0xffe0 /* Unused... */
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */ /* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */ #define NWAYTEST_RESV1 0x00ff /* Unused... */
...@@ -137,8 +137,8 @@ ...@@ -137,8 +137,8 @@
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
/* Flow control flags */ /* Flow control flags */
#define FLOW_CTRL_TX 0x01 #define FLOW_CTRL_TX 0x01
#define FLOW_CTRL_RX 0x02 #define FLOW_CTRL_RX 0x02
/** /**
* mii_nway_result * mii_nway_result
......
bsp/at91sam9260/drivers/usart.c
浏览文件 @ 92beddf3
此差异已折叠。
bsp/at91sam9260/platform/at91_aic.h
浏览文件 @ 92beddf3
...@@ -15,41 +15,41 @@ ...@@ -15,41 +15,41 @@
extern "C" { extern "C" {
#endif #endif
#define AIC_IRQS 32 #define AIC_IRQS 32
#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
#define AT91_AIC_SRCTYPE_LOW (0 << 5) #define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5) #define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5) #define AT91_AIC_SRCTYPE_HIGH (2 << 5)
#define AT91_AIC_SRCTYPE_RISING (3 << 5) #define AT91_AIC_SRCTYPE_RISING (3 << 5)
#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
#ifdef __cplusplus #ifdef __cplusplus
} }
......
bsp/at91sam9260/platform/at91_pdc.h
浏览文件 @ 92beddf3
...@@ -11,21 +11,21 @@ ...@@ -11,21 +11,21 @@
#ifndef __AT91_PDC_H__ #ifndef __AT91_PDC_H__
#define __AT91_PDC_H__ #define __AT91_PDC_H__
#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ #define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
#define AT91_PDC_RCR 0x104 /* Receive Counter Register */ #define AT91_PDC_RCR 0x104 /* Receive Counter Register */
#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */ #define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */ #define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */ #define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */ #define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */ #define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */ #define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */ #define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */ #define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */ #define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */ #define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */ #define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */ #define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
#endif #endif
bsp/at91sam9260/platform/at91_pio.h
浏览文件 @ 92beddf3
...@@ -16,35 +16,35 @@ ...@@ -16,35 +16,35 @@
extern "C" { extern "C" {
#endif #endif
#define PIO_PER 0x00 /* Enable Register */ #define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */ #define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */ #define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */ #define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */ #define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */ #define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */ #define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */ #define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */ #define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */ #define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */ #define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */ #define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */ #define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */ #define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */ #define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */ #define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */ #define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */ #define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */ #define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */ #define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */ #define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */ #define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */ #define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */ #define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */ #define PIO_OWSR 0xa8 /* Output Write Status Register */
#ifdef __cplusplus #ifdef __cplusplus
} }
......
bsp/at91sam9260/platform/at91_pit.h
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...@@ -15,18 +15,18 @@ ...@@ -15,18 +15,18 @@
extern "C" { extern "C" {
#endif #endif
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ #define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */ #define AT91_PIT_PITS (1 << 0) /* Timer Status */
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ #define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ #define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
#ifdef __cplusplus #ifdef __cplusplus
} }
......
bsp/at91sam9260/platform/at91_pmc.h
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bsp/at91sam9260/platform/at91_rstc.h
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...@@ -15,27 +15,27 @@ ...@@ -15,27 +15,27 @@
extern "C" { extern "C" {
#endif #endif
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) #define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
#define AT91_RSTC_RSTTYP_USER (4 << 8) #define AT91_RSTC_RSTTYP_USER (4 << 8)
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
#ifdef __cplusplus #ifdef __cplusplus
} }
......
bsp/at91sam9260/platform/at91_shdwc.h
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extern "C" { extern "C" {
#endif #endif
#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ #define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
#define AT91_SHDW_WKMODE0_NONE 0 #define AT91_SHDW_WKMODE0_NONE 0
#define AT91_SHDW_WKMODE0_HIGH 1 #define AT91_SHDW_WKMODE0_HIGH 1
#define AT91_SHDW_WKMODE0_LOW 2 #define AT91_SHDW_WKMODE0_LOW 2
#define AT91_SHDW_WKMODE0_ANYLEVEL 3 #define AT91_SHDW_WKMODE0_ANYLEVEL 3
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
#define AT91_SHDW_CPTWK0_(x) ((x) << 4) #define AT91_SHDW_CPTWK0_(x) ((x) << 4)
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ #define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
#ifdef __cplusplus #ifdef __cplusplus
} }
......
bsp/at91sam9260/platform/at91_tc.h
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bsp/at91sam9260/platform/gpio.h
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bsp/at91sam9260/platform/interrupt.c
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...@@ -175,7 +175,7 @@ static void at91_gpio_irq_init() ...@@ -175,7 +175,7 @@ static void at91_gpio_irq_init()
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
irq_desc[idx].counter = 0; irq_desc[idx].counter = 0;
#endif #endif
idx++; idx++;
} }
rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA); rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
...@@ -308,7 +308,7 @@ void rt_hw_interrupt_umask(int irq) ...@@ -308,7 +308,7 @@ void rt_hw_interrupt_umask(int irq)
* @param name the interrupt name * @param name the interrupt name
* @return old handler * @return old handler
*/ */
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name) void *param, const char *name)
{ {
rt_isr_handler_t old_handler = RT_NULL; rt_isr_handler_t old_handler = RT_NULL;
...@@ -322,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, ...@@ -322,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
irq_desc[vector].param = param; irq_desc[vector].param = param;
#ifdef RT_USING_INTERRUPT_INFO #ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
irq_desc[vector].counter = 0; irq_desc[vector].counter = 0;
#endif #endif
} }
} }
...@@ -400,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) ...@@ -400,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
#ifdef RT_USING_INTERRUPT_INFO #ifdef RT_USING_INTERRUPT_INFO
void list_irq(void) void list_irq(void)
{ {
int irq; int irq;
rt_kprintf("number\tcount\tname\n"); rt_kprintf("number\tcount\tname\n");
for (irq = 0; irq < MAX_HANDLERS; irq++) for (irq = 0; irq < MAX_HANDLERS; irq++)
{ {
if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
{ {
rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
} }
} }
} }
#include <finsh.h> #include <finsh.h>
......
bsp/at91sam9260/platform/io.h
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bsp/at91sam9260/platform/irq.h
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bsp/at91sam9260/platform/reset.c
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bsp/at91sam9260/platform/rt_low_level_init.c
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* Date Author Notes * Date Author Notes
* 2015-04-14 ArdaFu first version * 2015-04-14 ArdaFu first version
*/ */
/* write register a=address, v=value */ /* write register a=address, v=value */
#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) #define write_reg(a,v) (*(volatile unsigned int *)(a) = (v))
/* Processor Reset */ /* Processor Reset */
#define AT91_RSTC_PROCRST (1 << 0) #define AT91_RSTC_PROCRST (1 << 0)
#define AT91_RSTC_PERRST (1 << 2) #define AT91_RSTC_PERRST (1 << 2)
......
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bsp/bf533/rtconfig.h
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bsp/dm365/platform/irqs.h
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bsp/dm365/platform/psc.c
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bsp/dm365/platform/reset.c
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bsp/dm365/platform/system_clock.c
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bsp/dm365/platform/trap.c
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bsp/efm32/application.c
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bsp/efm32/board.c
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bsp/efm32/board.h
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bsp/efm32/copy_this_file_dfs_elm.c
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bsp/efm32/copy_this_file_shell.c
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bsp/efm32/dev_keys.c
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bsp/efm32/dev_keys.h
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bsp/efm32/dev_lcd.c
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bsp/efm32/dev_sflash.h
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bsp/efm32/drv_adc.c
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bsp/efm32/drv_adc.h
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bsp/efm32/drv_emu.c
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bsp/efm32/drv_emu.h
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bsp/efm32/drv_ethernet.c
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bsp/efm32/drv_ethernet.h
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bsp/efm32/drv_leuart.c
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bsp/efm32/drv_leuart.h
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bsp/efm32/drv_rtc.c
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bsp/efm32/drv_rtc.h
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bsp/efm32/drv_sdcard.h
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bsp/efm32/drv_timer.c
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bsp/efm32/drv_usart.c
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bsp/efm32/enc28j60.h
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bsp/efm32/graphics/tftspi.h
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bsp/efm32/hdl_interrupt.c
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bsp/efm32/hdl_interrupt.h
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bsp/efm32/httpd.c
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bsp/efm32/mma7455l.h
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bsp/efm32/startup.c
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bsp/frdm-k64f/board/board.c
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bsp/frdm-k64f/board/drv_uart.c
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bsp/frdm-k64f/board/drv_uart.h
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bsp/frdm-k64f/board/led.c
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bsp/frdm-k64f/board/led.h
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bsp/frdm-k64f/rtconfig.h
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bsp/gd32303e-eval/drivers/board.c
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bsp/gd32303e-eval/drivers/drv_i2c.c
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bsp/gd32450z-eval/drivers/drv_lcd.c
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bsp/hifive1/applications/main.c
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bsp/imx6sx/cortex-a9/cpu/cpu.c
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bsp/imx6ul/applications/startup.c
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bsp/nuvoton_m451/drivers/board.c
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bsp/nuvoton_m451/drivers/led.h
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bsp/nuvoton_m451/drivers/usart.c
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bsp/nuvoton_m487/applications/mnt.c
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bsp/nuvoton_m487/driver/board.c
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bsp/nuvoton_m487/driver/drv_emac.c
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bsp/nuvoton_m487/driver/drv_qspi.c
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bsp/nuvoton_nuc472/rtconfig.h
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bsp/nv32f100x/app/src/ledapp.c
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bsp/pic32ethernet/application.c
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bsp/simulator/pcap/pcap_netif.c
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bsp/tm4c129x/applications/board.c
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bsp/w60x/drivers/drv_soft_i2c.c
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bsp/xplorer4330/drivers/drv_uart.c
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